INTRINSIC process parameter fluctuations cause undesirable

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability Kedar Patel, Senior Member, IEEE, Tsu-Jae King Liu, Fellow, IEEE, and Costas J. Spanos, Fellow, IEEE Abstract We present a model for estimating the impact of gate line edge roughness (LER) on the performance of doublegate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (ξ), rms amplitude or standard deviation (σ) of the line edge from its mean value, and roughness exponent (α). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates. Index Terms Double gate (DG), FinFET, intrinsic parameter fluctuation, line edge roughness (LER), variability. I. INTRODUCTION INTRINSIC process parameter fluctuations cause undesirable performance mismatch in identically designed transistors. As the dimensions of the transistors are scaled down, this mismatch increases and, hence, has greater impact on the circuit performance and yield. The primary sources of transistor performance variability that have emerged are line edge roughness (LER), gate dielectric thickness (t ox ) variation, random dopant fluctuations (RDFs), and metal-gate work function (WFV) [1], [2]. Advanced transistor structures such as the double-gate (DG) FinFET [3] are more robust to t ox variation and RDF because a thin body is used to suppress short-channel effects (SCEs), without the need for channel/body doping. In a recent study, FinFETs have been found to have lower threshold voltage variability due to LER [4]. Due to the challenges with scaling planar bulk MOSFETs, advanced structures such as FinFET may be adopted as early as the 25-nm CMOS technology node [5]. Manuscript received March 24, 2009; revised August 14, First published October 30, 2009; current version published November 20, This work was supported in part by FLCC/IMPACT, an industry and academia alliance with support from the UC Discovery Grant Program. The review of this paper was arranged by Editor D. Esseni. K. Patel is with SanDisk Corporation, Milpitas, CA USA, and also with the University of California, Berkeley, CA USA ( kedar. patel@sandisk.com). T.-J. K. Liu and C. J. Spanos are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED LER is stochastic and is affected by many factors during pattern definition. It is a fundamental consequence of resist processing: Erosion of polymer aggregates at the edges of a resist during development has been shown to create a rough profile [6], [7]. In this paper, we examine the impact of LER on FinFET performance. Earlier work on understanding the effects of LER on device performance was either focused on planar bulk CMOS [8] or followed a computationally expensive Monte Carlo (MC) approach [9]. Due to the stochastic nature of LER, an accurate estimate of device performance variability can only be achieved through a full MC 3-D device simulation. However, this computational approach is prohibitively expensive and does not provide insight into how LER impacts device performance. Our premise is that LER manifests itself in the form of offset between the front gate (FG) and the back gate (BG), as well as the difference in FG and BG critical dimensions. As such, we believe that the 2-D transistor structure is sufficient to capture the effects due mismatched FG and BG. Therefore, in this paper, we develop a computationally efficient statistical model that is formulated to link the characteristic LER descriptors to device performance variability. The organization of this paper is as follows: In Section II, we provide a brief background on LER and its characteristic descriptors. In Section III, we describe the details of the 2-D device simulation and the formulation of our model. The simulated device structure is designed to meet the ITRS specifications for the 32-nm high-performance (HP) CMOS technology node. Finally, in Section IV, we discuss the results of our work. The impact of gate length variation and lateral offset between the FG and BG is studied. Sensitivity of key performance parameters such as saturation threshold voltage (V t,sat ), ON-state saturation drive current (I d,sat ), and OFF-state leakage current (I off ) to the various LER parameters is discussed. II. LER A. Background LER and linewidth roughness (LWR) are often used synonymously. Mathematically, they are related but different. As shown in Fig. 1, LER refers to the fluctuations of a given line edge about its mean value, whereas LWR corresponds to fluctuations in a linewidth about its own mean value. For a line sampled at N points along the width W, LWR is described by the variance in the linewidth as σ 2 LWR =(N 1) 1 N i=1 (L i L) 2. (1) /$ IEEE

2 3056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009 Fig. 1. LER is the fluctuation of a line about its mean value for a given edge. LWR is the fluctuation of a linewidth L i about its mean value L averaged over the width W. LWR can also be described in terms of variability of each individual edge as σ 2 LWR = σ 2 L + σ 2 R 2ρ X σ L σ R (2) where the subscripts L and R refer to the left and right edges of a line, respectively, and ρ X is the cross-correlation coefficient between them. The value of ρ X depends primarily on the method of line formation, as will be described later in this paper. If we assume that then we can simplify (2) to σ L = σ R σ LER (3) σ 2 LWR = 2σ 2 LER(1 ρ X ). (4) The variance or, alternately, the sigma value does not provide a complete description of LER [10], [11]. The shortfall of the sigma value arises primarily due to the spatial spectral content of roughness along the edge. In order to capture that spectral content, we invoke the formulation of the autocorrelation function, which describes the correlation between points of a stationary random process such as the one that is responsible for LWR formation. For a stationary LWR profile, the autocorrelation between two points is only a function of distance (or lag ) between them. Similarly, for a jointly stationary LWR profile, the cross-correlation coefficient described in (4) is also only a function of the lag between them. In describing LWR, it is convenient to approximate the autocorrelation coefficient with a closed-form expression given by [12] ρ A (y) = exp [ (y/ξ) 2α] (5) where y is the lag, ξ is the correlation length, and α is the roughness exponent. The correlation length denotes the distance beyond which the amplitudes of two points along an edge can be considered almost uncorrelated. The roughness exponent is a relative measure of the high-frequency component in the roughness; larger values correspond to fewer high-frequency amplitude variations. The simulated effect of each parameter on roughness is shown in Fig. 2. The algorithm used to generate the LWR profiles in this paper is briefly as follows: The power spectrum in (5) and the Gaussian noise are convolved in the frequency domain to obtain the Fourier transform of the output edge; the output edge in the spatial domain is obtained by performing a subsequent inverse Fourier transform. In generating an LWR profile, proper care must be taken to avoid sampling near the edge of the profile due to artifacts of discrete FFT on a finite series. It should be pointed out that (5) represents just one form of a plausible autocorrelation function. Other forms such as exponentially decaying sinusoid can also be used [13]. In this paper, we follow the convention introduced in [12], and we, therefore, assume that LWR can completely be described by three parameters: correlation length (ξ), rms amplitude or standard deviation (σ) of the line edge from its mean value, and roughness exponent (α) [10], [11]. B. Spacer Versus Resist Lithography In a FinFET fabrication process, the gate electrode can be defined in one of two ways: using a resist as the mask ( resistdefined ) and using a spacer as the mask ( spacer-defined ). Conventional resist-defined lines produce edges with uncorrelated roughness, and ρ X = 0 can be assumed in (4). This is due to a fact that erosion of polymer aggregates is a random process for each resist edge. In contrast, spacer-defined lines have line edges that are well correlated. This is because a spacer mask is formed along the sidewall of a dummy resist-defined feature via a conformal thin-film deposition process followed by a highly uniform anisotropic etch process [Fig. 3(a)]. If the spacer width (corresponding to the thickness of the deposited film) is much smaller than the inverse of the LWR spatial cutoff frequency, the spacer-defined lines will have a uniform width, and ρ X = 1 can be assumed in (4). It should be noted that resist pattern transfer to an underlying layer acts a low-pass filter [14] so that the LWR of a patterned film will have reduced high-spatial-frequency components as compared to the resist that was used to define it. For a bulk MOSFET structure, gate LWR affects device performance because the gate length (L g ) is modulated along the width of the channel. Several approaches to modeling this effect have been reported in literature; slice approximation presented by Oldiges et al. [15] and full 3-D device simulation [8], [9], and [16] are the most commonly used. In the slice approximation approach, gate LWR is approximated by regularly sampling L g along the width of the channel and modeling the transistor as a parallel combination of individual transistors with the channel width equal to the sampling interval and the L g values corresponding to the sampled values. (Gate LWR is zero for each individual transistor.) This approach can yield reasonably accurate estimations of performance parameters for planar bulk MOSFETs. Unfortunately, it is not applicable to the FinFET structure because the channel length (along the fin sidewalls) is not impacted by gate LWR in the same manner. III. SIMULATION DETAILS AND MODEL FORMULATION A. FinFET Structure A FinFET can be formed in a straightforward manner by first patterning a silicon-on-insulator layer of thickness h fin into a

3 PATEL et al.: GATE LINE EDGE ROUGHNESS MODEL FOR ESTIMATION OF FinFET PERFORMANCE VARIABILITY 3057 Fig. 2. Illustration of the impact of (a) rms amplitude or standard deviation (σ), (b) autocorrelation length (ξ), and (c) roughness exponent (α) on LER. Note the differences in the oscillatory behavior of the peaks in (b). In (c), the lower value of α contributes higher frequency components of roughness. Fig. 3. Illustration of methods of defining gates with (a) identical (and therefore correlated) edges and (b) uncorrelated edges. narrow fin of width t fin and height h fin. After the gate stack layers are grown or deposited, either a resist or a spacer is used to define the gate electrode that crosses over the active area (i.e., the fin). After the gate layer is etched using the resist or spacer mask, the resultant gate electrode straddles the fin to gate the channels along the front and back fin sidewalls. The fin height h fin, thus, determines the effective width of both the front and back channels of the transistor. Fig. 4 shows how LWR affects both the fin and the gate in a FinFET structure. If a thin gate dielectric (rather than a thick dielectric hard mask) exists between the gate and the top surface of the fin, a channel can also be formed along the top surface of the fin. In this case, the FinFET may be considered as a parallel combination of three FETs with channels along the front, back, and top fin surfaces. The top FET has a smooth channel surface but has nonuniform L g due to gate LWR. In contrast, the front and back FETs have a rough channel surface due to fin LWR but relatively uniform L g (dependent on the gate-etch process). Fin-sidewall roughness can significantly degrade carrier mobility due to surface scattering. Fortunately, the sidewall surfaces and fin corners can be smoothened prior to gate stack formation by a suitable thermal anneal to improve carrier mobility, reduce gate leakage current, and improve device reliability [17], [18]. Additionally, it has been shown that fin Fig. 4. Illustration of the fin LER and gate LER components in a tri-gate FinFET. The magnitude of LER is exaggerated here for illustration purposes. (a) FinFET with LER, (b) electrical diagram showing three transistors, and (c) bulk CMOS equivalent component transistors are shown separately to distinguish the difference in effects of the two LER components. LWR primarily affects the device performance by changing the average fin width in the channel region [9]. Thus, in this paper, we focus primarily on gate LWR. The fin width must be smaller than the effective channel length in order to suppress SCEs without the need for heavy fin/body doping. Indeed, light fin/body doping is desirable to minimize variability due to the RDF effects. In this case, the volume of the fin is inverted when the FinFET is turned on [19] so that the current flows in the body of the fin rather than at the fin surfaces. Consequently, gating of the top fin surface (i.e., the top FET) contributes negligibly to the OFF-state leakage and ON-state drive current [20]. Therefore, in this paper, we focus only on the DG FinFET performance. Fig. 5 shows how gate LWR can result in different L g values and misalignment between the FG and BG. The gate length values for the FG and BG (L fg and L bg, respectively) are determined by sampling the autocorrelated LWR function along each edge of the gate electrode at the front and back surfaces of the fin; thus, the locations of points 1 4 are affected by the fin width since it determines the sampling distance. Although the primary criterion for the choice of

4 3058 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009 Fig. 5. Schematic views of a DG FinFET: (a) Top view of a FinFET. (b) Threedimensional top view of a FinFET illustrating various gate electrode features. The FG and BG lengths and placements are defined by the points labeled 1 4, where the gate electrode wraps around the top of the fin. TABLE I TWO-DIMENSIONAL DEVICE SIMULATION PARAMETERS fin width (t fin ) is SCE control, mitigation of the gate LWR effects to reduce variability may be an important secondary consideration. As discussed earlier, spacer-defined lines have highly correlated edges so that gate length variations are negligible if spacer lithography is used to pattern the gate electrode. Nevertheless, the FG and BG can be misaligned. Thus, it is important to also study the case where the FG and BG have the same gate length but are offset by some distance. If a highly anisotropic and uniform etch is used to form the gate electrode, the locations of points 1 4 (as determined by gate LWR and fin width) are transferred uniformly from the top of the fin to the bottom of the fin. In reality, the etch bias can vary from the top of the fin to the bottom of the fin, resulting in a tapered profile. The gate sidewall along the fin height may have a rough profile, and it has been shown that this behavior is adequately modeled by using the gate length that has been averaged along the height of the fin [9]. Moreover, the fin itself can have a tapered profile; this has been studied by other researchers [21], [22]. These aforementioned nonidealities of the gate and fin profile are not considered in this paper. B. Simulation Details Table I lists the values of the process and device parameters that were used, generally following the ITRS HP 32-nm node specifications. Fig. 6 shows the simulated 2-D device structure with FG and BG nonidealities. The source and drain doping profiles are Gaussian, peaked at the edges of the gatesidewall spacers (defined by the implant baseline in Fig. 6), and assumed to have a lateral source/drain (S/D) doping gradient σ S/D = 4 nm/dec [23]. This implant profile produces a gate-underlapped S/D structure, which has been found to be optimal for the sub-20-nm physical L g regime [24]. Assuming Fig. 6. Two-dimensional simulated device cross section of a DG FET structure shown with nonidealities (misaligned and with gate length difference between the FG and BG). an inversion carrier density of cm 3, the effective gate length of the nominal device is 23.4 nm. Ideal metallic contacts are made to the surfaces of the uniformly doped S/D regions. All simulations were performed using the Sentaurus device simulator [25], with coupled Poisson, quantum, and high-field saturation models. In hydrodynamic (HD) simulations, the carrier velocity is assumed to depend on the local carrier temperature, and, in the near-ballistic regime, it tends to overestimate the velocity overshoot and drain current. In a study performed by Granzner et al. [26], it was found that, for 20-nm-gate-length DG devices, the ON-current and subthreshold leakage current from the HD simulation were both overestimated by 80% compared to the MC simulation. In order to accurately relate the simulation data to the experimentally determined values of ON-current and subthreshold leakage current, one would be required to carefully calibrate the HD model parameters such as the energy relaxation time (among other parameters). Nayfeh and Antoniadis [27] calibrated the HD parameters using fullband MC simulation. In our simulation, we used the energy relaxation time (τ E ) of 0.14 ps and energy flux parameter (r n ) of 0.3 [23]. C. Model Formulation First, we formulate a simple statistical model to describe the variability in the geometrical parameters in terms of characteristic LWR descriptors. Consider the illustration in Fig. 7 which describes the model parameters. Using point u 2 as the reference, we need to describe the relationship of points u 1, u 3, and u 4 in terms of characteristic LWR descriptors. Misalignment between the FG and BG can occur due to the presence of an offset (between points u 1 and u 3 and/or between points u 2 and u 4 ), with or without a difference in the gate critical dimension of the FG and BG. Therefore, the geometry depicted in Fig. 6 can alternately be described by our choice of three parameters: FG length (L fg ), offset between FG and BG (δ), and gate length difference between FG and BG (ΔL). By definition, the variability in L fg is identically equal to the linewidth variability given by (4). For any linear combination of n correlated Gaussian random variables U = n a i u i (6) i=1

5 PATEL et al.: GATE LINE EDGE ROUGHNESS MODEL FOR ESTIMATION OF FinFET PERFORMANCE VARIABILITY 3059 TABLE II TWO-DIMENSIONAL DEVICE PERFORMANCE PARAMETERS Fig. 7. Definition of the model parameters. The bold lines represent the left and right edges of the gate electrode. Points u 1 u 4 are the locations where the gate electrode intersects the fin. The drain is arbitrarily assumed to be on the right side. the variance of the linear combination can be given by [29] V (U) = n n a 2 i σi a i a j σ i σ j ρ ij. (7) i=1 i=1 j>i Indexes i and j are the points on the LWR profile as described in Fig. 5, σ is their respective standard deviation, and ρ ij is the correlation between points i and j. Let us first define the offset parameter δ as the difference between the right edges of FG and BG, namely, points u 2 and u 4 in Fig. 7 δ (L bg,re L fg,re )=(u 4 u 2 ). (8) Therefore, using (7), we can write σ 2 δ = a 2 2σ a 2 4σ a 2 a 4 σ 2 σ 4 ρ 24. (9) Substituting a 2 = 1, a 4 = 1, σ 2 = σ 4 = σ LER, and ρ 24 = ρ A (t fin ), we can express the variation in the offset parameter as σ 2 δ = 2σ 2 LER [1 ρ A (t fin )]. (10) As mentioned previously, the fin thickness (t fin ) determines the sampling distance in the autocorrelated LWR function along each edge of the gate electrode as defined in (5). The difference in gate length (ΔL) between the FG and BG is given by ΔL (L bg L fg )=[(u 3 u 4 ) (u 1 u 2 )]. (11) The locations of points u 1, u 3, and u 4 relative to point u 2 are random but related variables. Again, we invoke the use of (7), and we substitute a 1 = 1, a 2 = 1, a 3 = 1, a 4 = 1, σ 1 = σ 2 = σ 3 = σ 4 = σ LER, and ρ 12 = ρ 34 = ρ X (0) ρ 14 = ρ 23 = ρ X (t fin ) ρ 13 = ρ 24 = ρ A (t fin ) (12) where ρ X (0) and ρ X (t fin ) are the cross-correlation terms between the left and right edges evaluated at lag 0 and t fin, respectively. ρ A (t fin ) is the autocorrelation term defined in (5) and evaluated at lag t fin. For a resist-defined gate electrode, we have ρ X (0) =0 and ρ X (t fin )=0, and the variation in ΔL is given by σ 2 ΔL = 4σ 2 LER [1 ρ A (t fin )]. (13) It should be noted that, for a given σ LER, the variability in ΔL is twice the variability in δ. Similarly, for a spacer-defined gate electrode, we have ρ X (0) =1 and ρ X (t fin )=ρ A (t fin ). The latter equality holds true because, for a spacer-defined gate electrode, the left and right edges are assumed to be identical. Thus, for a spacer-defined gate electrode, the variation in ΔL is zero σ 2 ΔL = 0. (14) The overall variability in device parameter P depends on many process factors; gate and fin geometries are two important factors. It has been previously shown that fin LWR primarily affects the device performance by changing the average fin width in the channel region [9]. Therefore, to the first order, the variability in device parameter P due to fin LWR can be modeled as ( ) 2 P σp,f 2 = σlwr,f 2. (15) t fin Moreover, the overall variability in device parameter P purely in terms of gate and fin geometries can be written as σ 2 P = σ 2 P,f + σ 2 P,g. (16) The subscripts f and g refer to the fin and gate contributions to the device parameter variance, respectively, noting that, since they correspond to different layers, they can be assumed to be statistically independent. In this paper, we focus primarily on the contribution of the gate to device performance variability. In the following section, we estimate the device parameter sensitivity to the model parameters L fg, δ, and ΔL via 2-D device simulations using a deterministic grid of values for these parameters. The variability in these geometrical model parameters is transformed into the variability in the device parameters via probability density functions generated from the deterministic set. IV. RESULTS AND DISCUSSION Table II shows the nominal transistor performance parameters obtained from the 2-D device simulation, which roughly

6 3060 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009 Fig. 8. Fin width dependence of the saturation threshold voltage. V t,sat is defined to be V gs corresponding to 100-nA/μm I ds for V ds = 0.9 V. Fig. 10. Threshold voltage dependence on the CD difference ΔL and gate offset δ assuming 13-nm FG length. Fig. 11. Threshold voltage dependence on δ andδl. AnFGlengthof13nm is assumed. The positive values of ΔL correspond to larger BG compared to FG, whereas the positive values of δ correspond to BG shifted more toward the drain as compared to FG. Fig. 9. Fin width dependence of the saturation current and subthreshold leakage current. matches the ITRS values for the 32-nm HP node [5]. Hereafter, the device parameters will be referenced to the nominal device, where no offset or gate length difference exists between the FG and BG. The saturation threshold voltage refers to the value of V gs corresponding to 100 na/μm forv ds = 0.9 V. Let us first understand the fin LWR contribution to device parameter variability. The ITRS does not specify any LWR requirements for the fin width [5]. We assume that the fin LWR budget for the 32-nm node (7.5-nm fin width) is the same as the gate LWR budget for the 18-nm node (7-nm physical gate length). Thus, 3σ LWR,f isassumedtobe1nm.fig.8shows the fin width dependence of saturation threshold voltage. It should be noted that at 28 mv/nm, the threshold voltage is quite sensitive to the fin width thickness variation. Thus, using (15), the fin LWR is estimated to contribute 30 mv (3σ) to the total variation in V t,sat. The fin width dependence of saturation current and subthreshold leakage current is shown in Fig. 9. Among the gate resist requirements specified by the ITRS for the 32-nm node, the allocated 3σ budget for low-frequency LWR is 1.7 nm [5]. Although some measured LWR values have been reported [11], the values of the correlation length ξ and roughness exponent α are largely unreported and/or have been kept proprietary. As discussed earlier, the etch process acts as a low-pass filter for LWR, and the lower values of α correspond to the high-frequency component in LWR. Therefore, unless explicitly mentioned, in this paper, we assume that α = 1 which corresponds to an autocorrelation function as defined in (5). Given the complex statistical nature of LWR, the MC approach is an obvious choice. However, since MC TCAD simulations are computationally expensive and require a large number of runs in each case to determine the statistical parameters with reasonable accuracy, we employed a methodology based on experimental design techniques to eliminate the need for full MC simulations. First, we performed 2-D simulations for a predetermined set of values for L fg, ΔL, and δ at 0.5-nm interval within the 6-nm range ( 3 to+3 nm) around their respective means. The computational cost for the exploratory simulation of the three aforementioned parameters is O(n 3 ), where n is the number of steps in each of the three parameter dimensions (L fg, ΔL, and δ). The choice of 0.5-nm step size was based on a tradeoff between the TCAD computational time and the investigative range of each parameter. Fig. 10 shows a 3-D plot of the threshold voltage sensitivity to ΔL and δ for a device with nominal FG. When the BG is smaller than the FG, it can be seen from Fig. 11(a) that the threshold voltage is lowered more for the BG shifted toward the drain versus the BG shifted toward the source. This effect is reversed when the BG is larger than the FG. Another important

7 PATEL et al.: GATE LINE EDGE ROUGHNESS MODEL FOR ESTIMATION OF FinFET PERFORMANCE VARIABILITY 3061 Fig. 12. Comparison of the threshold voltage distributions obtained via direct MC simulation and experimental grid for L fg, ΔL, and δ. For the MC approach, 2000 random values of L fg, ΔL, andδ were generated and directly simulated with Sentaurus. For the grid approach, the predetermined values of L fg, ΔL, andδ at 0.5-nm spacing were simulated, and, then, random values were interpolated to this grid. Fig. 13. Variability in the saturation threshold voltage V t,sat for a resistdefined gate electrode (a) as a function of LWR amplitude and (b) as a function of correlation length. Note that the variability in V t,sat is a much stronger function of the LWR amplitude than it is of the correlation length. The fin width in both plots is 7.5 nm. observation from Fig. 11(a) is that, for a given CD mismatch between the FG and BG, the FinFET threshold voltage is relatively invariant over some range of the gate offset, whereas, as it can be seen in Fig. 11(b), even for no gate offset, the threshold voltage is fairly sensitive to CD mismatch. Thus, the CD mismatch between the FG and BG is more critical than the gate offset. By performing device simulation for this grid, we mapped out the variability space for the model parameters L fg, ΔL, and δ. The computational efficiency of our approach is enabled by the structure of our model which parameterizes the FinFET structure in terms of L fg, ΔL, and δ and relates them to the LWR descriptors ξ, σ, and α. Thus, any realization of gate LWR is translated into the corresponding values of L fg, ΔL, and δ, and the device performance can then be estimated through straightforward interpolation using the presimulated grid. Thus, expensive TCAD simulations need to be performed only once at each of the grid values, and, for any given set of LWR parameters (ξ, σ, and α), an MC experiment can be performed outside of the TCAD environment (in any tool such as MATLAB [30]). A lithography process engineer may need to evaluate several scenarios of LWR descriptors before settling for a given process. An accurate assessment of each scenario would warrant a minimum of 200 MC runs. Thus, the initial investment of TCAD simulation is quickly paid off if many such scenarios need to be evaluated. Using our MATLAB script (which accurately preserves all correlations), we generated 2000 MC samples of L fg, ΔL, and δ. This MC set was directly simulated with Sentaurus; each run took approximately 200 s on 2-GHz quad CPU running 64-b Linux. The same MC set was also approximated by interpolation using the presimulated grid values. Interpolation in MATLAB was completed in less than 5 s. The resulting probability density functions are compared in Fig. 12, and we conclude that our grid approach produces reasonably accurate results, combined with very good computational efficiency. For all subsequent analysis, the probability density function for each device parameter was approximated by interpolat- Fig. 14. Variability in the (filled symbols, left y-axis) saturation drive current and (open symbols, right y-axis) OFF-state leakage current for a resist-defined gate electrode as a function of LWR amplitude. The fin width is 7.5 nm. ing values of L fg, ΔL, and δ using the presimulated basis set. Fig. 13 shows the impact of the LWR parameters σ LWR and ξ on the variability in the saturation threshold voltage V t,sat for a resist-defined gate electrode. An increase in σ LWR or a decrease in ξ each results in greater variation in δ and, hence, the effective channel length; thus, the variation in the threshold voltage increases due to SCE. From Fig. 13(a), it should be noted that, for the ITRS stipulated value of 1.7 nm for 3σ LWR, we observe a 21- to 30-mV variation (3σ) in V t,sat as compared to the 16-mV (1σ) variation reported due to WFV [2]. Additionally, we observe that the V t,sat sensitivity to σ LWR ranges from 14 to 17 mv/nm. This is roughly half compared to the 28-mV/nm V t,sat sensitivity to t fin variation observed in Fig. 8. Thus, the fin width variation is the more significant component than gate LWR. The variability trends for I d,sat and log 10 (I off ) are consistent with the trends observed for V t,sat, as shown in Figs. 14 and 15. Fig. 16 shows that the variability in V t,sat is further lowered when the gate electrode is spacer-defined. In the spacer-defined case, σ 2 LWR = 2σ2 LER is assumed. Consistent reductions in the variability were also seen for I d,sat and log 10 (I off ) (not shown). It should be noted these trends observed for DG FinFETs in contrast with those reported for planar bulk MOSFETs [28].

8 3062 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009 ACKNOWLEDGMENT The authors would like to thank Dr. L. Smith (Synopsys) for the help with Sentaurus, the useful discussions, and bringing [27] to our attention; the anonymous reviewers for bringing [2] and [4] to our attention; and L. Sponton and Prof. M. Gastpar (UC Berkeley) for the helpful discussions. Kedar Patel would like to thank L. Rowland and Dr. K. Quader at SanDisk for providing the opportunity to conduct this work. Fig. 15. Variability in the (filled symbols, left y-axis) saturation drive current and (open symbols, right y-axis) OFF-state leakage current for a resist-defined gate electrode as a function of correlation length. The fin width is 7.5 nm. Fig. 16. Comparison of variability in the saturation threshold voltage V t,sat for a resist-defined versus a spacer-defined gate electrode (a) as a function of LWR amplitude for ξ = 10 nm and (b) as a function of correlation length for σ = 0.5 nm. The fin width in both plots is 7.5 nm. Constantoudis and Gogolides [28] observed that a larger correlation length increased the threshold voltage variability and, thus, lowered the yield, defined by 10% tolerance. However, for FinFETs with either resist- or spacer-defined gate electrodes, an increase in the correlation length reduces the variation in V t,sat. V. C ONCLUSION The impact of gate LWR on FinFET performance variability is studied in this paper. Using a simple analytical model that relates LWR parameters to DG structure parameters, we were able to gain physical insight into LWR and assess its impact on DG FET performance. For any given LWR profile, we have shown that the framework presented in this paper can be used to assess the device performance variability quickly without having the need to perform extensive MC TCAD simulations each time a new LWR profile needs to be investigated. Furthermore, if a compact model for the DG FET were to be developed and parameterized in terms of gate geometrical parameters L fg, ΔL, and δ described in this paper, then, with the aid of the variability equations presented in this paper, the variability of any device parameter of interest can directly be derived. REFERENCES [1] A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs, IEEE Trans. Electron Devices, vol. 50, no. 9, pp , Sep [2] S. O uchi, T. Matsukawa, T. Nakagawa, K. Endo, Y. X. Liu, T. Sekigawa, J. Tsukada, Y. Ishikawa, H. Yamauchi, K. Ishii, E. Suzuki, H. Koike, K. Sakamoto, and M. Masahara, Characterization of metal-gate FinFET variability based on measurements and compact model analyses, in IEDM Tech. Dig., San Francisco, CA, 2008, pp [3] N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. 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Available: Kedar Patel (M 99 SM 08) received the B.S. degree (magna cum laude) in engineering physics and the M.S. degree in electrical engineering from the University of California, Berkeley, in 1997 and 1998, respectively, where he is currently working toward the Ph.D. degree. In the past ten years, he has primarily worked on technology development and process integration. At Cypress Semiconductor, he worked on developing three generations of SRAM technologies and transferring them to production in Bloomington, MN. While at PDF Solutions, he consulted U.S. and European clients on logic and embedded DRAM and Flash-memory-related yield issues. At Matrix Semiconductor (now SanDisk Corporation), Milpitas, CA, he worked on technology development of three generations of a revolutionary 3-D (multilayered) onetime-programmable memory using industry standard semiconductor materials and processes, where he is currently managing the product engineering team that is responsible for SSD and 3-D products. His current research interests are in understanding the impact of intrinsic process variations on devices, as well as novel approaches to quantify their impact on circuit performance. He is the holder of two patents in process technology. Tsu-Jae King Liu (F 07) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984, 1986, and 1994, respectively. In 1992, she joined the Xerox Palo Alto Research Center as a Member of the research staff to research and develop polycrystalline silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. In August 1996, she joined the faculty of the University of California, Berkeley, where she is currently a Professor of electrical engineering and computer sciences and the Associate Dean for Research with the College of Engineering. Her research activities are currently in nanometer-scale logic and memory devices and technology. She has authored or coauthored over 300 publications and is the holder of over 60 U.S. patents. Dr. Liu has served on several committees for many technical conferences, including the International Electron Devices Meeting and the Symposium on VLSI Technology, and was a member of the IEEE EDS VLSI Technology and Circuits Technical Committee. From 1999 to 2004, she served as an Editor for the IEEE ELECTRON DEVICE LETTERS. She was the recipient of the DARPA Significant Technical Achievement Award (2000) for the development of the FinFET, the Electrical Engineering Award for Outstanding Teaching at UC Berkeley (2003), and the NAE Lillian M. Gilbreth Lectureship (2006). Costas J. Spanos (M 77 SM 96 F 00) received the B.E.E. degree (with honors) from the National Technical University of Athens, Athens, Greece, in 1980 and the M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, in 1981 and 1985, respectively. From 1985 to 1988, he was with the Advanced Computer-Aided Design Group, Digital Equipment Corporation, Hudson, MA, where he worked on the statistical characterization, simulation, and diagnosis of VLSI processes. In 1988, he joined the faculty of the Department of Electrical Engineering and Computer Sciences (EECS Department), University of California, Berkeley, where he is currently a Professor. From 1994 to 2000, he was the Director with the Berkeley Microfabrication Laboratory, and, from 2004 to 2005, he was the Director with the Electronics Research Laboratory, and, from 2004 to 2008, he was the Associate Dean for Research with the College of Engineering. He is currently the Associate Chair of the EECS Department and the Chair of the EE Division. He has published more than 200 referred articles, has received several best paper awards, and has coauthored a textbook in semiconductor manufacturing. From 1998 to 2003, he led a multicampus multi-pi research project on small feature reproducibility. His current research interests include the development of flexible manufacturing systems, the application of statistical analysis in the design and fabrication of integrated circuits, and the development and deployment of novel sensors and computer-aided techniques in semiconductor manufacturing. Prof. Spanos has served in the technical committees of the IEEE Symposium on VLSI Technology, the International Semiconductor Manufacturing Sciences Symposium, the Advanced Semiconductor Manufacturing Symposium, and the International Workshop on Statistical Metrology, and he was the Editor of the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING from 1991 to 1994.