SURFACE-POTENTIAL-based MOSFET models provide

Transcription

1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 55, NO 3, MARCH Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region Pradeep Agarwal, Govind Saraswat, and M Jagadesh Kumar, Senior Member, IEEE Abstract In this paper, by solving the 1-D Poisson equation using appropriate boundary conditions, we report a closed-form surface potential solution for all the three surfaces gate oxide silicon film interface, silicon-film buried oxide interface, and buried oxide substrate interface) of fully depleted silicon-on-insulator SOI) MOSFETs by considering the effect of substrate charge explicitly During the model derivation, it is assumed that the silicon film is always fully depleted and the back silicon film surface is never inverted The calculated values of the surface potentials obtained from the proposed model agree well with the iterative solution of exact Poisson equation with a maximum relative error bound of 03% In the entire model, only two square roots, one exponential, and two logarithm terms are used and the continuity and differentiability of the resultant surface potential solutions are ensured making the proposed model computationally efficient Index Terms Compact modeling, fully depleted silicon-oninsulator SOI) MOSFET, numerical solution, surface potential, threshold voltage Fig 1 Cross-sectional view of the FD SOI MOSFET I INTRODUCTION SURFACE-POTENTIAL-based MOSFET models provide consistent and accurate expressions for terminal currents and charges valid in all regions of operations 1] 8] These models have emerged as a better alternative to the thresholdvoltage-based models as they are suitable for simulating circuits with low power supply voltages and also allow physical modeling of the subthreshold region, which were the main drawbacks of the threshold-voltage-based models 9] 15] Many models based on surface potential approach have been developed for bulk MOSFETs and implemented in different circuit simulators 2] 5] The same modeling approach has been extended to partially depleted silicon-on-insulator SOI) PDSOI) MOSFET with a special consideration to effects, specific to PDSOI MOSFET, such as floating body and self-heating effects 16], 17] However, modeling of fully depleted SOI FDSOI) MOSFET is quite different due to appearance of depletion charge in the substrate region The previously reported FDOI models 18] 20] do not consider the substrate depletion, and hence, cannot be used for FDSOI devices having low substrate doping The recently published FDSOI model Hiroshima University Semiconductor Technology Academic Research Center IGFET model SOI HiSIM-SOI) 21] considers the substrate depletion explicitly and is based on the surface potential approach However, the model does not derive closed- Manuscript received October 5, 2007 The review of this paper was arranged by Editor C Jungemann The authors are with the Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi , India pradeep1agarwal@gmailcom) Digital Object Identifier /TED form single-equation solution of surface potentials by solving the Poisson equation Instead, it uses iterations to compute surface potentials at different surfaces of the FDSOI device that makes the model computationally inefficient Hence, it becomes important to have a closed-form single-equation solution of surface potential for different surfaces of the FDSOI device so that it can be used in circuit simulators To the best of our knowledge, there is no such solution available in the literature that solves surface potentials at all surfaces of the FDSOI MOSFET explicitly considering the effect of substrate depletion Therefore, the purpose of this paper is to obtain a closed-form analytical approximation for potentials at the three surfaces of the FDSOI MOSFET, namely front oxide silicon film surface φ sf, buried oxide silicon film interface φ sb, and buried oxide substrate interface φ sbulk For this purpose, three different equations are obtained by solving the 1-D Poisson equation in vertical direction and applying the boundary conditions at different surfaces These three equations are solved for various regions of operation and unified with the help of smoothing functions No discontinuity in the derivative of the surface potentials are found even though three types of smoothing functions are used II IDEAL SURFACE POTENTIAL The 1-D Poisson equation of an FD-SOI MOSFET, shown in Fig 1, can be written as 11] 2 φy) 2 = 1 py) ny) N ch ) 1) where φy) is the potential, is the dielectric constant of silicon, py) and ny) are the hole and electron concentrations, respectively and N ch is the doping in the silicon layer /$ IEEE

2 790 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 55, NO 3, MARCH 2008 Equation 1) can be further expressed as { ) ] 2 φy) 2 = qn ch exp φy) 1 ) exp 2φ ) ]} F + V CB φy) exp 1 where φ F is the Fermi potential, is the thermal voltage, and V CB is the channel floating body potential, which varies from V sb at source to V sb +V ds at drain Although V CB has been referred to by different names and symbols in literature as channel potential V cb ) in 17], the channel floating body potential V cb ) in 20], and bulk-referenced quasi-fermi potential V) in 22], but we will call it here as the channel floating voltage Multiplying both sides of 2) by 2 φy ) and then integrating from buried oxide silicon film interface φ sb to front oxide silicon film surface φ sf, we get φy) φy )=φ sf = 2qN ch φy) { exp φy )=φ sb ) φ sf exp φ sb ) φ sf φ sb ) exp 2φ F +V CB ) φ sf exp exp )] φ sb )] 2) )} φ sf φ sb ) The following boundary conditions need to be used in 3): 1) Electric flux displacement) at the front oxide/si film interface is continuous φy) φy )=φ sf = V g φ sf t ox 3) 4) where is the dielectric constant of the gate oxide, t ox is the front gate oxide thickness, and V g = V GS V FB, where V GS is the gate-to-source bias voltage and V FB is the flat-band voltage 2) Electric flux at the interface of the buried oxide/si film is continuous φy) φy )=φ sb = φ sb φ sbulk t box 5) where is the dielectric constant of the gate oxide, t box is the buried oxide thickness, φ sb is the surface potential at the buried oxide silicon layer, and φ sbulk is the surface potential at the buried oxide substrate interface Substituting the two aforementioned boundary conditions in 3) gives us V g φ sf ) 2 C2 box Cox 2 φ sbulk φ sb ) 2 { ) )] = γ 2 exp φ sf exp φ sb φ sf φ sb ) ) )] exp 2φ F +V CB φ sf φ sb ) exp exp )} φ sf φ sb ) 6) 2qNch ε where γ si = C ox and C ox = t ox Equation 6) has three unknowns namely φ sf, φ sb, and φ sbulk ) Therefore, two more equations are needed to solve it and they can be obtained by solving the Poisson equation in the silicon film layer and the substrate region as explained in the Appendix φ sf φ sb = α +φ sb φ sbulk ) C box 7) φ sb = φ sbulk + γ bulk φsbulk 8) 2qNsub ε si where γ bulk = C box, α = qn cht 2 soi 2, and C box = t box Equations 6) 8) together describe the exact Poisson equation for an FDSOI MOSFET and are obtained without any approximation except the assumptions that the back silicon surface and the substrate region never go into inversion and that the device always remains in FD condition These equations can be solved iteratively to get the exact values of all three surface potential expressions A single closed-form solution for the surface potential cannot be obtained for the FD-SOI MOSFET as in the case of bulk MOSFETs due to the nonlinear nature of 6) 8) Hence, separate solutions are first obtained in the weak and strong inversion regions, and then, they are combined to get a single closed-form expression, as discussed in the following sections III SURFACE POTENTIAL SOLUTION To obtain the surface potential solution, it is further assumed that the MOSFET does not operate in the accumulation region, which is a quite a valid assumption as the accumulation region is rarely used except in some specific applications Hence, when > 3, 6) becomes φ sf 1 γ 2 ) V g φ sf ) 2 C2 box φ sbulk φ sb ) 2 C 2 ox =φ sf φ sb )+ ) 2φF V CB + exp 1 exp φ sf φ sb )) ) 9)

3 AGARWAL et al: COMPACT SURFACE POTENTIAL MODEL FOR FD SOI MOSFET 791 Finally, the value of E b is used to obtain the expressions of all the three surface potentials in weak inversion as φ sf,weak = V g t ox E b + qn ) cht soi 13) φ sbulk,weak = 1 Eb 2 14) 2 qn sub Fig 2 Electric field profile from the Si/SiO 2 interface of the front gate oxide toward the substrate The solid lines indicate the electric field distribution for a given gate voltage The dashed lines show the electric field when the silicon film is just depleted Finally, 7) 9) are solved for the weak and strong inversion cases so that they can be unified with the help of smoothing functions as in the case of the bulk MOSFET A Weak Inversion The MOSFET operates in weak inversion when φ F <φ sf < φ 2F In this region, we can neglect the small inversion charge appearing at the front silicon film surface as in the case of the bulk MOSFET Fig 2 shows the electric field variation in the vertical direction when the MOSFET is operating in weak inversion, where the solid line represents the electric field at a certain gate voltage V GS We define V C as the minimum voltage necessary to keep the device in the FD mode In Fig 2, the dotted line shows the electric field variation in the vertical direction at V C At this voltage, the electric field at the buried oxide silicon layer surface becomes zero Therefore, V C can be written as V C = α + qn Cht soi C ox 10) Voltage V g = V GS V FB ) is equal to the total area under the electric field curve, shown in Fig 2, and can be written as V g V C = 1 Eb 2 +t ox + t box ) E b + E b t soi 11) 2 qn sub where E b is the electric field at the buried oxide/substrate surface when the device has just reached FD and N sub is the substrate doping From 11), E b can be written in terms of V g as E b = qn sub C eff + qnsub C eff where 1 C eff = 1 C ox + 1 C box + 1 ) 2 + 2qN sub V g V C ) 12) φ sb,weak = φ sbulk,weak + t boxe b 15) where φ sf,weak, φ sb,weak, and φ sbulk,weak denote the front surface potential, back surface potential, and bulk surface potential in the weak inversion region, respectively B Strong Inversion In the strong inversion region, 9) can be rearranged as 16) shown at the bottom of the page where φ sf,strong, φ sb,strong, and φ sbulk,strong denote the front surface potential, back surface potential, and bulk surface potential in the strong inversion region, respectively The value of φ sb,strong is given by 8) and φ sbulk,strong can be obtained from 7) and 8) as φ sbulk,strong = ) 2 β + β 2 α +φ sf,strong ) 17) where β =05γ bulk 1+ C box ) In 16), an additional 1 is added inside the logarithmic term to match the value of φ sf,strong obtained from this equation to the weak inversion surface potential φ sf,weak obtained from 13) at the intersection of the two regions This ensures the continuity of the final surface potential solution for all the regions of operation Equation 16) is a nonlinear equation in φ sf,strong and a direct solution of it cannot be obtained Two approximations are suggested for 16) in the case of bulk and PDSOI MOSFET cases 17], 22] The first approximation for the surface potential φ 1 sf,strong ) used in 17] is given as φ 1 sf,strong =2φ F + V CB 18) However, in 22], it is shown that the use of φ 1 sf,strong results in a large error at the strong inversion region It has also been shown in 22] that a replacement of φ sf,strong by a value several times higher than 2φ F + V CB results in a good modeling at strong inversion but inaccurate modeling at the moderate inversion region, which is crucial for low-voltage designs Hence, this approximation was also rejected φ sf,strong =2φ F + V CB + ln 1 γ 2 ) V g φ sf,strong ) 2 C 2 box C φ ox 2 sbulk,strong φ sb,strong ) 2 φ sf,strong φ sb,strong ) +1 1 e φ sf, strong φ sb, strong φ ) t ) 16)

4 792 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 55, NO 3, MARCH 2008 Fig 3 Comparison of front surface potential φ sf obtained iteratively φ sf,iterative from 7) 9)] and analytically φ sf,analytic from 16), 18), and 19)] Parameters used are: V FB = 05 V, V sub =0V, N ch =10 17 cm 3, N sub =10 15 cm 3, t ox =3nm, t box = 100 nm, and t soi =50nm The second approximation φ 2 sf,strong for the surface potential φ sf,strong is suggested as 22] φ 2 sf,strong =2φ F + V CB + φ sf,weak 2φ F V CB ) 2 φ 1+ sf, weak 2φ F V CB η 19) The model for φ 2 sf,strong is a continuous function changing smoothly from 2φ F + V CB at the onset of the strong inversion region to 2φ F + V CB η at the high values of gate voltages Here, η is a constant and its numerical value is between 4 and 6 to get a better approximation for φ s in the case of bulk MOSFETs 17], 22] Therefore, in the present study, η is taken as 6 for the range of doping and oxide thicknesses used This approximation results in a more accurate final solution Fig 3 shows a comparison between the exact solution of the front surface potential obtained by solving 7) 9) iteratively and the analytical strong inversion surface potential solution obtained from 16), 18), and 19) Approximations 1 and 2 represent the solution of 16) with φ sf,sttrong in the right side of the equation given by 18) and 19), respectively Direct use of approximation 19) in 16) results in discontinuities at two points, which can cause serious problems in circuit simulators, and therefore, a sharp increase in simulation time Hence, these discontinuities are removed by replacing 2φ F + V CB in 19) by a function f, which is continuous for all values of gate voltage changes from φ sf,weak at weak inversion to 2φ F + V CB at strong inversion 20], 22] f = φ sf,weak+2φ F +V CB φ sf,weak 2φ F V CB ) 2 +4δ ) where δ 2 is a fitting parameter and its value is taken as 01 20], 22] The removal of the discontinuities is demonstrated in Fig 4 The figure shows the plots of weak inversion front surface potential solution φ sf,weak, strong inversion front surface potential solution φ sf,sttrong, obtained from 16) and 18) 20), and the iterative solution of the surface potential, obtained from Fig 4 Weak inversion front surface potential φ sf,weak ), strong inversion front surface potential φ sf,strong ), and front surface potential obtained iteratively φ sf,iterative ) from 7) 9)] versus gate voltage Parameters used are: V FB = 05 V, V sub =0V, N ch =10 17 cm 3, N sub =10 15 cm 3, t ox =3nm, t box = 100 nm, and t soi =50nm 6) 8)) Good match is achieved in both the weak and strong inversion regions Also, no discontinuity is observed in the strong inversion solution C Single-Piece Model After obtaining separate solutions for the surface potentials in weak and strong inversion regions, we need to unify these two solutions with the help of a good smoothing function The smoothing function 1) should be continuous and differentiable and 2) should ensure that each of the approximations for the weak and strong inversions is reduced smoothly to insignificance outside of its respective region of validity Since the nature of the front surface potentials in the weak and strong inversion conditions in our case is similar to that of a PDSOI MOSFET, we have used a well-known smoothing function to satisfy the two aforementioned requirements, which have been successfully used in the case of the PDSOI MOSFET 17] The smoothing function is given as φ sf = φ sf,strong ln 1+e φ sf, strong φ sf, weak ) 21) Equation 21) relies on the fact that in strong inversion, φ sf,strong φ sf,weak, and in the weak inversion φ sf,strong << φ sf,weak The continuity and infinite differentiability of all the smoothing functions ensure the continuity and infinite differentiability of the final φ sf After obtaining φ sf, φ sb and φ sbulk are obtained by using φ sf from 21) in 7) and 8) IV MODEL VERIFICATION Since 6) 8) are obtained without making any approximations except the assumptions that no inversion takes place at the back surface and the silicon layer is fully depleted), we have compared our model results to the iterative solution of the Poisson equations 6) 8) The model calculations were performed using the MATLAB7 We used a large range of parameters to

5 AGARWAL et al: COMPACT SURFACE POTENTIAL MODEL FOR FD SOI MOSFET 793 TABLE I DEVICE PARAMETERS USEDINTHERESULT VERIFICATION OF THE FDSOI MOSFET Fig 6 Substrate surface potential φ sbulk versus gate voltage for different values of substrate doping Parameters used are: V FB = 05 V, V sub =0V, N ch =10 17 cm 3, t ox =3nm, t box = 100 nm, and t soi =50nm Fig 5 Three surface potentials φ sf, φ sb, and φ sbulk versus gate voltage Parameters used are: V FB = 05 V, V sub =0V, N ch =10 17 cm 3, N sub =10 15 cm 3, t ox =3nm, t box = 100 nm, and t soi =50nm verify our model The parameters used in our simulation are given in Table I The parameter ranges are chosen such that the device operates in the FD mode and no inversion of back surface or substrate takes place Although the model is verified for all sets of parameters given in the table, only important results are summarized here due to space limitations Fig 5 shows the variation of surface potentials φ sf, φ sb, and φ sbulk versus the gate voltage for a front oxide thickness of 3 nm, buried oxide thickness of 100 nm, and silicon film thickness of 50 nm The silicon film doping is kept sufficiently high cm 3 ) to ensure the absence of channel at the back silicon layer surface The substrate doping is selected quite low cm 3 ) to clearly demonstrate the effect of substrate depletion charge on the front surface potential When the substrate doping is low, a large potential drop appears across the substrate depletion region, which changes the channel inversion charge density significantly Fig 5 clearly shows a large drop across the substrate region given by φ sbulk The surface potentials from the analytical solution are in close proximity with the simulation results To further highlight the effect of substrate depletion, we have plotted φ sbulk for different values of substrate doping in Fig 6 At low values of substrate doping eg, cm 3 ), a large drop appears across the substrate depletion region However, the voltage drop decreases as the substrate doping is increased Fig 7 shows variation of the front surface potential φ sf with gate voltage for different values of the channel floating voltage V CB We notice that the surface potential varies linearly in the Fig 7 Front surface potential φ sf versus gate voltage for different values of V CB Parameters used are: V FB = 05 V, V sub =0V, N ch =10 17 cm 3, N sub =10 15 cm 3, t ox =3nm, t box = 100 nm, and t soi =50nm weak inversion region and then saturates at high values of gate voltages similar to that observed in the case of bulk MOSFETs The simulation results are in close proximity with the results obtained from the iterative solution of the Poisson equation for all values of the parameters given in Table I The maximum relative error in the surface potentials is below 03% for the range of parameters used The relative error is calculated as Relative Error Analytical Solution Iterative Solution = 100% Iterative Solution 22) Equation 22) is used to evaluate the relative error for various parameters and the maximum of these errors is taken as the maximum relative error V CONCLUSION For the first time, we have reported a closed-form surface potential solution for all the three surfaces of the FDSOI MOSFET The effect of substrate charge is considered explicitly The 1-D Poisson equation is solved in the vertical direction

6 794 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 55, NO 3, MARCH 2008 using appropriate boundary conditions The model results are compared with the iterative solution of the exact Poisson equation as the Poisson equation is known to describe the device behavior accurately The calculated values of the surface potentials obtained from the proposed model agree well with the iterative solution Maximum relative error is within a bound of 03% During the model derivation, it is assumed that the MOSFET is operating in the FD mode and the back silicon film surface or substrate is never inverted, which are quite valid assumptions for modern day s FDSOI devices In the entire model, for the front silicon film surface, only two square roots, one exponential, and two logarithms terms are used; hence, the model is computationally efficient Furthermore, the continuity and differentiability of all the smoothing functions used ensure the continuity and differentiability of the resultant surface potential solutions Our model can be used in the surface-potential-based models for deriving the charge and current expressions The nonideal effects and the specific detour field present in the FDSOI MOSFET can be incorporated in the same way as done in the HiSIM Model APPENDIX DERIVATION OF 7) AND 8) Assuming inversion at the back silicon film surface and the substrate to be absent, the Poisson equations for the substrate and silicon film are given by A1) and A2), respectively 2 φy) 2 = 1 qn sub ) A1) 2 φy) 2 = 1 qn ch ) A2) For simplicity, we have ignored the small voltage drop appearing across the front surface inversion charge layer while writing A2) Multiplying both sides of A1) and A2) by 2 φy ), and then, integrating A1) from the buried oxide substrate interface φy) =φ sbulk ] to deep neutral substrate region φy) =0] and A2) from a point y distance below the front oxide silicon film interface φy)] to the buried oxide silicon film interface φy) =φ sb ], we arrive at the following equations, respectively: φy) 2 φy )=φy)] φy) φy )=φ sb = 2qN ch φy) φ sb ) A3) φy) φy )=φ sbulk = 2qN sub φ sbulk ) A4) By noting the identity φy ) = φy ) φy )=φ = sbulk φy )=φxb E b, where E b is the electric field at the buried oxide substrate interface, as shown in Fig 2, and using this identity in A3) and A4), we get φy) φy )=φy ) E b 2 = 2qN ch φy) φ sb ) A5) E b 2 = 2qN sub φ sbulk ) A6) Applying the Poisson equation in the charge-free buried oxide region, we obtain the value of E b as E b = φ sb φ sbulk ) A7) t box ε si By substituting the value of E b from A7) in A5) and A6), and then, integrating A5) from the front oxide silicon film interface φy) =φ sf ] to the buried oxide silicon film interface φy) =φ sb ], the following equations are obtained: φ sf φ sb = α +φ sb φ sbulk ) C box A8) φ sb = φ sbulk + γ bulk φsbulk A9) 2qNsub ε where γ bulk = si C box, α = qn cht 2 soi 2, = t soi, and C box = t box Equations A8) and A9) are 7) and 8) of the main text, respectively REFERENCES 1] T-L Chen and G Gildenblat, Analytical approximation for the MOSFET surface potential, Solid State Electron, vol 45, pp , ] G Gildenblat, X Li, W Wu, H Wang, A Jha, R V Langevelde, G D J Smit, A J Scholten, and D B M Klassen, PSP: An advanced surface-potential-based MOSFET model for circuit simulation, IEEE Trans Electron Devices, vol 53, no 9, pp , Sep ] A R Boothroyd, S W Tarasewicz, and C Slaby, MISNAN A physically based continuous MOSFET model for CAD applications, IEEE Trans Comput-Aided Des Integr Circuits Syst, vol 10, no 12, pp , Dec ] MOS-11, NXP Semiconductors, Berlin, Germany Online] Available: 5] J He, Y Song, X Niu, G Zhang, M Chan, B Li, R Huang, and Y Wang, PUNSIM: An advanced surface potential based MOSFET model, in Proc MIXDES, Gdynia, Poland, Jun 2006, pp ] C B Jie, S Z Biao, Y Zhong, S Ting, and J Zheng, Modeling of front and back gate surface potential of deep-submicro FD-SOI MOSFET, in Proc 6th Int Conf Solid State Integr Circuits Technol, 2001, vol 2, pp ] G Gildenblat, X Cai, T-L Chen, X Gu, and H Wang, Reemergence of the surface-potential-based compact MOSFET models, in IEDM Tech Dig, Dec 2003, pp ] G Gildenblat, H Wang, T L Chen, X Gu, and X Cai, SP: An advanced surface-potential-based compact MOSFET model, IEEE J Solid State Circuits, vol 39, no 9, pp , Sep ] K Joardar, K K Gullapalli, C McAndrew, M E Burnham, and A Wild, An improved MOSFET model for circuit simulation, IEEE Trans Electron Devices, vol 45, no 1, pp , Jan ] H Wang, T-L Chen, and G Gildenblat, Quasi-static and nonquasistatic compact MOSFET models based on symmetric linearization of the bulk and inversion charges, IEEE Trans Electron Devices, vol 50, no 11, pp , Nov ] J R Brews, A charge-sheet model of the MOSFET, Solid State Electron, vol 21, p 345, ] J He, M Chan, X Zhang, and Y Wang, A physics-based analytic solution to the MOSFET surface potential from accumulation to strong-inversion region, IEEE Trans Electron Devices, vol 53, no 9, pp , Sep 2006

7 AGARWAL et al: COMPACT SURFACE POTENTIAL MODEL FOR FD SOI MOSFET ] J Benson, N V D Halleweyn, W Redman-White, C A Easson, M J Uren, O Faynot, and J-L Pelloie, A physically based relation between extracted threshold voltage and surface potential flat band voltage for MOSFET compact modeling, IEEE Trans Electron Devices, vol 48, no 5, pp , May ] M Miura Mattausch, U Feldmann, A Rahm, and M Bollu, Unified complete MOSFET model for analysis of digital and analog circuits, IEEE Trans Comput-Aided Des Integr Circuits Syst, vol 15, no 1, pp 1 7, Jan ] M Miura Mattausch, H Ueno, H J Mattausch, K Morikawa, S Itoh, A Kobayashi, and H Masuda, 100 nm-mosfet model for circuit simulation: Challenges and solutions, IEICE Trans Electron, vol E86-C, no 6, pp , Jun ] G Gildenblat, W Wu, X Li, H Wang, G Workman, S Veeraraghavan, and C McAndrew, SP-SOI: A third generation surface potential based compact MOSFET model, in Proc IEEE Custom Integr Circuits Conf, Sep 2005, pp ] M S L Lee, B N Tenbroek, W Redman-White, J Benson, and M J Uren, A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation, IEEE J Solid State Circuits, vol 36, no 1, pp , Jan ] K K Young, Short-channel effect in fully depleted SOI MOSFETs, IEEE Trans Electron Devices, vol 36, no 2, pp , Feb ] G F Niu, R M M Chen, and C Ruan, Comparisons and extension of recent surface potential models for fully depleted short-channel SOI MOSFETs, IEEE Trans Electron Devices, vol 43, no 11, pp , Nov ] Y S Yu, S H Kim, S W Hwang, and D Ahm, All-analytic surface potential model for SOI MOSFETs, Proc Inst Elect Eng Circuits Devices Syst, vol 152, no 2, pp , Apr ] N Sadachika, D Kitamaru, Y Uetsuji, D Navarro, M M Yusoff, T Ezaki, H J Mattausch, and M M Mattausch, Completely surface-potentialbased compact model of the fully depleted SOI MOSFET including shortchannel effects, IEEE Trans Electron Devices, vol53,no9,pp , Sep ] R van Langevelde and F M Klaassen, Explicit surface-potential-based MOSFET model for circuit simulation, Solid State Electron, vol 44, pp , 2000 Pradeep Agarwal received the BTech degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India His current research interests include device modeling and simulation for nanoscale applications Govind Saraswat received the BTech degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India His current research interests include device modeling and simulation for nanoscale applications M Jagadesh Kumar M 95 SM 99) was born in Mamidala, Andhra Pradesh, India He received the MS and PhD degrees in electrical engineering from the Indian Institute of Technology Madras, Chennai, India From 1991 to 1994, he was a Postdoctoral Researcher in the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada, where he was engaged in research on high-speed bipolar transistors and amorphous silicon thin-film transistors From July 1994 to December 1995, he was initially with the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India, and then joined the Department of Electrical Engineering, Indian Institute of Technology IIT) Delhi, New Delhi, India, where he became an Associate Professor in July 1997 and a Full Professor in January 2005 He is the author or coauthor of more than 120 papers published in refereed journals and conferences and is the author of two book chapters His teaching has often been rated as outstanding by the Faculty Appraisal Committee, IIT Delhi His current research interests include nanoelectronic devices, modeling and simulation for nanoscale applications, integrated-circuit technology, and power semiconductor devices Prof Kumar is a Fellow of the Indian National Academy of Engineering and the Institution of Electronics and Telecommunication Engineers, India He was the recipient of several awards including the 29th IETE Ram Lal Wadhwa Gold Medal and the ISA-VSI TechnoMentor Award of the India Semiconductor Association He is an Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES and an Associate Editor of the Journal of Computational Electronics He is also on the Editorial Board of Recent Patents on Nanotechnology, Recent Patents on Electrical Engineering, Journal of Low Power Electronics, Journal of Nanoscience and Nanotechnology, andtheiete Journal of Research as a subject area Honorary Editor for Electronic Devices and Components He has reviewed extensively for different journals including IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELI- ABILITY, Electronics Letters, and Solid-state Electronics