10.1" LCD PANEL P28 LVDS. CPU PineView-M VGA. D-Sub P26. 22mm x 22mm P6~P11. DMI x 2 AUDIO CODEC. Tiger Point HDA REALTEK ALC269Q

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1 M F lock iagram R.0 TI harger QRHR P. Inputs Outputs LOK EN. LRKLFT P RII OIMM P~P RII PU PineView-M LV 0." L PNEL P TOUT _IN T+ ystem / TPRER P. Inputs Outputs mm x mm P~P V -ub P TOUT +VLW +VLW +VLW_LO +EV MI x ystem / TPRER P. Inputs Outputs RJ P U# U# U# U#0 ON ON ON P0 U# MM-IM P0 Transformer 0/00Mb P P U# MER P P U# T P LN + in arder Reader JM P P U# WiFi P PIE x U.0 PIE Interface Tiger Point U.0 ( ports) T ( Ports) ZLI H UIO XPIE IF PI LP I/F mm x mm P~P H T UIO OE RELTEK LQ P T H P HP JK MI JK Int. MI peaker +_VU TOUT VFX PU / MXTJ+ P. INPUT OUTPUT TOUT VHORE ystem / PU P.0 Inputs Outputs +_VU +0_VRUN ystem / FU P.0 Inputs Outputs in ard lot P LP,MHZ +_VU +_VRUN E NUVOTON NPEL0X P M us Thermal ensor EM- P ystem / FU P.0 Inputs Outputs +_VU +_0VRUN PI M us attery Pack P IO P0 TOUH P P0 K P0 P lock iagram MF 0. ize ocument Number Rev Wednesday, March, 00 ate: heet of

2 PU0/PUT0 LK_PU_LK# LK_PU_LK LKN LKP Pineview PU/PUT LK_MH_LK# HPL_LKINN R K0 M_LK_R#0 K0/K0# MHz LN LK_PIE_LN# LK_PIE_LN R/RT R/RT LK_MH_LK EXP_LKIN# EXP_LKIN HPL_LKINP EXP_LKINN EXP_LKINP R K#0 R K R K# M_LK_R0 M_LK_R# M_LK_R O-IMM K/K# R/RT REFLK# PL_REFLKINN Wireless LK_PIE_WLN# LK_PIE_WLN R/RT R0/RT0 REFLK REFLK# PL_REFLKINP PL_REFLKINN REFLK PL_REFLKINP LK_PIE_# LK_PIE_ R0/RT0 PU/PUT LK_IH_MI# LK_IH_MI MI_LKINN MI_LKINP.KHz R/RT LK_IH_T# T_LKINN LK_IH_T T_LKINP U_MHz LK_IH LK PI_F LK_IH_PI PILK REF0 LK_IH LK TPT H_IT_LK H_OE_ITLK LK H udio K-0.MHz PI LK_KPI LPLK E.KHz P lock distribution MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

3 Pine Trail Power Flowchart for MF Voltage Rails O MEN ON X MEN OFF tate power plane +VLW_LO +EV +VLW +VLW +VU +_VU +VRUN +VRUN +_VRUN +_VRUN +_0VRUN +0_VRUN VFX VHORE 0 O O O O O O O X /, O O X X attery only O X X X / & attery don't exist () X X X X : TR : T : OFT OFF : ME OFF P Power Flowchart MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

4 Pine Trail Power On equence REV : 00/0/ / tate tate 0 tate _IN/T+ TOUT +VLW_LO/+EV +VLW/+VLW to LW_PWR PM_RMRT# PWRW# PWRTN# PM_LP_# U_ON +VU/+VU/+_VU PM_LP_# RUN_ON +VRUN/+VRUN +0_VRUN/+_VRUN +_V_PWR +_0VRUN +_0V_PWR to 0 +_VRUN/VFX LL_Y_PWR IMVP_VR_ON VHORE K_PWR ELY_VR_PWR H_PWR PLT_RT# P Power On equence() MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

5 Pine Trail Power On equence REV : 00/0/ to - attery Only - Mode T - TOUT TOUT a LW_ON 0 +VLW_LO +EV +VLW +VLW b ERT# +EV U_ON RUN_ON LW_PWR Reset I RNV0 E NPEL Power On utton 0 PM_LP_# PM_LP_# PWRTN# PM_RMRT# PLT_RT# Tigerpoint to 0 PUPWR H_PWR U_ON RUN_ON +_V_PWR +VU +_VU +VRUN +VRUN +0_VRUN +_VRUN +_0VRUN R_PWR FX_PWR LL_Y_PWR +_V_PWR IMVP_VR_ON ELY_VR_PWR Y_PWR_TPT PWROK VRMPWR PLT_RT# PUPWROO RTIN# PU Pineview PWROK +_0V_PWR VFX +_VRUN IMVP VHORE IMVP_LK_EN# K_PWR LK en. K0 P Power On equence() MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

6 U MI_RXP0 MI_RXN0 MI_RXP MI_RXN 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR MI_RXP0_ MI_RXN0_ MI_RXP_ MI_RXN_ F F H MI_RXP_0 MI_RXN_0 MI_RXP_ MI_RXN_ MI_TXP_0 MI_TXN_0 MI_TXP_ MI_TXN_ H J MI_TXP0 MI_TXN0 MI_TXP MI_TXN MI EXP_LKIN# EXP_LKIN N EXP_LKINN N EXP_LKINP R0 R RV_ RV_ N0 RV_ N RV_ K RV_ J RV_ M RV_ L RV_ QLJ EXP_ROMPO EXP_IOMPI EXP_RI RV_TP_ RV_TP_ RV_0 RV_ RV_ RV_ L0 L L N P K L M N EXP_OMP EXP_RI MIL TP MIL TP R 0_F 00 R._F 00 Pull-down must be placed within 00 mils of the processor. P PU- Pineview () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

7 Place resistors close to MH PIN ON MH_VREF, Place 0.uF P close to MH. RIMM_VREF R N_ 00 +_VU R K_F 00 R K_F 00 0.U_0V_K 00_XR U, M [..0] M Q[..0] +_VU R 0.0U_.V_K 00_XR, M WE#, M #, M R#, M 0, M, M,,,,,, M_#0 M_# M_KE0 M_KE M_OT0 M_OT M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# N_ 00 R 0._F 00 R 0._F 00 +_VU R 0K_J 00 M 0 M M M M M M M M M M 0 M M M M PU_V_ TP MIL TP MIL MH_VREF MH_R_RP MH_R_RPU Place P close to pin R_RPU H J R M_0 R M_ K R M_ K R M_ J R M_ H K R M_ R M_ J R M_ H R M_ K R M_ K0 H R M_0 R M_ J R M_ J R M_ J0 R M_ K R WE# J R # K R R# J0 R 0 H0 R K R H R #_0 K R #_ J R #_ J R #_ H0 R KE_0 H R KE_ K0 R KE_ J R KE_ K R OT_0 H R OT_ H R OT_ K R OT_ R K_0 F R K#_0 R K_ R K#_ R K_ R K#_ F R K_ R K#_ RV_ RV_ RV_ RV_ RV_ K RV_ RV_TP_ RV_TP_ L R_VREF K J R_RP R_RPU K RV_ QLJ R_ R Q_0 R Q#_0 R M_0 R Q_0 R Q_ F R Q_ R Q_ R Q_ R Q_ E R Q_ E R Q_ R Q_ R Q#_ R M_ R Q_ R Q_ E R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ 0 R Q#_ E R M_ M Q0 M Q#0 M M0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q# M M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q# M M M Q R Q_ M Q R Q_ F0 M Q R Q_ M Q R Q_ F M Q0 R Q_0 F M Q R Q_ M Q R Q_ E0 M Q R Q_ K R Q_ K R Q#_ J R M_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q#_ R M_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q#_ R M_ R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ M Q M Q# M M H J M Q M Q K M Q J F H M Q M Q M Q L M Q0 J M Q M Q M Q# M M E M Q M Q F M Q M Q M Q F M Q E M Q M Q E M Q M Q# J M M E M Q0 M Q M Q M Q M Q M Q M Q E M Q E0 M Q R Q_ F M Q# R Q#_ F0 M M R M_ M Q R Q_ 0 M Q R Q_ 0 M Q0 R Q_0 M Q R Q_ J0 M Q R Q_ J M Q R Q_ E M Q R Q_ M Q R Q_ M Q R Q_ M Q# R Q#_ M M R M_ R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ W R Q_ M Q M Q W M Q W M Q M Q0 M Q M Q M Q M Q[..0] M Q#[..0] M M[..0] P PU- Pineview () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

8 R R R N_K_J 00 K_J N_K_J XP_RV_ XP_RV_ XP_RV_ TP MIL TP MIL TP MIL XP_RV_0 XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ U XP_RV_0 XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_ XP_RV_0 XP_RV_ 0 XP_RV_ 0 XP_RV_ 0 XP_RV_ XP_RV_ XP_RV_ XP_RV_ L RV_ V RT_HYN RT_VYN RT_RE RT_REEN RT_LUE RT_IRTN RT T RT LK _IREF REFLKINP REFLKINN REFLKINP REFLKINN M0 RT_HYN M RT_VYN N P0 P N0 L L0 P REFET Y0 Y 0 Locate eries resistor within 0 mils of MH R0 _J 00 R _J 00 RE_V REEN_V LUE_V R _F 00 V T V LK REFLK REFLK# REFLK REFLK# HYN_V VYN_V Place IREF RE close to MH: <00mils to MH ball Place V R resistors close to MH: <0 mils to MH balls. RE_V REEN_V LUE_V R 0_F 00 R0 0_F 00 R 0_F 00 R 00 N_K_J XP_RV_ PM_EXTT#_/PRLPVR PM_EXTT#_0 PWROK RTIN# K PM_PRLPVR_R J0 PM_EXTT#0 L IMVP_PWR_R R R POWER_LOE_P_00 POWER_LOE_P_00 PM_PRLPVR, PM_EXTT#0 ELY_VR_PWR, PLT_RT#,,0,,0,, TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL R R W T V RV_TP_ RV_TP_ RV_TP_ RV_TP_ RV_TP_ RV_TP_0 RV_TP_ RV_TP_ MI HPL_LKINN HPL_LKINP W W LK_MH_LK# LK_MH_LK +VRUN PM_EXTT#0 R 0K_J 00 QLJ P PU- Pineview () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

9 U H_PLP# MIL TP +VRUN R0.K_J 00 R.K_J 00 L_LK_EI L_T_EI R R LV_LKIN- LV_LKIN+ LV_RXIN0- LV_RXIN0+ LV_RXIN- LV_RXIN+ LV_RXIN- LV_RXIN+ U U R R N N R R R.K_F 00 LI R TP MIL J POWER_LOE_P_00 LVREFH N POWER_LOE_P_00 LVREFL N L_LEN L L_LTL L LTL_LK TP MIL L LTL_T TP MIL K L_LK_EI K L_T_EI K L_LVEN H L_LKN L_LKP L_TN_0 L_TP_0 L_TN_ L_TP_ L_TN_ L_TP_ LI LV LVREFH LVREFL LKLT_EN LKLT_TL LTL_LK LTL_T L_LK L_T LV_EN LV IH MI# 0M# FERR# LINT0 LINT INNE# TPLK# PRTP# PLP# INIT# PRY# PREQ# THERMTRIP# PROHOT# PUPWROO E H H F0 F E F 0 E F E W H_MI# H_TPLK# H_PLP# H_PM_PRY# H_PM_PREQ# PROHOT# MIL TP0 H_MI# H_0M# H_FERR# H_INTR H_NMI H_INNE# H_TPLK# PM_PRTP#, H_PLP# H_INIT# PM_THERMTRIP# H_PWR H_MI# MIL TP H_TPLK# MIL TP Place within 00 mils of TLREF' pin.zo=0ohm. +_0VRUN R K_F 00 +_0VRUN R R N J 00 R _J 00 N_R_J 00 R _J 00 R0 _J 00 R _J 00 R _J 00 R _J 00 H_PM_PRY# H_PM_PREQ# PU_RV_0 H_TI H_TO H_TM H_TK H_TRT_N TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL H_THERM H_THERM H_PM#0 H_PM# H_PM# H_PM# H_PM_#0 H_PM_# H_PM_# H_PM_# PU_RV_0 H_TI H_TO H_TK H_TM H_TRT_N E F E0 0 PM 0# PM # PM # PM # PM 0#/RV PM #/RV PM #/RV PM #/RV RV_ TI TO TK TM TRT# THRM_ THRM_ THRM_/RV THRM_/RV PU TLREF V_ RV_ RV_0 LKN LKP EL_0 EL_ EL_ VI_0 VI_ VI_ VI_ VI_ VI_ VI_ RV_ RV_ RV_ RV_ RV_TP_ RV_TP_ EXTREF H L E H0 J0 K H K H0 H H 0 F E L 0 H K K PU_TLREF EL0 EL EL VI0 VI VI VI VI VI VI MIL TP MIL TP0 EXTREF U_0V_K 00_XR LK_PU_LK# LK_PU_LK EL0 EL EL +_0VRUN R _F 00 R.K_F 00 VI[..0] EL0 EL EL R K_F 00 R 00 R 00 +_0VRUN R0 00K_J 00 L_LEN L_LVEN QLJ Place within 00 mils of Processor pin. +_0VRUN 0P_0V_J 00_NPO U_0V_K 00_XR R 00 R 00K_J 00 R PROHOT# _J 00 R OVT_E#,, POWER_LOE_P_00 P PU- Pineview () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

10 +_VU plitting V_R and V_K_R power shapes are proven effective to reduce the R clock jitter. +_VU V_R and V_K_R rails R are split near Pineview-M to avoid noise coupling. power_close_gap_00 +_VRUN U_.V_K 00_XR 0U_.V_M 00_XR R POWER_LOE_P_00 +VFR PL +_0VRUN R power_close_gap_00. uf x uf x U_.V_K 00_XR 0.U_0V_K 00_XR U_.V_K 00_XR P_0V_J 00_NPO +_0VRUN uf x U_.V_K 00_XR 0 P_0V_J 00_NPO. uf x power_close_gap_00 R POWER_LOE_P_00 N_.U_.V_M 00_XR R 0 U_.V_K 00_XR 0 + N_0U_.V_M.x.x. 0 +_VRUN P_0V_J L 00_NPO +V_RIN uf x U_.V_K 00_XR U_.V_K 00_XR 0 U_.V_K 00_XR.U_.V_M 00_XR Place P and resistor close to MH alls for VK_R 0 uf x. uf x uf x P_0V_J 00_NPO R POWER_LOE_P_00 N_E LF Place beside 0 uf x uf x +V_V V_HMPLL +V_RIN +V_LI_VI +VRT +_0VRUN +VRUN U_0V_K 00_XR uf x +_0VRUN Place aps close to PU Pin,,. 00R-00MHZ_00 EM000 U_.V_K 00_XR.U_.V_M 00_XR 0.U_.V_M 00_XR U_.V_M 00_XR 0 U_.V_M 00_XR U_.V_M 00_XR U_.V_K 00_XR.U_.V_M 00_XR uf x U_.V_K 00_XR U_.V_K 00_XR.U_.V_M 00_XR.U_.V_K 00_XR U_.V_K 00_XR m U_.V_K 00_XR N_0.U_.V_K 00_XR R POWER_LOE_P_00 VFX +V_R +VK_R m N_U_.V_M 00_XR UE T VFX_ T VFX_ T VFX_ T T VFX_ VFX_ V VFX_ V VFX_ W VFX_ W W VFX_ VFX_0 W VFX_ K VM_ K VM_ K VM_ L VM_ L L VM_ VM_ L VM_ QLJ. K VK_R_ L VK_R_ U0 V_R_ U V_R_ U V_R_ U U V_R_ V_R_ U V_R_ V V_R_ V V_R_ V W0 V_R_ V_R_0 W V_R_ 0 VK_R_ VK_R_ V T0 V PL V_HMPLL VFR PL VRT. FX/MH R. 0m T J V_IO VRIN_ET VRIN_WET_ VRIN_WET_ VRIN_WET_ V_LI PINEVIEW_M EXP\RT\PLL POWER MI PU 0m LV 0m V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ VENE VENE V V_ VP_ VP_ 0m VLV VLV V_MI_ V_MI_ V_MI_ RV_ VFR_MIHMPLL VP_ E E E F F F H H H H J J J J K K K L L L L N N N N Y V0 W T T T P E VHORE 00m +TPEV_VP +V0_LV_R +V_RIN U_0V_K 00_XR + N_0U_.V_M.x.x. uf x uf x 0m +VFR_MIHMPLL U_.V_K 00_XR U_0V_K 00_XR U_.V_M 00_XR VHORE +VP U_.V_M 00_XR R0 00_F 00 R 00_F 00 uf x U_0V_K 00_XR +_0VRUN Place beside R VENE VENE R POWER_LOE_P_00 0.U_0V_K 00_XR R POWER_LOE_P_00 L POWER_LOE_P_00 0.UH_00 LQMNNR0K00 +_VRUN R N_U_.V_M 00_XR U_0V_K 00_XR +_0VRUN +_0VRUN +V0_LV +V_MI +V VHORE PU & P avoid to route with stub Layout Note: Route VENE & VENE traces at. Ohms with mil spacing to other signals. Place PU and P within inch of PU. 0.0 uf x P_0V_J 00_NPO N_U_0V_K 00_XR N_E LF U_.V_K 00_XR N_U_.V_M 00_XR Place near PIN Y uf x U_.V_M 00_XR P_0V_J 00_NPO 0.0U_.V_K 00_XR Place beside R N_E LF +_VRUN +_VRUN POWER_LOE_P_00 +_0VRUN P PU- Pineview () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet 0 of R POWER_LOE_P_00 R0 POWER_LOE_P_00 U_.V_M 00_XR

11 ize ocument Number Rev ate: heet of P MF 0. PU- Pineview () Wednesday, March, 00 ize ocument Number Rev ate: heet of P MF 0. PU- Pineview () Wednesday, March, 00 ize ocument Number Rev ate: heet of P MF 0. PU- Pineview () Wednesday, March, 00 N UF QLJ N UF QLJ V_ F V_ F V_ E V_ E V_ E V_ E V_ E0 RV_NTF_ E V_ RV_NTF_ V_0 V_ V_ V_ RV_NTF_ V_ V_ RV_NTF_ RV_NTF_ 0 V_ V_ V_ V_ V_0 L RV_NTF_ L0 RV_NTF_ L RV_NTF_ L V_ L RV_NTF_ L V_ L V_ L RV_NTF_0 K RV_NTF_ K0 V_ K RV_NTF_ K RV_NTF_ K V J V_ J RV_NTF_ J V_ H V_ H V_ H V_ H V_0 H V_ H V_ V_ 0 V_ F V_ F V_ F V_ F V_ F V_ E V_0 E V_ E V_ E V_ E V_ E V_ E V_ V_ V_ 0 V_ V_0 V_ V_ V_ V_ 0 V_ 0 V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ RV_NTF_ RV_NTF_ 0 RV_NTF_ RV_NTF_ V_0 V_ V_ V_ T V_ Y V_ Y V_ Y V_ W V_ W V_ W V_0 W V_ W0 V_ W V_ W V_ W V_ W V_ W V_ W V_ V V_ V V_0 V V_ V V_ V V_ U V_ U V_ U V_ U V_ T V_ R V_ R V_00 R V_0 P V_0 P V_0 P V_0 P V_0 P V_0 P V_0 P V_0 P V_0 N V_0 N V_ N V_ N V_ N V_ N V_ N V_ N V_ N V_ M V_ M V_0 L V_ L V_ L V_ L V_ L V_ L V_ L V_ K V_ K V_ K0 V_0 K V_ K V_ K V_ K V_ K V_ K V_ J V_ J V_ J V_ J V_0 H V_ H V_ H V_ H V_ H V_ H V_ V_ V_ V_ V_0 V_ F V_ F V_ F

12 M Q M Q M Q M Q M Q# M Q R_EXTT#0 M Q M M Q# M Q M Q M M M Q M Q M Q M Q M Q0 M M Q M Q# M Q M Q# M Q M M M Q M Q IMM0_0 M Q M Q M Q0 M Q M Q M Q M M0 M Q M Q M Q M Q M Q M Q M Q M M 0 M Q M Q M IMM0_ M M Q M M Q M Q M Q0 M Q M Q0 M M Q# M Q#0 M Q M Q M Q M M R_VREF M Q M Q M Q M Q M Q0 M Q M M Q M Q M M M Q M Q M Q M Q# M Q0 M Q R_VREF M M M M 0 M Q M Q M Q M Q M Q M Q M Q M M M M M M M Q M Q M Q M Q0 M Q M M M Q0 M Q M Q M Q M Q M Q# M_KE0, M, M_KE, M WE#, M_LK, M R#, M_#0, M_OT, M_T, PM_EXTT#0 M_LK_R M_LK_R# M #, M_#, M Q[:0] M [..0], M Q[..0] M Q#[..0] M M[..0] M, M_LK_R0 M_LK_R#0 M 0, M_OT0, +_VU +_VU +VRUN +_VU +_VU RIMM_VREF +_VU +VRUN ize ocument Number Rev ate: heet of P MF 0. RII(O-IMM0) ustom Wednesday, March, 00 ize ocument Number Rev ate: heet of P MF 0. RII(O-IMM0) ustom Wednesday, March, 00 ize ocument Number Rev ate: heet of P MF 0. RII(O-IMM0) ustom Wednesday, March, 00.V IMM=.0 (0 mil) Place close to VREF pin. Place these aps near o-imm0 Place these aps near o-imm0 Mus ddress: 0H(W)/H(R) R K_F 00 R K_F 00 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR.U_.V_M 00_XR.U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR R0 0K_J 00 R0 0K_J 00 P_0V_J 00_NPO P_0V_J 00_NPO.U_.V_M 00_XR.U_.V_M 00_XR.U_.V_M 00_XR.U_.V_M 00_XR 0.U_.V_M 00_XR 0.U_.V_M 00_XR R N_ 00 R N_ 00 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR P_0V_J 00_NPO P_0V_J 00_NPO R 0K_J 00 R 0K_J 00 R RM O-IMM (00P) N R O-IMM_x00P FOX_0-N-H R RM O-IMM (00P) N R O-IMM_x00P FOX_0-N-H VREF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V KE0 V N _ V V 0 V0 0 0/P WE# 0 V # # V OT V Q Q V Q# Q V Q Q V Q0 Q V Q Q V M0 0 V Q Q V Q 0 Q V M V K0 0 K0# V Q Q V 0 V0 Q0 Q V N 0 M V Q Q V 0 Q Q V Q# Q 0 V0 Q0 Q V KE 0 V V 0 V V 0 0 R# 0 0# 0 V OT0 V N 0 V Q Q V M 0 V Q Q V Q 0 Q V V M V Q Q V0 Q Q V NTET V0 Q# Q V Q0 Q Q Q V M V Q Q V L V(P) Q# Q V 0 Q Q V Q Q 0 V K K# V M 0 V Q Q V Q0 0 Q V Q# Q V 0 Q Q V 0 00 V MFIX 0 MFIX 0 R N_ 00 R N_ 00 R K_F 00 R K_F 00 R N_0K_J 00 R N_0K_J U_.V_K 00_XR 0 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR.U_.V_M 00_XR.U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR.U_.V_M 00_XR.U_.V_M 00_XR P_0V_J 00_NPO P_0V_J 00_NPO

13 +0_VRUN 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR P_0V_J 00_NPO Place one cap close to every two pull-up resistors terminated to +0_VRUN. +0_VRUN M 0 R _J 00, M [..0] M M R _J 00 R _J 00 +0_VRUN +0_VRUN,, M_#0 M_# R _J 00 R _J 00,, M 0 M R _J 00 R _J 00 M M M M R _J 00 R _J 00 R0 _J 00 R _J 00,,,, M_KE0 M_KE M_OT0 M_OT R _J 00 R _J 00 R _J 00 R _J 00, M, M #, M R#, M WE# R _J 00 R _J 00 R _J 00 R _J 00 M M M M 0 R0 _J 00 R _J 00 R _J 00 R _J 00 M M M M R _J 00 R _J 00 R _J 00 R _J 00 P RII (Termination) MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

14 WLN_RXN WLN_RXP WLN_TXN WLN_TXP LN_RXN LN_RXP LN_TXN LN_TXP WWN_RXN WWN_RXP WWN_TXN WWN_TXP 0.U_0V_K 00_XR 0 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR N_0.U_0V_K 00_XR N_0.U_0V_K 00_XR +_VRUN MI_TXN0 R UP0N H U_PN0 MI_TXP0 R MI0RXN MI0RXP UP0P H U_PP0 MI_RXN0 P MI0TXN UPN H U_PN MI_RXP0 P0 MI0TXP UPP H U_PP MI_TXN T MIRXN UPN J U_PN MI_TXP T0 UPP J U_PP MI_RXN T MIRXP MITXN UPN K U_PN 0 MI_RXP T MITXP UPP K U_PP 0 T MIRXN UPN K U_PN T MIRXP UPP K U_PP U UPN L U_PN U MITXN MITXP UPP L U_PP V MIRXN UPN M U_PN V0 MIRXP UPP M U_PP V MITXN UPN N U_PN 0 V MITXP UPP N U_PP 0 LN_TXN_ LN_TXP_ LN_TXN_ LN_TXP_ WWN_TXN_ WWN_TXP_ Place the resistor within 00 mils of TPT. U K PERn K J PERp PETn J PETp M PERn M PERp K K PETn PETp L PERn L PERp L PETn M P PETp PERn P PERp N PETn N PETp PI-E MI U O0# O# O# O# E O# E O[]#/PIO O[]#/PIO0 O[]#/PIO URI URI# LK U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# URI F R._F 00 U_O#0 U_O# U_O# LK_IH Port0 Port Port Port Port Port Port Port U port table External U External U WWN (/P) luetooth amera module MM-IM Traces tied together close to Pin Length no longer than 00 mil to Resistor. External U WLN(WIFI) PI_PIPQ# PI_PIPQ# PI_PIPQF# PI_PIPQ# RP +VRUN U_O# U_O# U_O#0 U_O# U_O# U_O# U_O# U_O# RP.K 00_PR RP.K 00_PR PI_ERR# PI_TOP# PI_EVEL# PI_FRME# +VLW +VLW RP +VRUN R._F 00 LK_IH_MI# LK_IH_MI MIOMP H MI_ZOMP J MI_IROMP W MI_LKN W MI_LKP QV.K 00_PR RP +VRUN.K 00_PR RP +VRUN TRP#/PIO and TRP#/PIO have weak internal pull-ups +VRUN traping Options Flash TRP#/ PIO 0 N_K_J 00 R0 FLH_EL0 N_K_J 00 R0 FLH_EL 00.K_J R0 00 0K_J R0 R0 N_K_J 00 TRP#/ PIO 0 TPT_M_RV_PU TPT_K_RV_PU RV_TPT_ Routing PI PI LP +VRUN N_0K_J R0 00 N_0K_J R0 00 LK_IH_PI 0 PI_RT# RUNTIME_I# TRP0#:Top-lock wap Override. If the signal is sampled low, this indicates that the system is strapped to the "top-block swap" mode (Tiger Point inverts for all cycles targeting FWH IO space) PI_EVEL# PI_IRY# PI_ERR# PI_TOP# PI_PLOK# PI_TRY# PI_PERR# PI_FRME# P_REQ# P_REQ# FLH_EL0 FLH_EL TPT_PIO_PU RUNTIME_I# PI_PIPQ# PI_PIPQ# PI_PIPQ# PI_PIPQ# PI_PIPQE# PI_PIPQF# PI_PIPQ# PI_PIPQH# RV_TPT_ TPT_K_RV_PU TPT_M_RV_PU U PR EVEL# J PILK PIRT# IRY# PME# ERR# F TOP# PLOK# 0 0 TRY# PERR# FRME# NT# E NT# REQ# 0 REQ# QV PI PIO/TRP# TRP#/PIO PIO PIO PIRQ# PIRQ# PIRQ# H0 PIRQ# E PIRQE#/PIO PIRQF#/PIO H PIRQ#/PIO F PIRQH#/PIO TRP0# K RV_ M RV_ /E0# /E# /E# /E# E H L J E0 E L H H M L PI_PIPQ# PI_IRY# PI_PIPQH# PI_PIPQE# TPT trap Pin trap Pin TRP0# TRP# TRP#.K 00_PR P_REQ# P_REQ# TPT_PIO_PU RUNTIME_I# Internal PU/P PU 0K PU 0K PU 0K PI_PLOK# PI_PIPQ# PI_PERR# PI_TRY# R00.K_J 00 R0.K_J 00 R0.K_J 00 R0.K_J 00 +VRUN.K 00_PR External PU/P PU 0K(N) to +VRUN/P K(N) PU 0K(N) to +VRUN/P K(N) PU 0K(N) to +VRUN/P K(N) P Tiger Point () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

15 U +VRUN R 0K_J 00 TRP_ET_UP R E0 Y 0 Y0 W0 V E E U Y E E V 0 RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_0 RV_ PIO T HOT T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI TLE# 0TE 0M# PULP# INNE# INIT_V# INIT# INTR FERR# NMI RIN# ERIRQ MI# TPLK# THRMTRIP# E E U Y0 Y Y Y T V 0 H_0TE H_RIN# INT_ERIRQ TRI H_LE# H_THERMTRIP_R T_RXN0 T_RXP0 T_TXN0 T_TXP0 LK_IH_T# LK_IH_T H_LE# H_0TE H_0M# H_INNE# H_INIT# H_INTR H_FERR# H_NMI H_RIN# INT_ERIRQ,0 H_MI# H_TPLK# PLE TRI REITOR LOE TO IH: <00 MIL TO IH LL TRI H_LE# H_0TE R._F 00 R 0K_J 00 R.K_J 00 +VRUN H_RIN# R 0K_J 00 QV INT_ERIRQ R.K_J 00 +_0VRUN H_THERMTRIP_R +_0VRUN R _J 00 PLE LOE TO TPT 0 < 000MIL pull-up at PE R0 POWER_LOE_P_00 PM_THERMTRIP# H_FERR# R _J 00 Place close to TPT P Tiger Point () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

16 U +VRUN +VLW H_OE_ITLK, H_OE_RT# M_LK_IH M_T_IH 0 LP_RQ0#,0 LP_FRME# H_OE_TOUT H_OE_YN LK_IH R 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 R0 0K_J 00 R K_J 00 R.K_J 00 U V,0 LP_[..0] WP M_LERT#_R MLLERT_IH MLINK0_IH MLINK_IH EXT_MI# WKE_I#_R IH_RI# _RT# L 0 V EEPROM_OP-_x HTL0 PIE_WKE# IH_TLOW# R _J 00 R _J 00 N_P_0V_J 00_NPO +VLW LP_0 LP_ LP_ LP_ H_OE_TIN0 R _J 00 R _J 00 lose to R for EMI 0 0.U_.V_K 00_XR H_ITLK H_OE_RT#_ TP MIL TP MIL H_OE_TOUT_ H_OE_YN_ R LN_RT# POWER_LOE_P_00 RT_X RT_X RT_RT# M_LERT#_R M_LK_IH M_T_IH MLLERT_IH MLINK0_IH MLINK_IH TP MIL TP MIL TP MIL TP0 MIL TP MIL LRQ#/PIO V L0/FWH0 L/FWH Y L/FWH W L/FWH Y LRQ0# Y FWH/LFRME# P H_IT_LK U H_RT# W H_IN0 V P H_IN H_IN H_OUT Y H_YN LK U EE_ E EE_IN T EE_OUT V EE_HLK T LN_LK P LN_RTYN LN_RT# LN_RX0 LN_RX LN_RX W LN_TX0 T LN_TX U LN_TX W RTX V RTX T RTRT# E0 MLERT#/PIO H MLK E MT H LINKLERT# F MLINK0 F MLINK R PI_MIO T PI_MOI M PI_# P R PI_LK PI_R QV RT M PI LP UIO LN EPROM MI MUY#/PIO0 PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PRLPVR TP_PI# TP_PU# PIO PIO PIO PIO PIO LKRUN# PIO PIO PIO PIO PUPWR/PIO THRM# VRMPWR MH_YN# PWRTN# RI# U_TT#/LPP# ULK Y_REET# PLTRT# WKE# INTRUER# PWROK RMRT# INTVRMEN PKR LP_# LP_# LP_# TLOW# PRTP# PLP# TP T W W K H M P E 0 Y R 0 F U V E H T U0 J H0 E F F0 T_P_ETET# TPT_PIO TPT_PIO EXT_MI# T0_PWR_EN# WKE_I#_R PNEL_I0 ONFI_MOE_N PM_PRLPVR TPEV_IH_P PNEL_I PM_LKRUN# ORI0 ORI ORI PLTRT#_R PIE_WKE# M_INTRUER# IMVP_PWR RMRT#_IH IH_INTVRMEN LP_#_R LP_#_R LP_#_R IH_TLOW# PM_PRTP#_R I_LP_PI# 0 MIL TP MIL TP R N_ 00 EXTMI# MIL TP R WKE_I# POWER_LOE_P_00 MIL TP R0 N_ 00 PM_PRLPVR, PM_TPPI# PM_TPPU# IH_THRM# R0 N_ 00 VR_PWR_LKEN R IH_YN# POWER_LOE_P_00 IH_RI# PM_U_TT# ULK MIL TP R 0K_J 00 MIL TP R R M_FLH_EN 0 PM_LKRUN#,0 H_PWR OVT_E#,, K_PWR PWRTN# PM_U_TT# 0 _RT# 0 PIE_WKE#, POWER_LOE_P_00 POWER_LOE_P_00 PLTRT#_R Y_PWR_TPT PM_RMRT# H_PKR PM_LP_# PM_LP_# PM_LP_# PM_PRTP#, H_PLP#, LL_Y_PWR, ELY_VR_PWR PIO (Internal pull-high) MI / oupling election: If the signal is sampled high, the MI interface is strapped to operate in coupled mode (No coupling capacitors are required on MI differential pairs). If the signal is sampled low, the MI interface is strapped to operate in coupled mode (oupling capacitors are required on MI differential pairs). +VRUN +VRUN PLT_RT#,,0,,0,, Y_PWR_TPT Mus ddress: E/FH +VLW +VRUN +VRUN +VLW +VRUN M_LK_IH M_T_IH R.K_J R 00.K_J.K_J 00 Q 00 N00W Q N00W M_LK, M_T, +VLW Panel I PNEL_I0 PNEL_I TPT_PIO TPT_PIO T0_PWR_EN# ONFI_MOE_N M_INTRUER# VRT I_LP_PI# PM_LKRUN# IH_THRM# IH_YN# VR_PWR_LKEN RMRT#_IH RT_X MIL TP0 MIL TP MIL TP R R R R MIL TP POWER_LOE_P_00 POWER_LOE_P_00 POWER_LOE_P_00 POWER_LOE_P_00 R POWER_LOE_P_00 U0 N_0P_0V_J 00_NPO N_NLV0KR U NZ0P 0 N_0.U_0V_K 00_XR R N_ 00 R.K_J 00 R0 R.K_J 00 R N_0K_J 00 R N_0K_J 00 R0 0K_J 00 R 0K_J K_J R 00 0K_J R 00 0K_J R0 00 0K_J R R M_J 00 R N_0K_J 00 R.K_J 00 R 0K_J 00 R K_J 00 R 00K_J 00 R0 0K_J 00 P_0V_J RT_RT# R 0K_J VRT +EV IH_INTVRMEN R K_F 00 Y_PWR_TPT M_FLH_EN TPEV_IH_P R 0K_J 00 R 0K_J 00 R K_J 00 RT_X R 0M_J 00 00_NPO Y.KHZ_.P_0PPM M0 00_NPO P_0V_J J OPEN_JUMP_OPEN 00 U_.V_M 00_XR U_.V_M 00_XR RT H00H-0PT R 0_F 00 R0 RT 0_F 00 MFIX MFIX FOX_H0E-LH HEER ONN_P N P Tiger Point () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

17 +VRUN +VRUN +VLW +VLW H00H-0PT R 0 00 H00H-0PT R 00 UE VREF VREF_us VccTPLL VccRT VccMIPLL VUPLL V_PU_IO F F Y E Y F W m +VREF +VREF_U +V_T_PLL m +VMI_PLL_IH +_VRUN_TPT m 0 U_.V_M 00_XR 0 U_.V_M 00_XR U_0V_K 00_XR 0 0U_.V_M 00_XR 00 0.U_0V_K 00_XR 0m m +_VRUN m R 0 0.U_0V_K 00_XR 0 0.U_0V_K 00_XR VRT 0 0.0U_.V_K 00_XR power_close_gap_00 P_0V_J 00_NPO Place near IH PIN E 0 0.U_0V_K 00_XR 0 P_0V_J 00_NPO Place next to pin Y +_VRUN m R 0 0.U_0V_K 00_XR 0 POWER_LOE_P_00 0U_.V_M 00_XR POWER Vcc Vcc Vcc Vcc Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc Vcc Vcc Vcc Vcc Vcc M M0 N J0 K P V0 H F0 0 R0 T +V_P_ Place near VT, VUORE,VP +_0VRUN_TPT 0U_.V_M 00_XR Place near V U_0V_K 00_XR U_0V_K 00_XR U_.V_M 00_XR U_0V_K 00_XR U_.V_M 00_XR Place near pin VUPLL F P_0V_J 00_NPO 0.U_0V_K 00_XR m R +_0VRUN Place near pin V,H power_close_gap_00 0.U_0V_K 00_XR 0 N_U_0V_K 00_XR N_U_0V_K 00_XR m P_0V_J 00_NPO +VRUN R POWER_LOE_P_00 QV Vccus Vccus Vccus Vccus F N K F Place near VPPI,VPLP +V_P_ 0.U_0V_K 00_XR U_.V_M 00_XR U_.V_M 00_XR Place near pin K,N Place near pin F-VU N_0U_.V_M 00_XR Place near pin VT +VLW m R POWER_LOE_P_00 P_0V_J 00_NPO +VMI_PLL_IH Place near to F P_0V_J 00_NPO 0.0U_.V_K 00_XR.U_.V_K 00_XR +_VRUN m R POWER_LOE_P_00 Place near pin VPLL,Y UF Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_0 Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_0 Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_0 Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_0 Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_0 Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ Vss_ RV_ QV 0 0 E F H H H K K K K K0 L M M N N N N N P P P R R T T V V V V V V W W Y Y 0 0 E E0 E E F E P Tiger Point () MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

18 +_0VRUN +VRUN R POWER_LOE_P_00 +V_M +VRUN 0 0U_0V_M 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR P_0V_J 00_NPO 0.U_.V_K 00_XR U_V_K 00_XR 0.U_V_K 00_XR P_0V_J 00_NPO P_0V_J 00_NPO 0U_0V_M 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR 0 0.U_V_K 00_XR 0.U_V_K 00_XR 0.U_V_K 00_XR +VRUN 0 P_0V_J 00_NPO P_0V_J 00_NPO 0 LK_IH EL EL LK_IH EL0 LK_IH_PI LK_KPI PLK_FWH K0_X Y.MHZ_0P_0PPM K0_X R0 R R R +VRUN R 0K_J 00 R K_J R R _J _J.K_J _J _J _J +V_M K0_X K0_X PU_EL_R PU_EL_R PLKLK PLKLK PLKLK TP TP +_0VRUN LK_ MIL MIL 0 U VPU_IO VPLLI/O VRI/O_ VRI/O_ VRI/O_ VI/OMHZ V VPI VREF VR VPU V X X REF/FL/TET_EL FL/TET_MOE U/FL PI_F/ITP_EN PI/_EL PI PI/TME PI/R#_ PI0/R#_ PI_TOP# PU_TOP# PU_F_LR PUT_F_LR PU_LR0 PUT_LR0 RT_LR0 R_LR0 RT_LR R_LR PU_ITP_LR/R PUT_ITP_LR/RT R_LR RT_LR RT_LR R_LR 0 RT_LR/TLKT R_LR/TLK OTT/RT_LR0 OT/R_LR0 0 LK_PIE_LN#_R LK_PIE_LN_R REFLK_ REFLK_# R N_0K_J 00 LK_MH_LK# LK_MH_LK LK_PU_LK# LK_PU_LK LK_PIE_WLN LK_PIE_WLN# LK_PIE_ 0 LK_PIE_# 0 LK_IH_MI# LK_IH_MI EXP_LKIN EXP_LKIN# R0 0K_J 00 LK_IH_T LK_IH_T# N PM_TPPI# PM_TPPU# PU Wireless WWN MI R0 _J 00 R _J 00 R 00 R0 00 N LK T REFLK REFLK# LK_PIE_LN# LK_PIE_LN LN LK_IH PLK_FWH LK_IH_PI LK_KPI LK_IH EL F For EMI EL F N_P_0V_J 00_NPO N_P_0V_J 00_NPO N_P_0V_J 00_NPO N_P_0V_J 00_NPO N_P_0V_J 00_NPO EL0 F PU F 0 00M X 0 0 M M 0 M M M 00M M 0M Reserved +VRUN R 0K_J 00 R 0K_J 00 R 0K_J 00,, PLKLK PLKLK PLKLK M_LK M_T REFLK REFLK# R 00 R 00 R 00 R 00 REFLK_ REFLK_# 0 LK T FIX/RT_LR/E /R_LR/E N_ N_ N NPI NREF NR_ NR_ NR_ NPU THERML P R_LR/R#_ RT_LR/R#_H 0 R_LR/R#_E RT_LR/R#_F 0 R_LR/R#_ RT_LR/R#_ K_PWR/P# N R#_ R#_H K_PWR +VRUN R 0K_J 00 Q N00. K_PWR IMVP_LK_EN# WLN_LKREQ# 0 _LKREQ# R R R#_H R#_ R 0K_J 00 R 0K_J 00 +VRUN ILPRYLFT setting table PIN NME ERIPTION LRKLFT PI0/R#_ PI/R#_ PI/TME PI PI/M_EL PI_F/ITP_EN RT/R#_ yte, bit 0 = PI0 enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R0 or R pair yte, bit 0 = R#_ controls R0 pair (default), = R#_ controls R pair yte, bit 0 = PI enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R or R pair yte, bit 0 = R#_ controls R pair (default) = R#_ controls R pair 0 = Overclocking of PU and R llowed = Overclocking of PU and R NOT allowed 0 = Pin as R-, Pin as R-#, Pin as OT, Pin as OT# = Pin as MHz, Pin as MHz_, Pin as R-0, Pin as R-0# 0 =R/R# = ITP/ITP# yte, bit 0 = R enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R0 or R pair yte, bit 0 = R#_ controls R0 pair (default), = R#_ controls R pair PIN NME R/R#_ R/R#_E RT/R#_F R/R#_ RT/R#_H ERIPTION yte, bit 0 = R enabled (default) = R#_ enabled. yte, bit 0 controls whether R#_ controls R or R pair yte, bit 0 0 = R#_ controls R pair (default) = R#_ controls R pair yte, bit 0 = R# enabled (default) = R#_F controls R yte, bit 0 = R enabled (default) = R#_F controls R yte, bit 0 = R# enabled (default) = R#_ controls R yte, bit 0 = R enabled (default) = R#_H controls R0 P LOK EN MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

19 Use E to implement power limit Wireless switch should use U., reserve U.00 / for detecting voltage level (efault setting -- Hardware Power Limit) +EV If use E to implement, it should do setting as below. 00m +VRUN tuff 0,, R, R, PR, PR, PR N R, PR, PU, P, P, PR, PR, PR P_0V_J 00_NPO 0U_.V_Y 00_YV 0.U_V_M 00_XR 0.U_V_M 00_XR 0.U_V_M 00_XR 0.U_V_M 00_XR 0.U_V_M 00_XR 0U_.V_Y 00_YV 0.U_V_M 00_XR P_0V_J 00_NPO H00H-0PT H_RIN#_ H_RIN# T_WLN_W# E_VPT 0, PWRW# +EV R PWRW# R0 LI witch R N_ 00 N_0.0U_.V_K 00_XR +EV PWRW#_R LIIN# POWER_LOE_P_00 E_/PIO R K_J R00.K_J PM_THRM# FN_TH E_IPT R 0 N_0.0U_.V_K 00_XR POWER_LOE_P_00 0, LIIN# 0 WWN_PWR_EN PM_LP_# 00P_V_K 00_XR IN_E HRE_TRL LW_PWR TT_PR# 0, FX_PWR 00_RT# tpc0t_0 TP, R_PWR _OFF tpc0t_0 TP LN_PWR_EN tpc0t_0 TP 0 ETX 0 ERX PM_LP_# +EV PM_THRM#_E LIIN# E_/PIO PM_LP_# PWRW#_R IN_E YTEM_I YTEM_I0 E_TRIT# PM_LP_# VREF 0/PIO0 /PIO /PIO /PIO PIO0 PIO0 PIO0 PIO0 0/PIO /PIO /PIO PIO V V V V V / / PIO TK/PIO PIO PIO/TM (wake-up PIO/TI capability) PIO0/TO PIO/RY# PO/TET# PO/TRIT# PIO (no wake-up capability) ER OUT_R/PO/XORTR# PIO/IN_R PIO0 V 0 V LP M PI IR FIR U LPP#/PIO0 LREET# LLK LFRME# PIO L0 L L L ERIRQ LKRUN#/PIO KRT#/PIO PIO/0 EI#/PIO MI#/PIO PWUREQ#/PIO PIO PIO /PIO L/PIO /PIO L/PIO /PIO L/PIO PIO PO/HM PIO PIO PIO/TRT# PIO PIO PIO0 PIO PIO PIO T_WLN_W#_P PLT_RT# LK_KPI LK_00 H_RIN#_ H_0TE_ RUNTIME_I#_ T_M_R R0 00_F 00 LK_M_R R0 00_F 00 M_THRM_T M_THRM_LK MOEL_I HM PM_RMRT#_R R0 LL_Y_PWR_E T_00 R N_ 00 PLT_RT#,,0,,0,, LK_KPI LP_FRME#,0 LK_00 LP_0,0 LP_,0 LP_,0 LP_,0 INT_ERIRQ,0 PM_LKRUN#,0 H00H-0PT H00H-0PT TP TP TP tpc0t_0 tpc0t_0 tpc0t_0 POWER_LOE_P_00 R0 N_ 00 T_00 WLN_EN, OVT_E#,, T_WLN_W# RUNTIME_I# EXTMI# WKE_I# OP_#, WWN_EN,0 T_M LK_M M_THRM_T M_THRM_LK RUN_ON,0, PM_RMRT# LL_Y_PWR, U_ON,,0, PLOK_LE H00H-0PT H_0TE_ LK_KPI LK_M T_M MU hannel.k_j 00 M_THRM_LK M_THRM_T MU hannel 0 0K 00_PR PM_THRM#_E T_WLN_W# T_PR# WLN_EN changes to HIH enable 0 N_0P_0V_J 00_NPO RP RP R0 0K_J 00 R0 0K_J 00 R 0K_J 00 +VLW +VRUN +VRUN +VU H_0TE 0.U_V_M_ 00_XR U_0V_K 00_XR VORF N N N N N N N 0 NPEL0X PM_LP_# PM_LP_# PM_LP_# RUN_ON U_ON LW_ON RUN_ON R 00K_J 00 R 00K_J 00 R 00K_J 00 R 00K_J 00 R 00K_J 00 R 00K_J 00 R 00K_J 00 HM PLT_RT# R.K_J K_J R KXLKO P_0V_J 00_NPO +VRUN M0 0K Y T/P RP.KHZ_.P_0PPM 00_PR R0 0M_J 00 KXLKI P_0V_J 00_NPO LK_TP T_TP ,0, PI_ROM_I PI_ROM_O PI_ROM_# PI_ROM_LK FN_PWM UPEN_LE POWER_LE NUMLOK_LE +_0V_PWR L_OFF# HRE_LE RLOK_LE PWRTN# LW_ON T_PR# IMVP_VR_ON ENH# PM_LP_# tpc0t_0 PI_ROM_O TP R.K_J 00 T_ON RUN_ON PWRLIMIT# M_RT_ET# T_TP LK_TP T_PR# KXLKI KXLKO MOEL_I0 LW_ON_R T_TP LK_TP PI_ROM_I PI_ROM_O_R R0 _J 00 PI_ROM_LK_R R _J 00 N_000P_0V_K 00_XR 0 00 R N_ 0 0 U KX/KLKIN KX LKOUT/PIO _PWM/PIO _PWM/PIO _PWM/PIO _PWM/PIO E_PWM/PIO F_PWM/PIO0 _PWM/PIO H_PWM/PIO T/PIO T/PIO T/PIO0 T/PIO0 PIO PIO PT/PIO PLK/PIO PT/PIO PLK/PIO PT/PIO PLK/PIO F_I F_O F_0# F_K NPEL0X P/ FIU KOUT0/JENK# KOUT/TK KOUT/TM 0 KOUT/TI KOUT/JEN0# KOUT/TO KOUT/RY# KOUT K KOUT KOUT/P_VI# 0 KOUT0_P0_LK KOUT_P0_T KOUT/PIO KOUT/PIO KOUT/PIO KOUT/PIO/XOR_OUT KOUT/PIO0 KOUT/PIO KIN0 KIN KIN KIN KIN KIN KIN KIN V_POR# 0 KO0 KO KO KO KO KO KO KO KO KO KO0 KO KO KO KO KO KI0 KI KI KI KI KI KI KI ERT# KO0 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO0 0 KO 0 KO 0 KO 0 KO 0 KO 0 TP tpc0t_0 TP tpc0t_0 KI0 0 KI 0 KI 0 KI 0 KI 0 KI 0 KI 0 KI 0 +EV N_0K_J R 00 N_0K_J R 00 YTEM_I0 YTEM_I +EV YTEM I0- R R 00K_J R 00 H00H-0PT 00K_J 00K_J Place at E side. E REET ERT# 0.U_V_M_ 00_XR R POWER_LOE_P_00 P FORE_OFF# E (NPEL) MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

20 MFIX MFIX +VRUN F 0V-0._0 0L0 LK_TP +VRUN_TP +VRUN_TP 0.U_V_M 00_XR Touch Pad ONN. N LEFT# RIHT# FP ONN_P KOTL_F0-V0 T_TP N_0P_0V_J 00_NPO Touch Pad Left utton W T00-0L-00_W-TT Right utton W T00-0L-00_W-TT VR N_MLV00M0_VR LEFT# RIHT# VR KO 00P_0V_J 00_NPO 00P_0V_J 00_NPO KO 00P_0V_J 00_NPO KI 00P_0V_J 00_NPO KO 00P_0V_J 00_NPO KO 00P_0V_J 00_NPO KO 00P_0V_J 00_NPO KO 00P_0V_J 00_NPO KO0 KI 00P_0V_J 00_NPO Place these caps close to N. KO KO KI KO0 KI KI KO KO KO KO KO0 KI N KO KO KI 0 KO0 KI KI KO KO 0 KO KO KO0 KI FP ONN_P Keyboard KO KO KO KO KO KO KI KI KO KO KO KO KO KO KO KO KI KI KO KO KI KI KI0 KI0 FOX_0--H N_MLV00M0_VR FT Test Point for Touch Pad (OTTOM side) tpc0b_00 tpc0b_00 TP00 TP0 N LEFT# tpc0b_00 TP tpc0b_00 tpc0b_00 TP0 TP RIHT# T_TP tpc0b_00 tpc0b_00 TP TP tpc0b_00 tpc0b_00 TP TP LK_TP +VRUN_TP tpc0b_00 TP FT Test Point for Keyboard (OTTOM side) KI KO KO KI tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 tpc0t_ TP0 PI_ROM_# PI_ROM_I_R PI_ROM_WP# N +EV PI_HOL# PI_ROM_LK PI_ROM_O 0.U_0V_K 00_XR +EV LI witch U V OUT N N LIIN#, MRM0 EXTERNL PI ROM INTERFE +EV LP_0 LP_0, PI_ROM_LK LP_ LP_ PI_ROM_LK, LP_ LP_, PI_ROM_O LP_ LP_FRME# PI_ROM_O 0, LP_ LP_FRME#, PI_ROM_I PI_ROM_I LP_RQ0# I_LP_PI# PI_ROM_# PI_ROM_# PM_U_TT# 0 MIL TP M_FLH_EN M_FLH_EN,,,,0,, PLT_RT# PLT_RT# PM_LKRUN# PM_LKRUN#, R_INERT, INT_ERIRQ INT_ERIRQ PLK_FWH MIL TP, PWRW# PWRW# +VRUN 0 +VRUN R R +EV PI_RT#_JI N_0K_J ERX ERX 00 ETX ETX MIL TP POWER_LOE_P_00 _RT# 0 +EV ebug Port N MFIX MFIX MFIX MFIX PI_RT# +EV +EV +EV N N_FP_P FOX_RF0-00-F TO ONN_xP FOX_QT00-L0-F PI_ROM_I R 0K_J 00 R _J 00 R 0K_J 00 PI_ROM_# PI_ROM_I_R PI_ROM_WP# IO ROM U # V O/IO HOL#/IO WP#/IO LK N I/IO0 FLH_OI-P_M WQVI PI_HOL# PI_ROM_LK PI_ROM_O 0.U_V_M_ 00_XR P_0V_J 00_NPO R 0K_J 00 P K/TP/ebug Port MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet 0 of

21 For EMI (lose to JM) +.V_LN 0 0.U_V_K 0.U_V_K N_0U_0V_M 00_XR 00_XR 00_XR closed pin# closed pin# closed pin# +.V_LN _T0/X_0/M_0 _T/X_/M T/X_/M T/X_/M_ X_/M_ X_/M_ X_/M_ X_/M M/M_/X_WE# _LK/M_LK/X_# R0 _J 00 R00 _J 00 R _J 00 R _J 00 R0 _J 00 R0 _J 00 R0 _J 00 R0 _J _J R R0 _J 00 R_0 R_ R_ R_ R_ R_ R_ R_ R_M_M _LK/M_LK/X_#_ 0 N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO 0 N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO N_0P_0V_J 00_NPO LN&RPower OFF(atteryonly) +VLW 0 mils R U_0V_K M_J 00_XR P_0V_K 00_XR R N_ 00 0 mils +V_LN 0.U_V_K 0.U_V_K 0.U_V_K N_0U_0V_M 00_XR 00_XR 00_XR 00_XR closed pin# closed pin# closed pin# closed pin# E ontroll LN_PWR_EN R POWER_LOE_P_00 N_0.U_V_M 00_XR R 00K_J 00 Q N00. Q FN0P +V_LN +V_LN +V_LN _LK/M_LK/X_# _M/M_/X_WE# _T/X_/M WP#/X_WP# X_LE MIL TP 0.U_V_K 0.U_V_K 0.U_V_K N_0U_0V_M 00_XR 00_XR 00_XR 00_XR closed pin# closed pin# closed pin# closed pin# +V_LN 0.U_V_K 0.U_V_K 0.U_V_K N_0U_0V_M 00_XR 00_XR 00_XR 00_XR closed pin# closed pin# closed pin# closed pin# +.V_LN +.V_LN +V_LN MI0+ MI0- MI+ MI- TP MIL TP MIL _T/X_/M T/X_/M T0/X_0/M_0 0 0 LE0 LE V_ N_ VIP_ VIN_ V VIP_ VIN_ N_ V VIP_(N) VIN_(N) V(N) VIP_(N) VIN_(N) MIO0 MIO MIO VIO MIO MIO MIO N_ 0 MIO MIO VIO_ MIO MIO MIO0 MIO MIO REXT VX XIN XOUT N_ LX F VRE LKN LKP VH RXP RXN N_ TXN TXP X_/M_ X_/M_ X_/M_ X_/M_ X_RE# MIO ingle End = 0 ohm U N_ MIO 0 MIO M_/R_LEN TETN VIO_ V_ VO R_0N R_N M_L/LE REQN MP 0 WKEN RTN VTX MIL TP0 X_R/# X_LE _R_0N M_R_N M_L R_PPE# MP PIE_WKE# RTN +.V_LN +V_LN MIL TP +V_OUT MIL TP M_/R_LE PIE_WKE#, R POWER_LOE_P_00 N_0.U_V_K 00_XR R R R 0 N N N N 0 N N isable E Enable E() N 00K N 0.u Enable E(). For JM/ only.. MP connect to Main Power or RTN for E application, to UX power otherwise. R N_ 00 R N_00K_J 00 +V_LN +VRUN Function 0 JM REXT R0 K_F 00 LNXIN LNXOUT RELX PIe ifferential Pairs = 00 ohm PIE_RXP_JM 0 0.U_V_K PIE_RXN_JM LN_RXP 0.U_V_K LN_RXN R K_J 00 PLT_RT#,,,0,0,, ard Reader Pull High/Low Resistors +V_LN +V_R R.K_J 00 R.K_J 00 R 0K_J 00 R 0K_J 00 M_R_N _R_0N _M/M_/X_WE# _WP#/X_WP# MHz rystal LNXIN HOONI_EF.0000F Y LNXOUT MHZ_P_0PPM R N_M_J 00 P_0V_J 00_NPO 0 P_0V_J 00_NPO +V_LN +.V_LN +V_LN +V_LN 0.U_V_K 0U_0V_M 00_XR 00_XR LN_TXN LN_TXP LK_PIE_LN LK_PIE_LN# N_R R K_J 00 X_R/# External EEPROM for M address MF0 saves M address in IO U 0 N V WP L N_EEPROM_OI-P_K T0N-H-T +V_LN N_0.U_V_K 00_XR R N_.K_J 00 +V_LN R N_.K_J 00 M_L M_/R_LE Internal witching Regulator +.V_LN L RELX (0mil) (0mil).UH_.x.x. PH0-RM closed to chip. 0U_0V_M 0.U_V_K 00_XR 00_XR +V_OUT +V_R +V_R R POWER_LOE_P_00 0U_0V_M U_0V_K.U_V_Y 00_XR 00_XR 00_YV tpc0t_ TP _R_0N tpc0t_ TP _WP#/X_WP# tpc0t_ TP0 N FTTestPointforard(OTTOMside) 00 0.U_.V_K 00_XR R_ R_ R LK/M_LK/X_#_ R_M_M R_ M_R_N R_ R_ R_0 R LK/M_LK/X_#_ R_M_M R_ R_ R_0 R R_0N _WP#/X_WP# 0 0 T V_ T T V LK M T IN V T T V T0 T LK V_ V T T T0 T etect ommon Write Protect MFIX MFIX N R0 0 N_R R0 0 N_R OKET_P YMIHI_FR0-00- N_R P LN + in R - JM MF 0. ize ocument Number Rev Wednesday, March, 00 ate: heet of

22 +.V_LN R PTH PTH 0 PTH PTH RJ_ RJ_ RJ_ RJ_+ RJ_ RJ_+ N MOULR JK ONN_P FOX_JM-R0-H Zdiff = 00 Ohm RJ_ RJ_ RJ_ RJ_ 0 MI0+ MI0- MI+ MI- L TX+ T+ T T TX- T- RX+ R+ T T RX- R- -_0UH LF-HP- N_ 00 MI0+ MI0- MI+ MI- N_R RJ_+ RJ_+ FT Test Point for RJ (OT side) tpc0t_ tpc0t_ tpc0t_ tpc0t_ TP TP TP TP RJ_ RJ_ RJ_ RJ_+ tpc0t_ TP RJ_ tpc0t_ TP RJ_+ R0 _J 00 R _J 00 R _J 00 R _J 00 U_ 00P_KV_K 0_XR 0 0.U_V_M 00_XR 0 0.U_V_M 00_XR 0, 0 close to Pin, Pin of L each Place close to L N_TR 0 0.U_0V_K 00_XR 0 000P_0V_K 00_XR N_TR P Transformer & RJ MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

23 +VRUN udio Power +V_UIO L 00R-00MHZ_00 HP0Z-0T0 +V_UIO_ R N_ 00 +V_UIO +VRUN +V_PV +VRUN R 00 P_0V_J 00_NPO 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0U_0V_M 00_XR 0.U_0V_K 00_XR +VRUN 0 0U_0V_M 00_XR 0 0.U_0V_K 00_XR P_0V_J 00_NPO +V_UIO U_0V_K 00_XR U0 IN OUT HN# N ET -TUF 0 0.U_0V_K 00_XR N_UIO 0U_0V_M 00_XR close to U pin close to U pin H_PKR, R K_J 00 OP_# MUTE_POP# PN H_OE_TIN0 H_OE_TOUT, H_OE_RT# H_OE_YN 0.U_0V_K 00_XR N_UIO +V_PV PN N_UIO U V V_IO PV PV H_OE_ITLK LK N_P_0V_K 00_NPO U_EP# EP U_P_EEP TP MIL U_PIF_OUT PIFO Z_PKR_R Trace width> U_P_EEP 0.U_0V_K 00_XR mils PEEP R 0 P# 00P_0V_J.K_J 00_NPO U_VREF 00 VREF LO_P 0U_0V_M 00_XR 0U_0V_M PV R 00 PV 00_XR V V R0 N_ 00 THERMLP V LQ-V-R lose to odec MI_T PIO0/MI_T MI_LK PIO/MI_LK R _J ZIN0 00 T_IN T_OUT 0 REET# YN V V MI_L MI_R MI_L MI_R LINE_L LINE_R LINE_L LINE_R HPOUT_L HPOUT_R PK_OUT_L- 0 PK_OUT_L+ PK_OUT_R- PK_OUT_R+ MONO_OUT 0 MI_VREFO_L MI_VREFO_R 0 MI_VREFO ENE ENE N_UIO MI_L.U_0V_K 00_XR MI_R.U_0V_K 00_XR HPOUT_L HPOUT_R ENE_ U_JREF JREF U_N N U_P P PVEE P_0V_J 00_NPO R _J 00 R _J 00.U_0V_M 00_XR H_PKL- H_PKL+ H_PKR- H_PKR+ MI_VREFO_L MI_VREFO_R.U_0V_M 00_XR R 0K_F 00 N_UIO EXT_MI_L EXT_MI_R HP_JK_L HP_JK_R ENE_ R.K_F 00 R 0K_F 00 HP_JK_J# EXT_MI_J# N_UIO R R 0 0.U_.V_K R 00 R 00 00_XR N_UIO PN N_UIO P udio odec LQ MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

24 H_PKL+ H_PKL- H_PKR+ H_PKR- R 00 R 00 R 00 R 00 INTPKL+_ON INTPKL-_ON INTPKR+_ON INTPKR-_ON MFIX MFIX FOX_H0E-LH HEER ONN_P JPK +VLW +V_LW 000P_0V_K 00_XR 000P_0V_K 00_XR 000P_0V_K 00_XR 000P_0V_K 00_XR +VLW R N_M_J 00 FT Test Point for peaker (OTTOM side), OP_# MUTE ONTROL R 0K_J 00 MUTE_POP Q0 LT R MUTE_POP# 0K_J Q 00 LT 0.U_0V_K 00_XR INTPKL+_ON INTPKL-_ON INTPKR+_ON INTPKR-_ON, H_OE_RT# R 00K_J 00 MI_VREFO_L MI_VREFO_R U_EP# NW HP ONN N_ R 00 EXT_MI_L EXT_MI_R EXT_MI_J# RP.K 00_PR EMI E R 00 R P_0V_J 00_NPO EXTERNL MIROPHONE HP_JK_R Q N00W N_UIO N_UIO MUTE_POP# MUTE_POP# Q N00W R 00 R 00 FOR EMI E _HP_R_ON _HP_L_ON HP_JK_J# _HP_L_ON _HP_R_ON HEPHONE _N HP_JK_L R M_J 00 NW tpc0b_00 TP tpc0b_00 TP tpc0b_00 TP tpc0b_00 TP0 R 00 K_J R 00 K_J VR _N ERPHONE ONN_P 00P_0V_J INTRON_J--0 00_NPO N_MLV00M0_VR N00W Q _HP_R HP_L_ Q N00W R 00 VR N_MLV00M0_VR 0P_0V_K 00_XR 0P_0V_K 00_XR ERPHONE ONN_P INTRON_J--0 N_UIO N_ N_UIO N_UIO N_UIO P MI & udio Jack MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

25 +VRUN +VRUN_H +VRUN +VRUN_H R. 0. N_ R N_0U_.V_M 00_XR N_0.U_0V_K 00_XR Reserved P + N_U_0V_.x.x. TEPLMR MPT +VRUN_H 0 0.U_V_M 00_XR T_TXP0_ T_TXP0 0.0U_0V_K 00_XR T_TXN0_ T_TXN0 0.0U_0V_K 00_XR T_RXN0_ T_RXN0 0.0U_0V_K 00_XR 0.0U_0V_K 00_XR T_RXP0_ T_RXP0. 0U_0V_M 00_XR 0U_0V_M 00_XR P_0V_J 00_NPO +VRUN_H P_0V_J 00_NPO 0. N TX N_M TX# N_M RX# N_M RX N_M_P_ V_._ N_M_P_ V_._ N_M_P_ 0 V_. P N_M_P_0 V_.0 P V_.0_ N_M_P_ V_.0_ P_REERVE_ PTH PTH 0 V P V V T ONN_P FOX_LF-KLH T H ONN. P T H MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

26 Terminal Resistor RE_V RE_V R 0_F 00 REEN_V REEN_V R 0_F 00 Filter ircuit ( pole) L 0P_0V_J_N 00_NPO L 0P_0V_J_N 00_NPO R-00MHZ_00 T000 RT_R_ON P_0V_J 00_NPO R-00MHZ_00 T000 RT ON P_0V_J 00_NPO E Protection ircuit +VRUN RT_R_ON VW +VRUN RT ON VW 0.U_V_M 00_XR R routing. from H to the first 0 ohm resistor: mils(min. mils spacing ). from the first 0 ohm res. to the second 0 ohm resistor: mils. from the second 0 ohm resistor to connector: mils. spacing minimum mils, 0 mils spacing is recommended. R,, should be length matched to 00 mils, max. length is 00 mils. R,, signals should be ground referenced +VRUN 0 MPT _HIFT_+VRUN F V-0._0 0L0 0.U_V_M 00_XR RT_+VRUN U_0V_K 00_XR RT_R_ON RT ON RT ON RT_ET# N0 0 V ONN_P FOX_Z-N-H _T_ON HYN_ON VYN_ON _LK_ON LUE_V LUE_V L R-00MHZ_00 T000 RT ON RT ON +VRUN N_V R 0_F P_0V_J_N 00_NPO P_0V_J 00_NPO VW R0 N_ 0 Place E iodes Near -ub onn. N_V The 0 Ohm resistors near V connector and minimizing length to filter. The filters to V connector maximum distance 00 mils. +VRUN Level hifter for U V LK +VRUN +VRUN RT_+VRUN R R K_J K_J R.K_J R.K_J _LK_ON HYN_V 0U_0V_M 00_XR NZP U OE# +VRUN R _J 00 HYN_ON N_P_0V_J 00_NPO M_RT_ET# R N_ 00 N_000P_0V_M 00_XR RT_ET# +VRUN N_VPT R 00 V T Q N00W _T_ON 0U_0V_M 00_XR U R Q N00W VYN_V NZP OE# _J 00 VYN_ON N_P_0V_J 00_NPO P V onnector (-ub) MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

27 U_PWR0,,0, U_ON +VLW 0.U_V_K 00_XR U_ON U_V_K 00_XR. U EN(EN#) O# IN_ OUT_ IN_ OUT_ N OUT_ PU U_O#0 U_PWR0 0.U_V_K 00_XR U_O#0 U_PN0 U_PP0 R0 00 L 0 N_0R-00MHZ_0R R0 00 P 0U_.V_R + TPE0MZ N 0 0P_0V_K 00_XR 0 N N_RJ U_PN0_ U_PP0_ V V- V+ N NPTH NPTH PTH PTH N U REEPTLE_P FOX_U-0-H U_PWR R00 00 P 0U_.V_R + TPE0MZ 0P_0V_K 00_XR 0.U_V_K 00_XR +VLW U_ON U_V_K 00_XR. U_O# U_PWR 0.U_V_K 00_XR U_O# U_PN U_PP L 0 N_0R-00MHZ_0R R0 00 N N N_RJ U_PN_ U_PP_ V V- V+ N NPTH NPTH PTH PTH N U REEPTLE_P FOX_U-0-H U_PWR 0.U_V_K 00_XR +VLW U_ON U_V_K 00_XR. U EN(EN#) O# IN_ OUT_ IN_ OUT_ N OUT_ PU U_O# U_PWR 0.U_V_K 00_XR U_O# U_PN U_PP R0 00 L0 0 N_0R-00MHZ_0R R0 00 P 0U_.V_R + TPE0MZ N 0P_0V_K 00_XR N N_RJ U EN(EN#) O# IN_ OUT_ IN_ OUT_ N OUT_ PU U_PN_ U_PP_ V V- V+ N NPTH NPTH PTH PTH N U REEPTLE_P FOX_U-0-H P U onnector x MF 0. ize ocument Number Rev ustom ate: Wednesday, March, 00 heet of

28 +VRUN MI_T MI_LK R 00 00m N_ R0 F U_PP U_PN R _J 00 R _J 00 V-0._0 M0P00TF 00 WEM & MI 0P_0V_J 00_NPO 0P_0V_J 00_NPO U_V 0 0U_0V_Y 00_YV R0 00 R0 00 U_0V_Y 00_YV U_PP_F U_PN_F U_V MI_T_F MI_LK_F P_0V_J 00_NPO U_V 0P_0V_K 00_XR MFIX MFIX 0 N HEER_P FOX_H0E-LH +LV LV onn. LV_RXIN0+ LV_RXIN0- L_T_EI L_LK_EI L_LTL LV_LKIN+ LV_LKIN- LV_RXIN+ LV_RXIN- LV_RXIN+ LV_RXIN- R 00 +LE_V R INV_RJ POWER_LOE_P_00 +LV_ 0.U_V_M 00_XR 0.U_V_M 00_XR N_.P_V_ 00_OH N_.P_V_ 00_OH N_.P_V_ 00_OH N_.P_V_ 00_OH 0U_.V_M 00_XR P_0V_J 00_NPO P_0V_J 00_NPO MFIX NPTH UMMY P MFIX MFIX UMMY P NPTH MFIX N FP ONN_0P FOX_0-0-H lose to N FT Test Point for amera (OTTOM side) MN R0 00 tpc0t_ TP tpc0t_ TP U_PP_F U_PN_F MN L ore Power +LV tpc0t_ TP U_V tpc0t_ TP0 tpc0t_ TP tpc0t_ TP MI_T_F MI_LK_F +VRUN Inrush 00m normal 0m.U_.V_K 00_XR 0.U_.V_K 00_XR MN.U_.V_K 00_XR U IN IN IN OUT EN IN IN N THERML P RU_V0. L_LVEN LE acklight Power +VRUN,0 LIIN# L_LEN +VRUN U NZ0P R N_ 00 L_OFF# INV_ENLE_ +VRUN U NZ0P R N_ 00 N_0.U_0V_K 00_XR INV_ENLE N_0.U_.V_M 00_XR R 00K_J 00 R 00K_J 00 R 00K_J 00 Q0 N00. N_0.0U_V_M 00_XR Q FN0P R N_ 00 F V-0._0 0L0THYR L +LE_V 0R-00MHZ_00 EM00 0.U_V_M 00_XR +LE_V 0 0.U_V_M 00_XR P LV & WEM MF 0. ize ocument Number Rev ustom ate: Wednesday, March, 00 heet of

29 MFIX MFIX +VRUN +VRUN +VRUN +VLW Power LE RLOK LE /reen LTT-KKT LE TP tpc0b_00 NUM LE /reen TP tpc0b_00 P LE /reen TP tpc0b_00 tpc0b_00 TP R TP tpc0b_00 R N_0K_J 00 tpc0b_00 TP R R 00 R N_0K_J 00 Q Q RLOK_LE N00. NUMLOK_LE N00. PLOK_LE reen R POWER_LE UPEN_LE Q N00W Q N00W +V_LN HRE_LE harge LE /Umber +VLW +VRUN H LE /Yellow +VRUN Q N00. R LE /Yellow Q N00W +V_LN TP tpc0b_00 Power witch W PWRW#,0 H0_W-MP FT Test Point for Power witch (OTTOM side) tpc0b_00 TP PWRW# tpc0b_00 TP +VU Wireless witch Orange TP tpc0b_00 LTT-KKT LE LTT-KKFKT LE tpc0b_00 TP0 R 00 TP tpc0b_00 LTT-KKT LE tpc0b_00 TP Q N00. HT-U LE TP0 R 00 TP Q0 N00. tpc0b_00 tpc0b_00 H_LE# R 0K_J 00 Q N00. HT-UY LE TP R 00 TP tpc0b_00 tpc0b_00 M_/R_LE R 0K_J 00 TP tpc0b_00 R 00 TP tpc0b_00 Q N00W LE HT-0UY VR N_MLV00M0_VR FPT RF_LE# E Q TYU TP R 0 00 TP tpc0b_00 tpc0b_00 W H_W-MP 0 0.U_V_M_ 00_XR T_WLN_W#, WLN_EN WLN_LE# Q N00W T_LE,0 WWN_EN Q R N00W K_F 00 Q N_N00. LTT-KKT LE Wireless LE /reen P Power witch & LE MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

30 For MF0 MP, these components are N in this page. +V_LW_ +VLW WWN_+_V +VLW R N_K_J 00 R N_00K_J 00 Q. Q. N_0U_.V_M 00_XR N_P_0V_J 00_NPO WWN_+_V +VRUN : 00m MX WWN_+_V P + N_0U_.V_R TPE0MZ WWN_PWR_EN Q N_N00W N_N00W WWN_+_V 0 N_P_0V_J 00_NPO N_0U_.V_M 00_XR _LKREQ# LK_PIE_# LK_PIE_ WWN_RXN WWN_RXP WWN_TXN WWN_TXP R N_ 00 R N_ 00 R N_ 00 R N_ 00 R N_ 00 R N_ 00 WWN_+_V UIM_PWR UIM_T UIM_LK UIM_RT_N WWN_EN_ WWN_+_V UIM_PWR R POWER_LOE_P_00 U_PN U_PP R POWER_LOE_P_00 WWN_EN WWN_+_V WWN_EN, PLT_RT#,,,0,,, WWN_+_V R N_0K_J 00 WWN_EN Full ize Mini ard R 00 N_ U_PP U_PN UIM_PWR 0 N_0.0U_V_M 00_XR N_ON00L N_0.U_V_K 00_XR N_000P_0V_K 00_XR N_0.U_.V_K 00_XR N_0U_.V_M 00_XR N_0U_.V_M 00_XR R N_ 00 R N_0K_J 00 L 0 N_0R-00MHZ_0R N N N_RJ MFIX MFIX N WKE# T_T T_HLK LKREQ# N REFLK- REFLK+ N UIM_ UIM_ N PERn0 PERp0 N N PETn0 PETp0 N0 N +.VUX +.VUX N REERVE REERVE REERVE REERVE +.VUX N +_V UIM_PWR UIM_T 0 UIM_LK UIM_RT# UIM_VPP N 0 W_ILE# PERT# +.VUX N +_V M_LK 0 M_T N U_- U_+ 0 N LE_WWN# LE_WLN# LE_WPN# +_V 0 N +.VUX N_PI_*P FOX_0-0T-H R 00 N_ MFIX MFIX W W W W IM PREENE N_ IM I/O IM LK VPP IM RT N_ IM V N N_IM R ONN_P FN_MF0--0 IM ONN. UIM_U- UIM_U+ UIM_T UIM_LK UIM_RT_N UIM_PWR N_TVPT N_TVPT R N_0K_J 00 UIM_PWR N_U_.V_M 00_XR P Mini PIE - MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet 0 of

31 +VU +VU : 00m MX +V_WLN +_VRUN +_VRUN : 0m MX +_V_WLN R R power_close_gap_00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR 0.U_.V_K 00_XR 00 0.U_.V_K 00_XR 0 0U_.V_M 00_XR 0 0U_.V_M 00_XR P_0V_J 00_NPO POWER_LOE_P_ U_.V_K 00_XR 0 0U_.V_M 00_XR +_V_WLN, PIE_WKE# TP tpc0t_0 N +V_WLN T_HT T_HLK R0 R WLN_LKREQ# LK_PIE_WLN# LK_PIE_WLN WLN_RXN WLN_RXP WLN_TXN WLN_TXP POWER_LOE_P_00 POWER_LOE_P_00 +V_WLN WLN_T WLN_LK MFIX MFIX WKE# T_T T_HLK LKREQ# N REFLK- REFLK+ N UIM_ UIM_ N PERn0 PERp0 N N PETn0 PETp0 N0 N +.VUX +.VUX N REERVE REERVE REERVE REERVE +.VUX N +_V UIM_PWR UIM_T 0 UIM_LK UIM_RT# UIM_VPP N 0 W_ILE# PERT# +.VUX N +_V M_LK 0 M_T N U_- U_+ 0 N LE_WWN# LE_WLN# LE_WPN# +_V 0 N +.VUX WLN_ON U_PN_L U_PP_L R0 POWER_LOE_P_00 R 00 R 00 WLN_LE# WLN_LE# WLN_EN, PLT_RT#,,,0,,0, U_PN U_PP PI_*P FOX_0-0T-H R N_ 00 P + 0U_.V_R TPE0MZ 0 0U_.V_M 00_XR P_0V_J 00_NPO Half ize Mini ard +VLW T_V luetooth ONN. 0 U_0V_K 00_XR T_ON 0m U VIN VOUT N EN N T0-.KER 0 0.U_0V_K 00_XR L 0.UH_00 TL00-RM 0.U_.V_M 00_XR T_PR# MIL TP T_WKEUP T_HLK MFIX N T_LE T_PP_W T_PN_W T_HT 0 MFIX TO _xp P_0V_J FOX_QT00-H-H 00_NPO T_V RP0 0 00_PR T_LE U_PP U_PN tpc0t_ TP T_PR# tpc0t_ TP tpc0t_ TP T_V N FT Test Point for luetooth (OTTOM side) P Mini PIE - WIFI & T MF 0. ize ocument Number Rev ustom ate: Wednesday, March, 00 heet of

32 P Reserved MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

33 PU Thermal ensor +VRUN H_THERM place close to thermal sensor H_THERM FORE_OFF#,,,0,,0, PLT_RT# 0 00P_0V_K_ 00_XR Q N00. H_THERM H_THERM O#_O R 0K_J U_V_M_ 00_XR U V MLK P MT N LERT# THERM#/R N EM--ZL-TR Mus ddress: /H Remote for PU N_U_0V_K 00_XR R.K_J 00 M_THRM_LK M_THRM_T PM_THRM# +VRUN FN +VRUN FN_PWM U_0V_K 00_XR R FN_PWM_ POWER_LOE_P_00 000P_0V_K 00_XR 00m R K_J 00 Q HT0PT E Q TEU R.K_J 00 0.U_0V_K 00_XR N_MLLPT 0.0U_V_Y 00_YV F V-0._0 M0P00TF R0 0K_J 00 FN_TH_ VFN FPT R POWER_LOE_P_00 MFIX MFIX N0 HEER_P FOX_H0E-LH FN_TH FT Test Point for FN (OT side) tpc0b_00 TP tpc0b_00 TP VFN FN_TH_ tpc0b_00 TP tpc0b_00 TP FN_PWM_ P Thermal & Fan MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

34 O O O O O N_O_.x N_O_.x O_.x O_.x O_.x O for WWN O for WLN O for Thermal Module H hole_tbcd crew Hole for Thermal Module H0 hole_tcbcd H hole_cdn H hole_tbcd H hole_tbcd H hole_tbcd luetooth P ME NUT & EMI MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

35 MF Power lock iagram daptor V 0 W TOUT TI TPRER witch Mode For ystem Power +VLW/ +VLW/ +VU/ RUN_ON RUN_ON N-hannel MOFET N-hannel MOFET +VRUN/0. +VRUN/. LW_ON VRE +VLW_LO ENTRIP VRE +EV ENTRIP PE POO LW_PWR Q attery harger witch Mode TOUT FitiPower FP witch Mode For R Power +_VU/ +_0V_PWR RUN_ON N-hannel MOFET LO Fitipower FP +_VRUN/0. +_VRUN/ +_V_PWR PE U_ON EN PE POO R_PWR RUN_ON LO MT +0_VRUN/0. Ich=. TOUT FitiPower FP witch Mode For ystem Power. +_0VRUN/ attery Pack P. Wh +_V_PWR EN PE POO RUN_PWR +_0V_PWR LO Fitipower FP VFX/. TOUT MXIM MXTJ+ FOR PU ore. VHORE/. IMVP_VR_ON HN# PE VRHOT# LKEN# PWR OVT_E# IMVP_LK_EN# ELY_VR_PWR P Power lock iagram MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of

36 MF IN&harger P.U_0V_k 0_XR tpc0b_00 tpc0b_00 PTP PTP _IN PR _J 0 INUNER ottom ide PTP PTP tpc0b_00 tpc0b_00 +EV V-_0 000.WR PN P+ -IN_P FOX_H0E-LH PR _J 0 P.U_0V_k 0_XR HRE_TRL PR RET VREF N_K_F 00 +EV ottom ide TT_PR# ENH# ENH# VREF P 0.0U_0V_M 00_XR P 0.U_0V_K 00_XR PR 0K_J 00 +EV PR 0K_J 00 PTP _IN tpc0t_0 HEN# _IN OVPET ET PR 0K_J 00 PR K_F 00 _IN_MO PR 0K_F 00 TOUT _IN_R RV# ET OO# OVPET RET ET VREF LERN HEN# VREF _IN_MO _IN_MO P and N connections must be make using Kelvin-sense connections 0 0 PU QRHR N P RV# ET N OO# OVPET RET ET VREF LERN ELL HEN# V PV TRV# T HIRV PH TT REN LORV PN RP RN _IN_R PV TRV# HIRV PH TT REN LORV T+_ T+ T+ PR 0.0_0.W_F P 0.U_V_M 00_XR P 0.U_V_M 00_XR P 0.U_0V_K_ P 00_XR H00H-0PT TOUT Q / PTP tpc0t_0 TOUT PR 00K_F 00 0 Q PQ FM00 T+ TT_I T_M LK_M TT_PR# Y_PR# PH RP and RN connections must be make using Kelvin-sense connections PTP tpc0t_0 T+ P 0P_0V_K 00_XR PL 0R-00MHZ_0 M00 T+_ FT Test Point for attery (OTTOM side) P 0U_V_M 0_XR tpc0b_00 PTP0 tpc0t_0 PTP tpc0t_0 PTP tpc0t_0 PTP tpc0t_0 PTP tpc0t_0 PTP tpc0b_00 PTP0. P 0.U_V_M 00_XR T+_ T_M LK_M TT_PR#_ Y_PR#_ T+_ TT_I T_M LK_M TT_PR#_ Y_PR#_ attery ONN. P 0U_V_M 0_XR T+ IN_E _OFF PR 00 OO# PQ N00. LERN PR 0K_J 00 VJ OP T+_ T_M LK_M TT_PR#_ Y_PR#_ P P_0V_J 00_NPO P P_0V_J 00_NPO P N_0P_0V_J 00_NPO P N_0P_0V_J 00_NPO P 0.U_0V_K 00_XR P0 0.U_V_M 00_XR PL 0R-00MHZ_0 PF M00 INFUE P 0.U_0V_K 00_XR PR 0K_J 00 PR K_F 00 PQ N00. RET PR PR PR0 PR 0K_F 0K_F 00K_F 0K_F PQ ON0L P U_.V_M 00_XR PR 0K_J 00 P 0.U_V_M 00_XR PQ ON0L P 0.U_V_M 00_XR 0 PR._F 00 P 0.U_0V_K 00_XR P 00_XR U_V_M_ PQ ON0L P00 0.U_V_M 00_XR P0 0U_V_M 0_XR PR._J 00 PL.UH_._0.0R PM0T-RMN P TVPT PR 00 PR0 00 0U_V_M 0_XR P PEVUT PR 0.0_0.W_F P 0.U_V_M 00_XR P 0.U_V_M 00_XR 0 P PEVUT P 0.U_V_M 00_XR PTH PTH PN TTERY ONN_P FOX_P0-E-H PR PR 0K_J 0K_J PR 00K_F 00 PR 00K_F 00 VJ IPT P 0P_0V_J 00_NPO VJ OP IPT POWERP PR N_ 00 P 0.U_.V_K 00_XR REN REN P U_0V_K 00_XR TOUT PR TLE N_0K_F 00 PR E_VPT IPT E_IPT PR 00 N_ IPT 0W P./.W PWRLIMIT /W P N_0K_F 00 IN&harger MF 0. ize ocument Number Rev ustom Wednesday, March, 00 ate: heet of

37 MF0 Y Power (+_V/+V) TOUT TOUT 00m PTP +VLW_LO tpc0t_0 TOUT Reserve for EM P N_0.U_V_M 00_XR P N_U_.V_K 00_XR +VLW PTP tpc0t_0 00m +EV PTP tpc0t_0 +VLW P 0U_V_M 0_XR PQ FM00 PL.U-00KHZ_._0.0R PM0T-RMN P 0.U_V_M 00_XR 0 Q / Q PR 00 +EV R0VRE P PR 0.U_0V_K_ 00_XR 00 R0VTR R0VRE R0VT R0RVH R0LL R0RVL TOUT +VLW_LO PR R0VT 00 R0RVH R0LL P.U_0V_K 00_XR P 0.U_V_M 00_XR R0VTR PQ FM00 PL PM0T-RMN.U-00KHZ_._0.0R P N_0.U_V_M 00_XR +VLW PTP tpc0t_0 R0VREF +VLW_LO +VLW LW_PWR R0TONEL R0KIPEL R0ENTRIP R0ENTRIP R0EN0, LW_ON LW_PWR LW_ON +VLW_LO PR 00 ENTRIP R0RVL +VLW R0VF R0ENTRIP LW_PWR R0EN0 R0VLK R0ENTRIP R0ENTRIP R0LL +VLW +0V_VO +V_LW R0VF P U_V_K 00_XR P 0.U_V_M 00_XR P N_P_0V_J 00_NPO P0 PR0.U_.V_K.K_F 00_XR 00 PU VRE VT 0 RVH LL RVL VIN VRE VT RVH 0 LL Q / P 0.U_V_M 00_XR 0 Q P 0U_V_M 0_XR P NU_.V_K 00_XR P 0.U_.V_K 00_XR P +.x.x. N_0U_.V_M P +.x.x. 0U_.V_M PR 00 PR PR 00K_F 00K_F PR.K_F 00 R0LL R0VF PR 0K_F 00 PR N_0K_F 00 P 0.U_.V_K N 00_XR PR 0K_J 00 +VLW VO R0VF VF R0ENTRIP ENTRIP R0KIPEL KIPEL R0VREF VREF R0TONEL TONEL LW_ON# PQ N00W PQ TPRER N00W THERML P PR0 00 RVL VO VF ENTRIP POO EN0 VLK P P 0.U_V_M TPT 00_XR VLKIN P P 0.U_V_M TPT 00_XR VLKIN R0LL P 0.U_V_M 00_XR PR 0.K_F 00 PR 0K_F 00 +V_LW PTP tpc0t_0 P MMPZ0FPT + P 0U_.V_M.x.x. PR PR 0K_J P 0.U_V_M 00_XR P0 P N_P_0V_J 0.U_.V_K 00_NPO 00_XR PR._J 00 P 0P_0V_K 00_XR PR._J 00 P 0P_0V_K 00_XR P Y Power (+_V/+V) MF 0. ize ocument Number Rev ate: Wednesday, March, 00 heet of