YOUN SUNG CHOI UNIVERSITY OF FLORIDA

Transcription

1 IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDE- SEMICONDUCTOR DEVICES: CHANNEL MOBILITY, GATE TUNNELING CURRENTS, THRESHOLD VOLTAGE, AND GATE STACK By YOUN SUNG CHOI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA

2 2008 Youn Sung Choi 2

3 To my parents in Korea and family, Luke and Jin-Hwa 3

4 ACKNOWLEDGMENTS First and foremost I would like to thank my advisor, Dr. Scott E. Thompson, for his constant encouragement and expert guidance over the past four years. I have learned many things, including how to solve critical problems from a simple model and logical thinking, from him. I also would like to convey my special thanks to my co-advisor, Dr. Toshikazu Nishida. His consistent advice and technical writing skill have been very valuable in the course of my research. I also would like to express my gratitude to my committee members (Dr. Arnost Neugroschel, Dr. Jing Guo, and Dr. Franky So) for their interest and suggestions on my research. My colleagues in our lab have contributed significantly to my Ph.D. research work through interactive discussions. I would like to thank Dr. Ji-song Lim for his priceless help to publish my first publication, which has been a booster for my research works. Dr. Toshinori Numata, a visiting scholar from Toshiba, also gave me a lot of insightful ideas and reviewed a couple of my publications. Hyunwoo Park, Uma Aghoram, Min Chu and Andrew Koehler have been with me during my Ph. D. study and given me valuable ideas. I also would like to thank previous group members, Dr. Sagar Suthram and Dr. Guangyu Son, and current members, Dr. Yongke Son, Tony Acosta, Ukjin Roh, Xiaodong Yang, Srivatsan Parthasarathy, Mehmet Baykan and others for their helps. I dedicate this dissertation to my parents and family. I especially thank my father, mother, and younger brother in Korea for their endless support and love, which have made me what I am now. I also owe my deepest thanks to my wife, Jin-Hwa Lee, who has stood by and encouraged me, and my son, Luke Jun-Young Choi, who has grown up healthily. 4

5 TABLE OF CONTENTS ACKNOWLEDGMENTS...4 LIST OF TABLES...7 LIST OF FIGURES...8 ABSTRACT...11 CHAPTER 1 INTRODUCTION...13 page Overview of Strained CMOS Technology...13 How to Apply Strain to MOSFETs...15 Brief Description of Study UNIAXIAL-STRESS-INDUCED CHANNEL MOBILITY ENHANCEMENT...21 Physics...21 Strain Enhanced Hole Mobility STRAIN EFFECTS ON GATE LEAKAGE CURRENTS OF GERMANIUM (Ge) MOS DEVICES...32 N-Type Metal-Oxide-Semiconductor Field Effect Transistors...32 Ge Conduction Band Edge Shift and Splitting...32 Theoretical Model...34 Experimental Set-Up and Results...36 Extraction of Conduction Band Deformation Potentials...40 Summary...42 P-Type Metal-Oxide-Semiconductor Field Effect Transistors...43 Experimental Set-Up...43 Stress Altered Hole Tunneling Currents of Ge and Si p-mosfets...44 Stress Altered Electron Tunneling Currents From Metal Gate...51 Summary IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE LEAKAGE CURRENTS IN P-TYPE MOS CAPACITORS...56 Introduction...56 Experimental Set-Up...56 Results and Discussions...57 Conclusions

6 5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC CONSTANT OF NITRIDED HF-SILICATE DIELECTRIC SILICON MOS CAPACITORS...62 Introduction...62 Experimental Procedures...62 Results and Discussions...63 Conclusions IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON THRESHOLD VOLTAGE SHIFTS IN P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS...69 Introduction...69 Threshold Voltage Shift Models...69 Results And Discussion...71 Conclusion RELIABILITY OF NITRIDED HAFNIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICAL STRESS: TIME DEPENDENT DIELECTRIC BREAKDOWN...77 Introduction...77 Experimental Setup...78 Experimental Results...79 Discussion...82 Conclusion SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK...88 Summary...88 Recommendations for Future work...89 LIST OF REFERENCES...91 BIOGRAPHICAL SKETCH

7 LIST OF TABLES Table page 3-1. Dilation (Ξ d ) and shear (Ξ u ) deformation potentials extracted from gate tunneling current of Ge MOS device under tensile stress along [100] and [110] Deformation potential constants used in this study [17] and ΔEC and ΔE g of Si and Ge, calculated at 300 MPa of uniaxial tension and compression along [110] direction Model-predicted, with m=1.3, contributions of band edge shifts, DOS change, Δµ and ΔΦ M terms. (ΔΦ M is estimated from [102]) Measured and estimated reliability issues of thick (> 7 nm) high k Si MOSFET as a function of uniaxial mechanical stress

8 LIST OF FIGURES Figure page 1-1. Process architecture for strained Si Uniaxial four point wafer bending jig: two pairs of cylindrical rods are used and a sample is inserted between the pairs Uniaxial wafer bending jig. The displacement (d) is defined as d=d i -d f Hole constant energy band surfaces for the top band obtained from 6 band k p calculations for common types of 1GPa stresses Summary of key valence band parameters for top and second band for bulk Si under 500MPa stress Conduction valley energy level splitting under 500MPa of longitudinal uniaxial tensile stress: bulk and MOSFET inversion layer (1MV/cm) Valence energy band splitting calculated using 3 different models versus inversion charge density for longitudinal compression and biaxial tension stress Calculated and experimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= σx+σy) Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along Λ or [111] direction Schematic band diagrams for direct electron tunneling from inversion layer in Ge MOS device The [100] tensile stress-altered gate tunneling current for Ge MOS device under different gate biases The [110] tensile stress-altered gate tunneling current of Ge MOS device under different gate biases The [110] tensile stress-altered electron gate tunneling current of Ge and Si devices at inversion charge of /cm 2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively[68] Schematic band diagrams for [110] tensile stress effects on electron gate tunneling in Si and Ge devices Change in slopes ( d[δ I G ( σ ) / I G (0)]/ dσ ) versus gate voltage with 95% confidence error bars for tensile stress along [100]

9 3-8. Change in slopes ( d[δ I G ( σ ) / I G (0)]/ dσ ) versus gate voltage with 95% confidence error bars for tensile stress along [110] Carrier separation measurement of p-mosfet and 4-point wafer bending. The gate tunneling current (I G ) can be separated into electrons (I G,electron )and holes (I G,hole ) tunneling from gate and substrate, respectively[75] Carrier separation measurement of a) Source/drain (I S/D ) and substrate tunneling current (I SUB ) as a function of gate voltage (V G ) for Ge p-mosfet. b) I S/D and I SUB as a function of V G for Si p-mosfet Relative change in I S/D of Si and Ge p-mosfet as a function of stress. Symbols and lines are measured data and modeling, respectively Schematic band diagram for the hole gate tunneling current in a p-mosfet on a (100) wafer Valence band edge splitting of Ge and Si under tensile stress along [110] Charge density versus applied stress for the top (E 1 ), bottom (E 2 ), and third subbands (E 3 ) at an inversion charge density of 3.5x10 13 /cm 2 for a) Ge and b) Si, respectively Relative change in I SUB of Ge p-mosfet as a function of stress at gate bias of - 2.8V The V FB shift under uniaxial stress Work-function shifts of TaN, bulk Al and bulk Cu as a function of stress[87]. Workfunctions of three different metal increase/decrease with compressive/tensile stress. Line is the linear fit of extracted data Relative changes in gate tunneling current of MOS capacitor with TaN gate as a function of stress. Symbols and lines are measured data and modeling, respectively Relative change of gate leakage currents in MOS devices before constant voltage stress (CVS) and after CVS as a function of applied mechanical stress along [110] direction Schematic band diagrams for direct and trap-assisted gate tunneling mechanisms. Key parameters for mechanical stress-altered electron gate tunneling currents before and after CVS are summarized in table Schematic of SiO 2 /(100) Si interface structure including P b0 and P b1 centers, showing mechanical stress-induced changes in dangling bond angles (Ө) and interface trap activation energy (Φ T )

10 5-1. The C-V characteristics at 1MHz of the MOS device with Pt and Al gate on nitrided Hf-silicate film. The inset shows current density-voltage (J-V) measurements of both devices Poole-Frenkel (ln(j/e) vs E 1/2 ) plot of Pt and Al gate on nitrided Hf-silicate film at 25 o C. Inset in figure shows a schematic band diagram for MOS capacitors with HfSiON dielectric and interlayer and metal gates (Pt and Al) under negative gate bias Changes in gate leakage current of Si MOS capacitors with HfSiON dielectric as a function of applied stress Changes in dielectric constant of HfSiON, HfSiO x and HfO 2, measured from C-V and PF slope change Plots of uniaxial stressed V th shifts of p-mosfets with different gate stacks (poly Si/SiO 2 vs TiN/HfO 2 ) and different channels (Ge vs Si). Symbols and lines are experimental data and calculated models, respectively Plots of V th shifts of Ge and Si p-mosfets with the mobility correction as a function of stress. Symbols and lines are experimental data and calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si p- MOSFETs with TiN/HfO 2 gate stack as a function of stress Current-time curve for 7 nm HfSiON dielectric Si MOS device during CVS The t BD distributions and area scaled t BD distributions for different size samples under V G = -5.2 V Uniaxial tensile stress effect on t BD distributions and area scaled t BD distributions under V G = -5.2 V Uniaxial compressive stress effect on t BD distributions and area scaled t BD distributions under V G = -7 V The Q BD distributions for samples with two different HfSiON dielectrics thickness (7 and 8 nm) under tensile mechanical stress Interface trap generation under mechanical stress Schematic band diagram for key strain-related parameters for reliability issues

11 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy IMPACT OF MECHANICAL STRESS ON SILICON AND GERMANIUM METAL-OXIDE- SEMICONDUCTOR DEVICES: CHANNEL MOBILITY, GATE TUNNELING CURRENTS, THRESHOLD VOLTAGE, AND GATE STACK Chair: Scott E. Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering By Youn Sung Choi December 2008 Our study explores the impact of uniaxial mechanical stress on metal-oxide-semiconductor devices in terms of channel mobility, gate direct tunneling current, trap-assisted gate tunneling current, threshold voltage, high-k gate dielectric, and metal gate using four point wafer bending setup. Beyond 90 nm technology node, strained Si technology has been a mainstream in VLSI manufacturing technology. Therefore, it is important to properly understand strain effects on channel mobility and also other electrical parameters, such as gate leakage, gate stack, and reliability of MOS devices. Process-induced uniaxial stress has been compared with substrate-induced biaxial tensile stress and its advantages on Si p-mosfets have been pointed out. The net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. This results in larger hole mobility enhancement under uniaxial compressive stress. Impact of uniaxial mechanical stress on gate direct tunneling current in Si and Ge MOS devices are investigated. Because of the different conduction edges of Si and Ge, opposing uniaxial mechanical stress dependence has been observed in gate direct tunneling currents of Si and Ge n-mosfets. Based on gate bias-dependent gate direct tunneling current under 11

12 mechanical stress, Ge conduction band deformation potentials have been extracted and agree well with theoretical calculations. We also measure gate direct tunneling current of Si and Ge p- MOSFETs under mechanical stress using carrier separation technique in order to investigate strain effects on subband structure in p-type inversion layer of Si and Ge. Due to larger straininduced valence band edge splitting in Ge, the relative change in gate tunneling current in Ge is 3 times larger than that in Si under uniaxial tensile stress. Strain effects on trap-assisted gate tunneling mechanism, including trap-assisted tunneling and Poole-Frenkel emission, are also investigated from both SiO 2 and nitrided hafnium silicate (HfSiON) gate dielectric Si MOS capacitors. A decrease in electron and/or hole trap activation energy results in an increase in trap-assisted gate tunneling current with both [110] tensile and compressive stresses. The dielectric constant of HfSiON also increases with mechanical stress, resulting from strain-induced N p band splitting, which reduces the band gap of HfSiON. 12

13 CHAPTER 1 INTRODUCTION 1.1 Overview of Strained CMOS Technology Strain effects on semiconductors such as silicon (Si) and germanium (Ge) have been extensively studied to maintain historical performance improvement. Bardeen and Shockley introduced a deformation potential theory, explaining that the electron- or hole-phonon interaction causes a static displacement of the atoms, thus resulting in the conduction or valence band energy shifts[1]. Herring et al. and Pikus et al. quantified the conduction and valence band energy shift as a function of strain, respectively, based on deformation potential constants, which are important parameters in strained CMOS technology[2, 3]. The origin of strained-si to improve CMOS devices can be traced to thin Si layer grown on relaxed SiGe substrates in 1980s[4, 5]. The thin Si layer takes the larger lattice constant of the SiGe and creates biaxial tensile stress. Wafer-based substrate strain was experimentally and theoretically studied by a large number of researchers for two decades[6]. In the 1990s, two other strained-si activities started based on process-induced strain. First, high-stress capping layers deposited on MOSFETs were investigated as a technique to introduce stress into a channel.[7] Second, Gannavaram et al [8] proposed SiGe in the source and drain area for higher boron activation and reduced external resistance. It was this embedded SiGe literature that prompted Intel [9] to evaluate the technology, which resulted in larger than expected device performance enhancement, which, after considerable internal debate, was later attributed to uniaxial compressive channel stress[10]. Still, neither biaxial nor uniaxial stress was immediately adopted in CMOS logic technologies for several reasons. Biaxial stress suffers from defects and performance loss at high vertical electric fields[11]. Process-induced stress requires different stress types (tensile and compressive for n- and p-channel, respectively) to simultaneously 13

14 improve both n- and p-channel devices. However, inside Intel and in the industry, strain was becoming recognized as offering the best potential to enhance performance in sub-100-nm process technologies (significantly larger performance gain than high-κ gates, fully depleted silicon-on-insulator (SOI), or multi-gate devices). The only debate was on the best path to take (biaxial substrate versus uniaxial-process-induced stress)[12]. Careful analysis of the 1990 s biaxial and uniaxial strained-si experimental data suggested that the industry adopt process-induced uniaxial strain. The key observations are as follows. First, uniaxial (versus biaxial) stress provides significantly larger hole mobility enhancement at both low strain and high vertical electric field due to differences in the warping of the valence band under strain[13]. Large mobility enhancement at low strain is important since yield loss via dislocations occurs at high strain. Second, uniaxial (as compared to biaxial) stress enhanced mobility provides larger drive current improvement for nanoscale short-channel devices. This results since the uniaxial stress-enhanced electron and hole mobility arises mostly from reduced conductivity effective mass (versus reduced scattering for biaxial stress), since uniaxial shear stress provides significant valence and some conduction band warping. Lastly, process-induced uniaxial stress causes approximately five times smaller n-channel threshold voltage shift. Since any threshold voltage shift needs to be retargeted by adjusting channel doping (for industry standard poly-si gate devices on bulk or partially depleted SOI), the larger threshold voltage shift for wafer substrate-induced biaxial tensile stress causes approximately half of the stressenhanced electron mobility to be lost[14]. Rarely is the stress-induced threshold voltage shift taken into account in the biaxial tensile-stress mobility data. On the other hand, Ge and strained Ge are currently being investigated as a potential replacement to strained Si[15, 16]. To characterize strained Ge, accurate deformation potential 14

15 constants (Ξ d and Ξ u ) are required to model the strain induced energy level shifts and splitting. Recently, strain altered gate leakage current has been proposed as an accurate method to extract conduction band deformation potential constants and has been applied to Si with the results matching theoretical expectations[17, 18]. For Si p-mosfets, uniaxial tensile stress increases while compressive stress decreases the gate tunneling current[19, 20]. An opposite dependence exists in Si n-mosfets[18, 21]. These results can be understood from the strain-altered out-ofplane effective mass, energy splitting, and carrier repopulation in Si inversion layer[20], which can be used to understand impact of strain on gate tunneling currents of Ge n- & p-mosfets. Since Ge MOSFETs are usually incorporated with high k dielectric and metal gate, strain effects on metal/high-k dielectric gate stack, such as strain altered metal gate work function and high-k dielectric constant, can change the electrical parameters, such as the threshold voltage, gate leakage current, gate capacitance and so on. Unlike SiO 2 technology, high-k dielectric technology suffers from trap-related problems (i.e. bulk and interface traps) which may result in a degradation of the benefit from strain technology. Even in SiO 2 devices, especially in nonvolatile memory (NVM) application, stressinduced leakage current (SILC) has become a major concern for the reliability of the tunneling dielectric, resulting from the generated interface trap due to the repeated high-field stress (Fowler-Nordheim stress)[22, 23]. Therefore, it is important to understand impact of mechanical stress on trap-assisted gate leakage and dielectric breakdown. 1.2 How to Apply Strain to MOSFETs This section describes two techniques used in commercial 90 and 65 nm logic technologies to introduce uniaxial stress into the Si channel. The techniques in production include high stress 15

16 tensile and compressive SiN capping layers and selective epitaxial SiGe deposited in recessed/raised source and drains. The cost to implement process stressors is low at less than approximately 2-3% due to the comparatively few new process steps. Several process flows exist to introduce the epitaxial SiGe into a MOSFET[24-26]. The first consists of the steps shown in Fig. 1-1(a). The source/drains are etched creating a silicon recess. Next, SiGe (for p-channel) or SiC for n-channel is epitaxially grown in the source and drain. First generation embedded SiGe used ~17% Ge to create ~500MPa of channel stress. Future generations bring the SiGe closer to the channel and will likely increase the Ge concentration[25, 27]. Locating the SiGe closer to the channel will require reduced midsection thermal cycles to prevent any boron or Ge out-diffusion from the SiGe into the channel. To date a maximum of ~900MPa of stress has been created with embedded SiGe and impressive current improvements from 60-90% have been demonstrated on short devices (~35 nm)[25, 27]. Instead of embedded SiGe, dual stress liners (tensile and compressive capping layers) [28] are also being widely adopted[29, 30]. The advantages of a dual stress liner flow over epitaxial SiGe are reduced process complexity and integration issues. Recent progress in increasing stress of SiN films to ~3.0GPa for compressive and ~2.0GPa tensile [31] increases the attractiveness of this option. The capping films are introduced either as a sacrificial layer before source and drain anneal [28, 31, 32] or as a permanent layer post salicide (Fig. 1-1(b)). With 2-3GPa stress in the SiN, comparable performance to the first generation SiGe has been demonstrated. The process flow consists of a uniform deposition of a high tensile SiN liner post silicidation over the entire wafer followed by patterning and etching the film off p-channel transistors. Generally a thin etch stop layer is used under the liner to prevent any damage to the silicide. With highly selective 16

17 etches, the etch stop layer can be < 50A which only slightly degrades the stress transfer into the channel. Next, a highly compressive SiN layer is deposited and this film is patterned and etched from n-channel regions. Figure 1-1. Process architecture for strained Si (a) p-channel MOSFET process flow for the representative stacked gate transistor and TEM cross sectional view (source: Chipworks) and (b) dual stress liner with tensile and compressive silicon nitride capping layers. In this work, instead of process-induced stress described above, four point wafer bending technique has been used to apply strain to MOS devices. Figure 1-2 and 1-3 show the fixture to simulate uniaxially strained MOSFETs as shown in figure

18 Figure 1-2. Uniaxial four point wafer bending jig: two pairs of cylindrical rods are used and a sample is inserted between the pairs. Figure 1-3. Uniaxial wafer bending jig. The displacement (d) is defined as d=d i -d f. (a) an unstressed sample (b) a stressed sample. 18

19 Such a bending structure has been well studied and a relation between the applied force and stress under uniform stress is given by [33] t d σ = Y ε = Y (1-1) L 2a 2a 2 3 Here, σ and ε are the stress and strain values at the center of the sample respectively, Y is Young s modulus of Si along the stress direction, L D a =, and the deflection d is the vertical 2 displacement between the upper and lower plates of the uniaxial jig when we apply stress. In Fig. 1.3, d is defined as d = d i - d f, and actually measured by the change in micrometer graduations. The stress calibration of this setup has been done with both strain gauge and optical curvature measurements. 1.3 Brief Description of Study The main purpose of our study is to understand the strain effects on Si and Ge MOSFET operations: channel mobility, gate tunneling currents (direct and trap-assisted tunneling mechanisms), threshold voltage, high k dielectric constant, and reliability related to dielectric breakdown. The brief explanation of strain-induced mobility enhancement of Si MOSFETs is given and the physics behind some strained-si experimental data is explored. The strain effects on direct gate tunneling currents of Si and Ge MOSFETs are compared and explained. Based on experimental observations, qualitative analyses are made for both n- and p- MOSFETs. Next, deformation potential constants of Ge conduction band edge are extracted from the measured gate tunneling current under mechanical stress. 19

20 The impact of mechanical stress on gate leakage current based on trap-assisted conduction mechanism for Si MOS capacitors is discussed using constant voltage stressing and compared with strain-altered direct tunneling current. Strain induced changes in gate leakage current and dielectric constant of nitirided Hfsilicate dielectric (HfSiON) Si MOS capacitors are explored with qualitative explanations. Strain-induced threshold voltage shift models of different channel materials (Si and Ge) and gate stacks (Poly Si/SiO 2 and TiN/HfO 2 ) are discussed with theoretical modeling. Each component of model is analyzed thoroughly in conjunction with its underlying physical mechanism. Impact of mechanical stress on time dependent dielectric breakdown of HfSiON is also investigated using controlled external applied mechanical stress and its mechanism is experimentally clarified. 20

21 CHAPTER 2 UNIAXIAL-STRESS-INDUCED CHANNEL MOBILITY ENHANCEMENT 2.1 Physics When deciding on a strained-si process flow, it is first necessary to comprehend the potential magnitude for electron versus hole mobility enhancement and whether the mobility enhancement results from reduced conductivity effective mass or scattering. Since the valenceband dispersion relationship for semiconductors depends on nearest neighbor atomic spacing, certain stress (in particular shear stress) warps the valence bands (although less so for conduction band but some warping for shear stress)[34]. The warping of the valence band provides dramatic changes to the constant-energy surfaces in k space and can lead to large hole mobility enhancement via reduced conductivity mass in the channel direction. Mobility enhancement via reduced mass (as opposed to reduced scattering) is a key in nanoscale MOSFETs and often not appreciated. Only mobility enhancement from reduced mass (unlike reduced scattering) is maintained at the very short nm channel lengths (35-nm gate length) devices currently in production[35, 36]. A strained-si flow, which is scalable for multiple technology nodes, thus, needs to focus on reducing the hole conductivity mass with the goal of improving the n/p ratio from 2 to 1. Therefore, in this section, we will focus on strain-enhanced hole mobility from reduced conductivity mass. As a starting point, it is helpful to visualize the effect of strain on the valence-band constant-energy surfaces in k space for bulk Si. Fig. 2-1 shows the surfaces obtained using six band k p and band parameters in [37]. The strain-altered surfaces for the top two bands are shown at 1 GPa for the common stresses of interest: longitudinal compression on (001)[24, 25, 38, 39] and (110) hybrid wafer orientation [39] and biaxial tensile stress. [40] Note from the constant-energy surfaces in Fig. 2-1, the heavy and light hole bands lose their meaning and we label the bands (first, second, etc.) in this work. Some important differences in the band 21

22 structure under the various stresses at 500 MPa are summarized in Fig. 2-2 for the in-plane and out-of-plane conductivity effective masses and density of states at the band edge. We will refer to Fig. 2-2 in the next section during analysis of experimental data. Before covering strain-altered hole mobility calculations, we will briefly cover a qualitative model for strain-enhanced electron mobility since the concepts are similar for electrons and holes. The important concepts to understand are strain-induced energy-level splitting, inversion-layer quantum confinement energy-level shifts, average mass change due to repopulation and band warping, two-dimensional (2-D) density of states, and interband scattering changes due to band splitting. All of these will be discussed in the following sections. A simple qualitative model is now presented to gain insight and to understand the more complex mathematics used elsewhere [11] and later in this work. The electron mobility in bulk strained-si along <110> direction is determined by occupation and scattering in the Δ 2 and Δ 4 valleys and can be expressed as n 2 n Δ Δ4 μeff = q τδ2 + τ * Δ4 /( n * Δ2 + nδ4) mt ml (2-1) where q, n, τ, and m are the electron charge, concentration, relaxation time, and conductivity mass in the MOSFET channel direction, respectively. Strain improves the mobility by increasing the electron concentration in the Δ 2 valley. The repopulation improves the average in-plane conductivity mass (unstressed: m t = 0.19m 0 versus m l = 0.98m 0 ) and some further improvement is possible for stresses that warp the conduction valleys and lower m t [34]. Reduced intervalley scattering by the strain-induced splitting between Δ 2 and Δ 4 plays some role (enhances long channel mobility) when the splitting becomes comparable or larger than the optical phonon energy. In addition to a low in-plane mass, a high out-of-plane mass for the Δ 2 valley electron is 22

23 equally important since carrier motion perpendicular to the SiO 2 interface (taken as the z- direction in this paper) is quantized. This quantization in addition to strain alters the position of the energy levels. The quantization leads to bands becoming subbands since only discrete wave vectors k z are allowed. Including quantization, the total inversion-layer electron energy is given by discrete values of energy (E n ) added to the electron energy in the x- and y-directions (in the plane of the MOSFET)[41]. Figure 2-1. Hole constant energy band surfaces for the top band obtained from 6 band k p calculations for common types of 1GPa stresses (a) unstressed, (b) biaxial tension, (c) longitudinal compression on (001) wafer, (d) longitudinal compression on (110) wafer. (Note significant differences in stress induced band warping altering the effective mass). 23

24 2 hk k y Ε = Εn + + (2-2) 2m 2m 2 h x x y Each step in energy is called a subband with E n the energy of the bottom of the subband. As an example, self-consistent solution of Schrödinger and Poisson equation for 500 MPa of uniaxial tensile stress and an inversion-layer vertical field of 1 MV/cm gives the energy levels, as shown in Fig Since the subband separation is greater than kt, nearly all the electrons in most cases occupy the bottom two subbands [ground state n = 0 typically called E o (from Δ 2 ) and E o_ (from Δ 4 )]. The ground state energy is significantly lower for the Δ 2 valleys because of the higher quantization mass (Δ 2 : m z = 0.98m 0 versus Δ 4 : m z = 0.19m 0 ) which leads to increased splitting between the bottom two subbands and confinement and strain splitting being additive (for the common biaxial and uniaxial tensile stress). Note, the strong confinement in an MOSFET shifts the energy levels more than the moderate 500-MPa stress typically used in present-day production logic technologies. Thus, a high out-of-plane mass in the bottom subband (top subband for holes) is an important requirement for the strain altered band structure. Lastly, in addition to a low in-plane and high out-of-plane effective mass, a high in-plane mass perpendicular to the channel direction is also important. The density of states per unit area for the quantized system is 2/(2π ) 2 ( m m / m ) dk x y o x dk y, which results in the density-of-states 2D mass approximated by m = DOS m m x y. Though strain does not significantly alter the electron subband density of states, as discussed next, a high maintaining a hole concentration in the top subband. D m 2 DOS will be shown to be important for 24

25 Figure 2-2. Summary of key valence band parameters for top and second band for bulk Si under 500MPa stress. The conductivity and density of states effective mass is listed at Gamma point. Uniaxial compression is longitudinal along <110> channel direction. (Note significant differences for in-plane, out-of-plane and density of states masses). Similar to strained enhanced electron mobility, hole mobility in an inversion layer can qualitatively be described as resulting from occupation and scattering in the top two bands ptop p 2nd μ eff = q τ top + τ 2 /( 2 ) * nd p * top + p nd. (2-3) mtop,110 m 2nd,110 However, hole transport is more complicated since strain significantly warps the valence band (as seen in Fig. 2-1) altering both the in and out-of-plane mass and D m 2 DOS. Further, the mass changes with stress and is not constant in k space. As follows from the previous discussion on strain enhanced electron transport, an advantageous strain for holes needs to warp the valence band to create both a low in-plane and high out-of-plane mass and if possible a large mass in the plane of the MOSFET perpendicular to the channel direction (creates a large D m 2 DOS ). Band calculations and measurements to be discussed next show uniaxial stress warps the valence band 25

26 creating most of these features. The strain altered band structure is calculated using 6 band k p, including quantum confinement via a self-consistent solution of Schrödinger and Poisson equation[41, 42]. The mobility is calculated by a linearization of the Boltzman transport equation. The numerics confirm that the simple qualitative model captures much of the essential physics for understanding the physical mechanisms for mobility enhancement. Figure 2-3. Conduction valley energy level splitting under 500MPa of longitudinal uniaxial tensile stress: bulk and MOSFET inversion layer (1MV/cm). Note, energy level splitting from inversion layer confinement is larger than strained. 2.2 Strain Enhanced Hole Mobility In a MOSFET, the 2-D surface confinement in the inversion layer also shifts the valence bands and the conduction valleys[11, 43]. Whether the confinement-induced shift adds to or reduces (cancels) the strain-induced splitting simply depends on the magnitude of the out-ofplane masses (valence-band splitting is more complicated but this simple model captures the essential physics). Bands or valleys with a light out of plane mass will shift more in energy 26

27 relative to bands with a heavy mass (similar to the increasing ground state energy of a quantum well as the particle mass decreases). Hence, when the top most occupied band (or valley) has a lower out-of plane mass compared to the next occupied band, the splitting is reduced or lost with surface confinement. Fig. 2-4 pictorially shows the valence-band energy-level shift with confinement for both uniaxial and biaxial stress. E top represents the top band with large out-ofplane mass for uniaxial stress and small for biaxial stress (relative to the second band with masses given in Fig. 2-2). Hence, the top band will have a small shift in energy due to confinement for uniaxial stress but large shift for biaxial stress. E second represents the second band. As seen in Fig. 2-4, the stress-induced band splitting (E top E bottom ) increases for uniaxial stress but decreases for biaxial tensile stress. Thus, although strain favors occupation of the top band for both types of stresses, confinement favors occupation of the top band for uniaxial compressive stress and the second band for biaxial tensile stress. The net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. The competing effects of strain and surface confinement on the band splitting is the reason for the loss in mobility enhancement in biaxially strained-silicon p-mosfets at high electric fields. The undesirable light out of-plane mass created by biaxial tensile stress occurs in other material systems, such as Ge and III-V materials, and presents a fundamental problem in using this type of strain in inversion layer MOSFETs (dominant device type due to superior scaling properties). To date, unlike biaxial stress [6], limited data exist for the maximum mobility possible for uniaxial stress. We used a set of scattering parameters that fit the experimental data for hole mobility enhancement under biaxial tensile stress[11]. The calculations include acoustic and optical phonon and surface roughness scattering. This set of scattering parameters shows that the 27

28 dominant mechanism responsible for biaxial tensile-stress mobility enhancement (at large stress) is reduced optical phonon scattering. Acoustic phonon scattering is only slightly altered due to the changes in the density of states. Surface roughness scattering is slightly changed by stress but uncertainty exists in the literature[11, 44, 45] and more work is needed especially for the (110) substrate. The calculations for biaxial stress are consistent with the previous work [11], although in this work, Schrödinger s and Poisson s equations are solved self-consistently. The model fit to the biaxial tensile-stress experimental data is shown in Fig Figure 2-4. Valence energy band splitting calculated using 3 different models versus inversion charge density for longitudinal compression and biaxial tension stress. Note all models show the net band splitting from strain and confinement is additive for uniaxial compressive stress but subtractive for biaxial tensile stress. Using the same scattering parameters, mobility enhancement for uniaxial stress on (001) and (110) wafers is calculated, as shown in Fig. 2-5, and compared to uniaxial stress data from from three references[6, 24, 46]. The mobility calculations use the full sixband subband structure 28

29 and Kubo Greenwood linearization of the Boltzmann equation[16]. Where data exist (0 to 600 MPa for uniaxial stress), the model shows good agreement. The maximum predicted Si inversion-layer hole mobility enhancement is estimated to be 4 times higher for uniaxial stress on (100) wafer and 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a (110) wafer. The larger maximum mobility enhancement on a (001) wafer results from the high density of states in the top band, as discussed previously but scattering differences also play a role. Scattering differences for various substrate orientations and stresses should be expected as captured in analytical scattering expressions. First for acoustic phonon in the two dimensional inversion layer, the scattering time τ ac is expressed as [11, 44, 45, 47] τ 2 2D 1 Dac bmnmdoskbt 2D = ( m 3 2 DOS ac h ρul ) (2-4) where D ac = 3. 1eV [48] is the acoustic deformation potential constant of the valence band, D m 2 DOS is the density-of-state effective mass, ρ is the density, and u l is the longitudinal sound velocity. w m n The constant b dzψ v ( z) ψ v ( z) mn = 0 is the form factor which defines the transition from k k initial state m to final state n, and 2 represents the effective well width for the m-th subband. b mm Since the acoustic phonon energy is very small compared to the subband splitting, the acoustic phonon scattering mainly occurs via intraband scattering. Thus, stress-induced band splitting only weakly affects the acoustic phonon scattering time[13, 49]. As seen from Eq. 2-4, an increased density-of-states will decrease the acoustic phonon scattering time which is proportional to D m 2 DOS. For uniaxial stress on a (100) wafer with a high density of states in the top 29

30 band, this slight negative effect on mobility (at least for uniaxial stress on (001) wafer) is offset by the high hole density in the top band having a light conductivity mass in the channel direction. Also, a large out-of-plane mass increases the acoustic phonon scattering time (decreases scattering rate) since it decreases the effective well width (important for the high initial mobility on (110) wafer). Second, the optical phonon scattering time τ op is [13, 45, 47, 49] 1 τ op = m 2D DOS b mn 2ρω h 0 D 2 op 2 [ N q 1 f ( ε + k BΘ ΔE) 1 f ( ε ) + ( N + 1) p 1 f ( ε k BΘ ΔE) 1 f ( ε ) ] (2-5) where 8 Δ E is the band splitting energy, D op = ev / cm [50] is the optical deformation potential constant of the valence band, f ( ε ) is Fermi-Dirac distribution function at energy ε, Θ = 735K is the Debye temperature and k Θ = hω B 63meV and [ ( ) ] 1 N = exp hω / k T 1 = [ exp( Θ / T ) ] 1 q 0 B 1 0 = is the optical phonon energy[47], is the number of phonons from Bose-Einstein statistics. Hole intervalley scattering is not significantly reduced for stress < 1GPa since the band splitting is less than the optical phonon energy (60meV). Band splitting greater than 60meV (stress > 1GPa) is necessary to appreciably suppress intervalley phonon scattering. Also, the correlation between the topmost two subbands, b mn under uniaxial stress is smaller due to the higher band splitting (strain and confinement being additive) and, therefore, the scattering rate is less than that for biaxially stressed devices. Furthermore with the high out-of-plane mass causing larger subband splitting, the interband optical phonon scattering rate is less on (110) vs. (001) devices. Third, the surface roughness scattering relaxation time τ sr [11, 45] can be expressed as 1 τ sr = q 2 E 2 eff m 2πh 2D DOS 3 2π 0 S ( q) ( 1 cos( θ )) dθ (2-6) 30

31 where E is the transverse effective electric field in the inversion layer and S( q) eff = 2 πl Δ ( 1+ q L / 2) 3 is the power spectrum of the roughness at the interface. L is the correlation length ( L = 2. 6nm ) and is the average step height ( Δ = 0.4nm ). Differences in τ sr for various stresses and substrates result from changes in the density-of-states and location of the inversion layer charge from the SiO 2 interface. There is also a fair amount of uncertainly in surface roughness scattering particularly on a (110) wafer since the commonly used universal mobility vs. effective oxide field E eff applies only to the (100) substrate[51, 52]. However, one can conclude since the effective well width depends heavily on the out-of-plane effective mass for each subband, the top subband for a (110) devices having a very large out-of-plane effective mass (see Fig. 2-2), will lead to carriers significantly closer to the interface and greater surface roughness scattering. Figure 2-5. Calculated and experimental data for longitudinal compressive and biaxial tensile stress enhanced mobility vs. stress (Biaxial stress= σx+σy). Note, the maximum predicted Si inversion layer hole mobility enhancement is estimated to be ~4 times higher for uniaxial stress on (100) wafer and ~2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a (110) wafer. 31

32 CHAPTER 3 STRAIN EFFECTS ON GATE LEAKAGE CURRENTS OF GERMANIUM (Ge) MOS DEVICES 3.1 N-Type Metal-Oxide-Semiconductor Field Effect Transistors Ge Conduction Band Edge Shift and Splitting Strain-induced energy shift and splitting alters the gate tunneling current. The Ge conduction band minima are located at the equivalent gamma (L) points[53]. Fig. 3-1 shows the conduction band constant energy ellipsoids around the L point. Since the centers of the diagonally opposite half ellipsoids are one wave vector apart, the 8 half ellipsoids can be combined into four equivalent full ellipsoids( [ 111],[111],[111],[111] ).[54] Due to the major axis along the Λ or [111] direction, uniaxial stress along [100] shifts but does not split the 4 ellipsoids, while splitting occurs for stress along [110], as shown in Fig. 3-2(b) and (c)[55]. Fig. 3-2(a) shows a schematic drawing of the direct tunneling process from the Λ sub-bands (E Λ ) in the inversion layer for uniaxial tensile stress. The strain-induced shift of the conduction band edge is given by [2, 56] where Ξ and d ΔE i C ( σ ) = Ξ ( Tr( ε )) + Ξ ( k ε k) (3-1) d ij Ξ u are the dilation and shear deformation potential constants of the conduction band, respectively, and i denotes the various valleys. Tr(ε ij ) is the trace of the strain tensor u ij ( ε ij )[57, 58] and k andσ are a unit vector in reciprocal space and applied stress, respectively. In Hydro E Fig. 3-2(b), stress along [100] causes a hydrostatic conduction band edge shift ( Δ ) resulting in an altered HfO 2 /Ge conduction band offset. The hydrostatic strain-induced conduction band edge shift can be expressed in terms of the deformation potentials [53] and is given by 32

33 where Hydro Hydro 1 Δ E ( σ ) = Ξ Tr( ε ij ) = ( Ξ d + Ξ u ) Tr( ε ij ) (3-2) 3 Hydro Ξ is the hydrostatic deformation potential constant. Unlike stress along [100], stress along [110] leads to band splitting between the (110) plane and ( 110) plane ellipsoids. The band splitting of each conduction band edge is given by [55] 1 E S (3-3) 6 Shear Δ Λ(110) ( σ ) = + 44Ξ uσ < 110> 1 E ( ) σ (3-4) 6 Shear Δ σ = S Ξ Λ(110) 44 u < 110> where σ <110> is the uniaxial stress along [110] direction (positive for tensile stress) and S 44 is the elastic compliance constant. A schematic drawing of the [110] stress effect on E Λ is shown in Fig. 3-2(c). Figure 3-1. Conduction-band constant energy ellipsoids are centered at the L point, and the major axis of eight half ellipsoids are along Λ or [111] direction. Out-of-plane effective mass and E eff are defined along [001] direction.[54, 59] Note half of ellipsoids belong to (110) plane while the rest of ellipsoids belong to ( 110) plane. 33

34 Figure 3-2. Schematic band diagrams for direct electron tunneling from inversion layer in Ge MOS device. (a) Conduction band offset between HfO 2 and Ge is from reference.[59] (b) Stress along [100] raises Λ energy level resulting from hydrostatic strain-induced energy level shift ( E Hydro ). (c) Stress along [110] causes shear strain-induced energy Shear level splitting ( Δ ) between (110) plane Λ valley [ Λ (110) ] and Λ (110). Λ (110) E Λ energy level is raised while Λ(110) energy level is lowered. Note E Hydro is additive Shear for Δ. E Λ(110) Theoretical Model From the change in the stress altered tunneling current, the Ge deformation potential can be extracted[18]. The electron direct tunneling current density (I G ) can be expressed in terms of the electron charge density ( n i ) and lifetime ( τ i ) of each energy sub-band in the quantization layer, which are functions of stress, I G ni ( σ ) ( σ ) = q (3-5) τ ( σ ) i i 34

35 where the subscript i denotes each sub-band belonging to the Λ valley of Ge. Above the threshold voltage, most electrons occupy each ground state for the Λ(110) and Λ 110) valleys. The relative change of gate tunneling current due to the applied stress can be expressed as [18, 60] ( ) ( ) Δ ( ) Δτ σ ΔI σ nλ(110) σ Λ(110) Δτ Λ(110) ( σ ) G A(0) B(0) C(0) (3-6) I (0) n (0) τ (0) τ (0) G Λ(110) Λ(110) Λ(110) ( where A (0) = B (0) = C (0) = n n n Λ(110) Λ(110) Λ(110) 1+ τ (0) / n n (0) / n (0) / n Λ(110) Λ(110) Λ(110) Λ(110) n Λ(110) Λ(110) (0) / τ (0) + τ (0) / n (0) + τ (0) / n (0) + τ Λ(110) Λ(110) Λ(110) Λ(110) Λ(110) Λ(110) (0) (0) / τ (0) (0) / τ (0) (0) / τ Λ(110) Λ(110) Λ(110) (0) (0) (0) The charge density of electrons in the sub-bands is calculated from the self-consistent solution of the Schrödinger and Poisson equations[61]. The effective mass approximation is used for Ge[54, 62]. For a (100) surface oriented Ge device, the out-of-plane effective mass ( m ) can be defined as 3m lmt /(2ml + mt ), where ml and m t are the longitudinal and transverse effective masses of the Λ valley, respectively ( m l = 1.64m0 and m t = 0.08m0 )[54]. Once the basic Hamiltonian has been identified, the electron charge density is calculated by summing the contributions of each sub-band in the Λ valley. The electron charge density of each sub-band can be described by [63] * n n i kt = ( πh 2 ) gm * d EF E ln(1 + exp( kt i )) (3-7) 35

36 where k is the Boltzmann constant, T is room temperature, 300K, E F is the Fermi energy, * m d is * the density of state electron effective mass in the Λ valley ( m d =0.3 m 0 ) [59], and E i and g are the energy level of the i th sub-band and the degeneracy of the Λ valley, respectively. Based on the finite difference method [61], the self consistent solution provides the charge density and the corresponding sub-band energy levels. The tunneling lifetime of the electron in each sub-band is approximated by [64] 1 T ( Ei ) = τ * i 2m /[ E E ( x)] dx n i C (3-8) where E C (x) is the edge of the conduction band of Ge and T(E i ) is the transmission probability calculated with a modified WKB approximation[63, 64]. An E(k) dispersion proposed by Franz, HfO2 which is consistent with two bands separated by an energy gap ( E =5.8eV), is used for the E- k dependence of HfO 2 [65, 66] and an oxide effective mass, g m OX =0.18 m 0 is used for this calculation[59]. The validity of the WKB approximation for high-k dielectrics has been shown elsewhere[62] Experimental Set-Up and Results Four-point bending is used to apply uniaxial stress along the [100] and [110] directions on (100) surface oriented Ge MOS samples.[13] The Ge MOS devices consist of TiN metal gate on top of 3.0 nm HfO 2 gate dielectric on p-well substrate. Large area 10-4 cm 2 Ge MOS devices are used to eliminate the fringe leakage components. The electron gate tunneling current from the Ge substrate to gate is measured under inversion with positive gate bias and substrate grounded using a Keithley 4200 DC characterization system. 36

37 Fig. 3-3 shows the [100] stress-altered electron gate tunneling current for different gate biases. The tunneling currents increase with applied tensile stress. Unlike Si, stress along [100] does not result in any change in the average conductivity effective mass via electron Hydro repopulation the inset shows the tunneling barrier height reduced by Δ E. Fig. 3-4 plots the change in the electron gate tunneling current for mechanical stress along [110]. The change in the tunneling current for stress along [110] is slightly smaller than for stress along [100]. It is instructive to compare [110] tensile stress altered tunneling currents for (100) surface oriented Si and Ge n-mos devices which is shown in Fig The trend for Si MOS devices can be found in several recent publications all showing similar results[19, 67]. An opposite stress dependence is observed with an increase in tunneling current for Ge and a decrease for Si. The key difference in the gate tunneling mechanism between Si and Ge devices is due to the position of conduction band minimum (X for Si and L for Ge)[54]. To understand the difference, strain effects on the conduction sub-band structure of Si and Ge are illustrated in Fig For Si, due to different out-of-plane effective masses of 2 valley (0.92m 0 ) and 4 valley (0.19m 0 ), electron repopulation between these two valleys plays an important role in strain-altered gate leakage current[18]. The decrease in the gate tunneling current of Si results from repopulation into the 2 sub-band with a larger out-of-plane effective mass. In addition, the 2 sub-band shift leads to an increased barrier height. In Ge, the out-ofplane effective masses of the 8-fold degenerate Λ valleys are the same (0.12m 0 )[54]. Since Λ(110) and Λ 110) ( have the same out-of-plane effective mass and barrier height (without the applied stress), τ (0) is identical to τ (0), resulting in A(0) in (6) equal to zero. The Λ( 110) Λ(110) 37

38 degeneracy of Λ(110) and Λ 110) also results in n (0) = n (0) and B(0) = C(0) in (3-6). ( Λ( 110) Thus for Ge, Δ τ ( σ ) / τ (0) (second and third terms in (3-6)) is the dominant effect which is altered via strain by changes in the HfO 2 to Ge barrier height, as shown in Fig. 3-2(c). At lower gate bias, the relative change ofτ as a function of stress is larger, based on (3-8). Therefore, the relative change of stress altered gate leakage current at lower gate bias is larger than at higher gate bias, consistent with the experimental data in Fig. 3-3 and 3-4. Also, we observe, in Fig. 3-5, the increase of the gate leakage current in Ge device is approximately 3 times smaller than the decrease in the Si device. Λ(110) Figure 3-3. The [100] tensile stress-altered gate tunneling current for Ge MOS device under different gate biases. Current is increased due to reduced barrier height resulting from E Hydro. The inset represents schematic band diagram of sub-band in inversion with no stress and tensile stress along [100]. 38

39 Figure 3-4. [110] tensile stress-altered gate tunneling current of Ge MOS device under different gate biases. Current is increased due to reduced barrier height of electrons in Λ(110) energy level. The inset shows schematic band diagram with strain-induced sub-band splitting between Λ(110) and Λ (1 10) sub-bands. Figure 3-5. The [110] tensile stress-altered electron gate tunneling current of Ge and Si devices at inversion charge of /cm 2, where 1.2 V and 0.6 V gate biases are applied for Si and Ge MOS devices, respectively.[68] Si data are from reference [19] (measured from n-mosfets with N+ poly gate and SiO 2 dielectric). Note that strain-altered current is increased in Ge while decreased in Si due to the different position of conduction band minimum (X for Si and L for Ge).[54] 39

40 Figure 3-6. Schematic band diagrams for [110] tensile stress effects on electron gate tunneling in (a) Si and (b) Ge devices, respectively. A decrease in tunneling current for Si device is induced by 1) barrier height enhancement of mostly populated 2 and 2) electron repopulation into 2 sub-bands, which has higher out-of-plane effective mass(0.92m 0 ), while only barrier height lowering of Λ(110) contributes to an increase of tunneling current of Ge MOS device Extraction of Conduction Band Deformation Potentials In this section, the conduction band deformation potentials of Ge are extracted from the strain-altered gate tunneling current. Since stress along [100] only causes a Δ shear band splitting on the Λ valley structure, 3. To extract Ξ Hydro Hydro E shift and no Hydro Δ E can be determined from the data in Fig. 3- and capture the change in the tunneling current under the applied stress in the full range of gate voltages, Fig. 3-7 shows the change of slope in Fig. 3-3 or d[δ I ( σ ) / I (0)] dσ versus applied gate bias. G G / Hydro Ξ is used to fit the experimentally measured data[2, 53]. To illustrate the goodness of the model fit, maximum deviation curves are plotted in which Hydro Ξ ranges from 1.2 to 1.5 ev. The model fits well with the data over the range of gate 40

41 bias from 0.5V to 1.1V. The same procedure is employed for stress along [110] to determine the two deformation potentials of Ξ d and Ξ u. The slope of Fig. 3-4 was extracted and compared with fitting models over the entire gate bias range (0.5~1.1 V) in Fig The obtained values of deformation potential constants (Ξ d and Ξ u ) are compared with hydrostatic deformation potential Hydro Hydro 1 constants ( Ξ ) from stress along [100], based on Ξ = Ξ d + Ξ u [53]. The best fitting 3 values of Ξ d and Ξ u in Fig. 3-8 are in good agreement with Hydro Ξ in Fig The obtained deformation potentials ( Ξ d = 4.3 ± 0. 3and Ξ = 16.5 ± 0. ev ) listed in Table 3-1 are close to u 5 the theoretical values by Fischetti et al. ( Ξ d = 4. 43and Ξ = 16. ev )[17]. u 8 Figure 3-7. Change in slopes ( d[δ I G ( σ ) / I G (0)]/ dσ ) versus gate voltage with 95% confidence error bars for tensile stress along [100]. Best fits (1 and 2) for the entire data set occur for Ξ Hydro = 1.3 and 1.4 ev. Maximum deviations (3 and 4) from the data occur for Ξ Hydro = 1.2 and 1.5 ev. 41

42 Figure 3-8. Change in slopes ( d[δ I ( σ ) / I (0)] dσ ) versus gate voltage with 95% confidence G G / error bars for tensile stress along [110]. Best fits (2, 3, and 4) for the entire data set occur for Ξ d = -4.2 to -4.4 and Ξ u =16.5 to 16.8 ev. Maximum deviations (1 and 5) from the data set occur for Ξ d = -4.1 and -4.5 and Ξ u =17.0 and 16.0 ev, respectively. Table 3-1. Dilation (Ξ d ) and shear (Ξ u ) deformation potentials extracted from gate tunneling current of Ge MOS device under tensile stress along [100] and [110]. Comparison is made with previous theoretical and experimental results.[17, 53, 55, 69, 70] All quantities are in ev Summary In summary, measurement of the electron gate leakage currents under two different mechanical stress conditions provides a method to extract the Ge conduction band deformation potentials. For uniaxial tensile stress along [110] and [100], the change in gate leakage current for Ge is measured to be 3 times smaller than that of Si n-mos device and opposite in sign. This reverse behavior occurs because tensile stress for Si causes electron repopulation into Δ 2 42

43 increasing the out-of-plane effective mass while, in Ge, a reduced tunneling barrier is the dominant mechanism, resulting from the hydrostatic shift of the conduction band edge. Although the hydrostatic shift of Si is larger than that of Ge, its contribution to the strain-altered gate leakage current change in Si is not as critical as in Ge due to the primary role of electron repopulation via shear strain-induced band splitting in Si. 3.2 P-type metal-oxide-semiconductor field effect transistors Experimental Set-Up Three different kinds of samples are used in this work: (1) Ge <110> channel/(100) surface p-mosfets with TiN metal gate and 3.0 nm HfO 2 /interlayer (IL) stacked dielectric fabricated on n-type Ge substrate, (2) Si <110> channel/(100) surface p-mosfets with p+ poly-si gate and 1.3 nm SiO 2 fabricated on n-well, and (3) Si MOS capacitors with TaN gate and 2.5 nm SiO 2 fabricated on p-type Si substrate. Conventional carrier separation method is used to measure the electron and hole tunneling currents for the Ge and Si p-mosfets[71-73]. Fig. 3-9 is a schematic illustration of carrier separation and 4-point wafer bending. The electron (from the gate) and hole (from the substrate) tunneling currents are measured with source and drain physically tied to ground and the gate negatively biased. Mechanical uniaxial stress is applied longitudinal to the <110> channels of Ge and Si MOSFETs. The hole and electron tunneling currents are measured using a Keithley 4200 dc characterization system. Devices with different areas are measured and the current density exhibits no area dependence, which indicates a negligible edge tunneling effect[74]. To measure the magnitude of metal gate work-function shift under mechanical stress, Si MOS capacitors have been used for C-V measurements with HP 4294 to measure flat band voltage shift ( V FB ). 43

44 Figure 3-9. Carrier separation measurement of p-mosfet and 4-point wafer bending. The gate tunneling current (I G ) can be separated into electrons (I G,electron )and holes (I G,hole ) tunneling from gate and substrate, respectively.[75] Stress Altered Hole Tunneling Currents of Ge and Si p-mosfets Fig. 3-10(a) shows the carrier separation for Ge and Fig. 3-10(b) for Si p-mosfets. For both type of devices, the gate current, I G, is nearly identical with the source/drain current, I S/D, showing hole tunneling current from inversion layer is the dominant mechanism consistent with previous studies[64, 76, 77]. In Ge device, I S/D is lower and the portion of I SUB in I G is larger than that in the Si device due to 1) HfO 2 dielectric with larger equivalent oxide thickness and 2) TiN metal electrode with free electrons[73, 77]. Fig shows the relative hole gate tunneling current change in Ge and Si p-mosfet as a function of applied external mechanical stress. Theoretical calculation for the stress altered hole tunneling current, based on the self-consistent solution to the Poisson and Schrödinger s equation for Si and Ge, are also shown in Fig. 3-11[20]. A six band k p approximation is used for the calculation of charge density and out-of-plane effective mass[42]. The hole tunneling probability, based on a WKB approximation,[64, 65] is used to fit the experimental data. The 44

45 dominant tunneling mechanism for high-k dielectric can be either trap-assisted tunneling (Poole- Frenkel (PF) emission) or classical tunneling (direct or FN tunneling), depending on the thickness of dielectric and the quality of the high-k/substrate interface and bulk dielectric[62, 67, 78]. In our samples, we determine the dominant mechanism for gate tunneling current to be classical tunneling (direct or FN tunneling), based on two reasons: 1) PF plot is not linear (not shown)[79] and 2) hole tunneling occurs through thin higher band gap interlayer (PF emission is dominant for the device with thick dielectric)[67]. The strain altered hole tunneling current for both Ge and Si p-mosfets increase with stress and the relative change in Ge is approximately 4 times larger than that in Si. The measured data can be understood from strain altered out-of-plane effective mass and hole repopulation between the top two sub-bands (E 1 and E 2 )[80]. Fig shows a schematic drawing of the hole tunneling process from E 1 and E 2 and the strain induced sub-band energy shift. For both Ge and Si, the strain altered out-of-plane hole effective masses of E 1 and E 2 are observed to be fairly constant at the Γ point for stress < ~200 MPa and listed in Fig. 3-12(c)[13]. The band splitting at low stress and moderate to high gate bias is set by confinement and with E 1 having larger strain altered out-of-plane effective mass becomes the top band[80]. Applied tensile stress causes the E 1 to E 2 band splitting to decrease resulting in hole repopulation from E 1 to E 2, as shown in Fig. 3-12(b)[19, 20]. For tensile stress, the hole tunneling current enhancements of both Ge and Si devices result from hole repopulation into E 2, which has a smaller tunneling barrier height ( φ B, 2 < φb, 1 ) and out-of-plane effective mass ( z z me me 1 2 < ). Compared to Si, the larger increase in strain altered hole tunneling current of Ge can be explained by larger 1) stress induced valence band edge splitting and 2) change in hole tunneling attempt frequency. 45

46 The hole repopulation can be quantified from the valence band edge splitting (ΔEv) as a function of stress[81]. Fig shows the valence band edge splitting in Ge and Si under no confinement, based on ΔE V as follows: [55] ΔE 1 d σ [110] 2 b (3-9) V = ( S11 S12 ) + 3( S 44 ) where σ [110] is the applied longitudinal stress, S ij is the elastic compliance constants and b and d are deformation potentials of valence band from Ref. [17]. Note that ΔEv of Ge is 1.5 times larger than that of Si, causing more hole repopulation in Ge. Fig plots the hole charge density in the top three sub-bands (E 1, E 2, and E 3 ) as a function of stress for a) Ge and b) Si, respectively. Note in this calculation, since the total charge density is approximately constant with applied stress, we use ΔN 1 +ΔN 2 +ΔN 3 = 0, where N i is hole charge density of each sub-band[20]. Since the 2D density of states of both Si and Ge do not change significantly at low stress (<200MPa)[82], hole repopulation from E 1 to E 2 mainly results from valence band edge splitting as seen in Fig. 3-13, leading to the larger increase in the hole tunneling of Ge, relative to Si. 1/ 2 The inversion-layer hole attempt frequency on gate dielectric barrier is also different for E 1 and E 2 [19]. Due to the larger mass ratio of Ge (E 1 /E 2 =0.12/0.05), compared to that of Si (0.26/0.21), the relative change of stress altered hole tunneling attempt frequency in Ge is larger, resulting in a larger increase in hole tunneling current for Ge. 46

47 Figure Carrier separation measurement of a) Source/drain (I S/D ) and substrate tunneling current (I SUB ) as a function of gate voltage (V G ) for Ge p-mosfet. b) I S/D and I SUB as a function of V G for Si p-mosfet. 47

48 Figure Relative change in I S/D of Si and Ge p-mosfet as a function of stress. Symbols and lines are measured data and modeling, respectively. The magnitude of hole tunneling current change in Ge is approximately 4 times larger than that in Si. Figure Schematic band diagram for the hole gate tunneling current in a p-mosfet on a (100) wafer. a) each subband has different tunneling barrier height. b) E 1 and E 2 subbands shift under stress results in hole repopulation into E 2 sub-band, which has lower tunneling barrier height and smaller out-of-plane effective mass. c) Strain altered outof-plane effective mass for each sub-band is listed in table. 48

49 Figure Valence band edge splitting of Ge and Si under tensile stress along [110] (not including confinement). Ge has larger valence band edge splitting than Si. 49

50 Figure Charge density versus applied stress for the top (E 1 ), bottom (E 2 ), and third subbands (E 3 ) at an inversion charge density of 3.5x10 13 /cm 2 for a) Ge and b) Si, respectively. Strain altered out-of-plane effective mass of each sub-band is denoted (e.g., 0.12 m 0 ). Note, due to larger valence band edge splitting of Ge, hole repopulation in Ge is more than in Si. 50

51 3.2.3 Stress Altered Electron Tunneling Currents From Metal Gate The carrier separation technique also allows the electron tunneling current via I SUB to be measured which is altered by strain due to a shift in the band offset between the gate electrode and dielectric [83]. Fig shows the relative change of I SUB as a function of stress for the Ge channel MOSFET. Due to the decreased TiN gate work-function with stress, I SUB increases, showing that the work-function of metal gate decreases under tensile stress. To quantify the metal work-function shift, V FB, where V FB Q OX = φ MS, is measured using COX capacitance-voltage measurement. Since the permittivity of SiO 2, the fixed oxide charge and the interface trapped charge does not change appreciably with applied stress [84] and the Fermi energy level of the silicon substrate only changes up to ~1mV at 200 MPa [85, 86], the metal work-function shift ( Δ φm ) can be approximated from V FB. Fig shows the C-V characteristics of MOS capacitor with TaN gate and V FB is measured to increases/decreases with compressive/tensile stress. Fig plots Δ φm of the TaN gate as a function of stress, obtained from Fig. 3-16(b) and compared to the work-function shifts of bulk metals[87, 88]. The stress altered work-function in TaN gate follows a similar trend as that in bulk metal of Al and Cu. The TaN work-function increases/decreases by approximately 4 mv at compressive/tensile stress of 200 MPa. The relative change in the stress altered electron gate tunneling current from the TaN gate to substrate is measured and plotted in Fig. 3-18[89]. The data is extracted at the gate bias of -1.7 V. The gate tunneling current increases/decreases with tensile/compressive stress. An analytical equation based on the electron direct tunneling model is employed to fit experimental data [90, 91]. 51

52 J * 1 / 2 * 1 / 2 q m (2m ) 3 / 2 (2m φb ( σ )) 2 = exp[ 2 φ ( ) d qed ] 2 2 * b σ + (3-10) 4π hd m h 2h where E V = G V d FB Ψ S Ψ S = V G V FB + qn A d ε Si / ε OX ( VG VFB + qn Ad ε Si / εox ) ( VG VFB) * where d is the oxide thickness and m ( = 0.5m) [92] and E is the effective electron mass and the electric field in the SiO 2 layer, respectively. Also, m, Ψ and φ b (σ ) is the electron mass S in the free space, the substrate bend bending and the effective barrier height as a function of * applied stress, respectively. We used the effective oxide thickness, d = d δ ( δ = 0.08nm) instead of the physical thickness due to the surface roughness or the uncertainty of electrical measurement for the determination of the oxide thickness[90]. For modeling, φ b (σ ) is estimated with the linear fit of Δ φm in Fig Our calculation shows good agreement with measured data in Fig The relative change in electron tunneling current increases/decreases up to 1.0% under 200 MPa of tensile/compressive stress, resulting from the decreased/increased metal gate work-function by 4meV. 52

53 Figure Relative change in I SUB of Ge p-mosfet as a function of stress at gate bias of - 2.8V. Due to decreased work-function of TiN gate, electron gate tunneling current from TiN gate increases up to ~4% with 100MPa of stress. The inset shows the decreased tunneling barrier height via strain by the decreased work-function of TiN gate. Figure The V FB shift under uniaxial stress. (a) C-V curve of MOS capacitor, measured at 100KHz. V FB is extracted from C FB.[93] (b) V FB shift as a function of tensile and compressive stress. V FB decreases /increases with tension/compression. 53

54 Figure Work-function shifts of TaN, bulk Al and bulk Cu as a function of stress[87]. Work-functions of three different metal increase/decrease with compressive/tensile stress. Line is the linear fit of extracted data. Figure Relative changes in gate tunneling current of MOS capacitor with TaN gate as a function of stress. Symbols and lines are measured data and modeling, respectively. 54

55 3.2.4 Summary Due to larger 1) stress induced valence band edge splitting and 2) change in hole tunneling attempt frequency in inversion-layer of Ge under uniaxial tensile stress, the change in stress altered hole gate tunneling current in Ge is ~4 times larger than that in Si. The work-function of the metal gate is measured to change with strain and decrease/increase ~20meV for each 1 GPa of uniaxial tensile/compressive stress. 55

56 CHAPTER 4 IMPACT OF MECHANICAL STRESS ON DIRECT AND TRAP-ASSISTED GATE LEAKAGE CURRENTS IN P-TYPE MOS CAPACITORS 4.1 Introduction State-of-the-art logic devices requires uniaxial stress to enhance transistor performance[80, 94]. Uniaxial stress is also being used in nonvolatile memory (NVM) to improve the retention time[95-97]. In NVM, trap-assisted gate tunneling current can be a dominate factor in the retention time[98] and the reliability of the tunneling dielectric[22, 23]. The high electric field during programming (Fowler-Nordheim tunneling) generates electron traps in the SiO 2 dielectric or at the SiO 2 /Si interface, resulting in trap-assisted gate tunneling[98]. It has been reported that mechanical stress affects trap generation in MOS devices [99, 100], but less attention has been paid to mechanical stress-altered trap-assisted gate tunneling current[67]. In this work, we report for the first time, the effects of uniaxial stress on trapassisted gate tunneling current using controlled applied mechanical stress and constant voltage stress (CVS). 4.2 Experimental Set-Up Samples used in this work consist of MOS capacitors with TaN metal gate on top of 2.5 nm SiO 2 dielectric fabricated on p-type (100) Si surface substrate. Large area 10 5 μm 2 devices are used to eliminate the fringe leakage components. The electric damage is created by -4.0 V of gate voltage for 50 seconds[101]. By monitoring the gate leakage current as a function of time at the fixed gate voltage, the CVS condition is adopted, where applied gate voltage generates traps, but does not cause dielectric breakdown. Due to the generated traps during CVS, trap-assisted tunneling becomes a dominant gate leakage mechanism, resulting in an increase in gate leakage current after CVS, compared to one before CVS[23]. Next, uniaxial 4-point external mechanical stress is apply along [110] direction while changes in the gate to substrate electron tunneling 56

57 current (negative gate bias) and electron gate tunneling from substrate to gate (positive gate bias) are measured[13]. The maximum gate voltage used during the gate leakage measurement (V G = ±1.7 V) is limited below the magnitude of the gate voltage in CVS condition (V G = -4 V) to ensure minimal gate oxide damage during this measurement. 4.3 Results and Discussions To understand the effects of uniaxial mechanical stress on gate leakage current in samples before and after CVS, both gate and substrate injections are measured under tensile and compressive stresses. Figure 4-1 shows the relative change of gate leakage current in samples before (Fig. 4-1(a)) and after CVS (Fig. 4-1(b)) as a function of mechanical stress. The relative changes for gate and substrate injections are extracted at the gate voltage of -1.7 V and 0.8 V, respectively[89]. In samples before CVS where direct electron tunneling is a dominant mechanism, gate and substrate injections show an opposing dependence on mechanical stress, as shown in Fig. 4-1(a). Under tensile (compressive) stress, gate injection increases (decreases) while substrate injection decreases (increases). For sample after CVS where the dominant leakage current is trap-assisted tunneling current, both gate and substrate injection is increased under tensile and compressive stresses, as shown in Fig. 4-1(b). Fig. 4-1(b) also shows a larger slope for the change in gate and substrate injections under compressive stress as compared to tensile stress. The effects of mechanical stress on direct and trap-assisted gate leakage currents can be understood with Fig Fig. 4.2(a) illustrates the impact of mechanical stress on direct gate tunneling for gate and substrate injections. Under gate injection, applied tensile (compressive) stress decreases (increases) the tunneling barrier height of electrons from gate to substrate via TaN gate work function shift, resulting in an increase (decrease) in gate leakage current[102]. 57

58 Under substrate injection, mechanical stress-induced electron repopulation between Δ 2 and Δ 4 sub-bands in the n-type inversion layer changes the out-of-plane effective mass and tunneling barrier height of electrons in Δ sub-bands as previously reported [18, 19, 21, 103]. During CVS for thin SiO 2 (< 2.5 nm), energetic electrons injected from gate to the Si substrate breaking dangling bonds in the [111] direction, normally passivated by hydrogen at P b0 and P b1 centers at near the SiO 2 /(100)Si interface [99]. These additional defects increase trap assisted tunneling currents [98, 101]. For trap-assisted gate tunneling, the detrapping of the SiO 2 electron plays a primary role in gate leakage current [104]. The trap activation energy, φ T, where φ T = E OX C E TRAP, determines the detrapping processes as illustrated in Fig. 4-2(b). Here, E OX C and ETRAP are the conduction band edge of SiO 2 and trap energy level, respectively, and φt is a function of applied mechanical stress (σ) [105]. Uniaxial mechanical stress along [110] direction alters the structure of P b0 and P b1 centers, as illustrated in Fig. 4-3 [99, ]. This affects the stability of interface traps, resulting in a change in φ T [108]. In P b0 center, compressive stress along [110] decreases bond angle Ө 1 and increases the other bond angle Ө 2, due to 1) (100) Si substrate surface structure and 2) dangling bond along [111] direction [99, 106]. For tensile stress along [110], it should have the opposite effect as that for compressive stress. The Ө decrease, Ө(σ) <0, means an increase in repulsive force between the dangling bond and at least one of the three back bonds, resulting in the less stable dangling bond, as described in Fig. 4-3(a) and table [106]. For P b1 center, the dangling bond with unstrained Ө (Ө = 45 ) is known to have minimum energy and either positive or negative Ө(σ) makes the dangling bond less stable, as shown in Fig. 4-3(b) [109]. Therefore, both compressive and tensile stresses along [110] cause a decrease in the trap activation energy 58

59 at P b0 and P b1 centers, Δ ( σ ) < 0 [67, 99, 110], resulting in an increase in trap-assisted gate φ T leakage current for both gate and substrate injections, as shown in Fig. 4-1(b). It is reported that a change in SiO 2 /(100) Si interface trap activation energy under compressive stress is larger than one under tensile stress [105, 111, 112], matching with our results that the relative change of trap-assisted gate leakage current under compressive stress is larger than under tensile stress (observed for both gate and substrate injections in Fig. 4-1(b)). 4.4 Conclusions Different dependences of gate leakage currents on uniaxial mechanical stress are observed from direct and trap-assisted gate tunneling currents. The CVS technique is used to generate traps at SiO 2 /(100) Si interface and monitor interface trap-assisted gate leakage current in MOS capacitor with 2.5 nm thin SiO 2. Both mechanical tensile and compressive stresses along [110] increase trap-assisted gate leakage current via the lowering of trap activation energy of P b0 and P b1 centers, showing that uniaxial stress along [110] may not be applicable to improve the gate leakage of logic devices and the retention time of NVM devices when trap-assisted tunneling is a dominant mechanism in gate leakage current. 59

60 Figure 4-1. Relative change of gate leakage currents in MOS devices (a) before constant voltage stress (CVS) and (b) after CVS as a function of applied mechanical stress along [110] direction, respectively. 60

61 Figure 4-2. Schematic band diagrams for a) direct and b) trap-assisted gate tunneling mechanisms. Key parameters for mechanical stress-altered electron gate tunneling currents before and after CVS are summarized in table A. Toda et al Figure 4-3. Schematic of SiO 2 /(100) Si interface structure including P b0 and P b1 centers, showing mechanical stress-induced changes in dangling bond angles (Ө) and interface trap activation energy (Φ T ). 61

62 CHAPTER 5 STRAIN INDUCED CHANGES IN GATE LEAKAGE CURRENT AND DIELECTRIC CONSTANT OF NITRIDED HF-SILICATE DIELECTRIC SILICON MOS CAPACITORS 5.1 Introduction Hafnium silicate has been extensively studied as a gate dielectric material in advanced metal oxide semiconductor field effect transistors (MOSFETs) due to a high crystallization temperature, thermodynamic stability with Si, high permittivity and relatively large band gap (5.68 ev) [ ]. Nitrogen incorporated Hf-silicate (HfSiON) has received attention since HfSiON minimizes interfacial layer formation and reduces boron diffusion from the poly-si gate into the channel [117, 118]. Also, recent reports have explained additional advantages of nitrided Hf-silicate such as increased dielectric constant and improved reliability [119, 120]. Strained silicon technology has been adopted in high-k gate stack MOSFETs, showing strain can improve mobility similarly for Hf-silicate MOSFETs compared to SiO 2 MOSFETs [82]. However, to date, there is no systematic and quantitative result on the strain altered dielectric constant and gate leakage current of HfSiON dielectric film. In this work, we report on the effect of mechanically applied uniaxial stress on the gate leakage current and dielectric constant of Si MOS capacitors with HfSiON gate dielectric. 5.2 Experimental Procedures The HfSiO x films are deposited directly on p-type (100) pre-cleaned (1% HF solution and DI water rinse) 8 inch Si substrates with a resistivity of 3-25 Ωcm using atomic layer deposition (ALD) at 300 o C. The oxidizing agents for TEMAH and Si are O 3 and H 2 O, respectively. HfSiO x film deposition is followed by nitrogen incorporation by rapid thermal anneal (RTA) at 650 o C in NH 3 ambient for 60 s. MOS capacitors with Pt and Al gate electrode were fabricated using RF magnetron sputtering. All of the metals were deposited by Ar plasma assisted RF sputtering at a pressure of 15 mtorr and 150W RF (13.56 MHz) power. For all MOS devices, post metallization 62

63 annealing (PMA) was carried out in a tube furnace at 400 o C in forming gas (10% H 2 / 90% N 2 ) ambient for 30 min. Capacitance-voltage (C-V) and current-voltage (J-V) measurements were measured with Agilent E4980A and Keithley 4200, respectively, using external mechanical uniaxial stress along the [110] direction [13]. To extract the frequency-independent device capacitance value and eliminate the effect of both series and shunt parasitic resistances, a twofrequency method is adopted [121]. The flat band voltage (V FB ) is extracted from the C-V measurements [122]. To reduce the electrical instability from HfSiON charging [123], a constant gate voltage (-1V) was applied for 160 s before J-V measurement. This reduces the J-V instability to less than 0.2% variation. 5.3 Results and Discussions Figure 5-1 shows the C-V (a) and J-V (b) characteristics of Hf-silicate dielectric MOS capacitors. In order to verify the gate tunneling conduction mechanism, aluminum (Al) and platinum (Pt) electrodes are used due to their large bulk work function difference ( φal 4.1 and φpt 5.8 ev) [124]. The accumulation capacitance values are almost identical (~ F/cm 2 ) resulting in an equivalent oxide thickness of 2.7 nm regardless of the gate electrodes[125]. The nearly identical accumulation capacitance and parallel shift of C-V curves for Pt and Al gate electrodes indicates that, regardless of gate material, a sharp interface and minimal interaction between the metal gate and dielectric film are maintained. Due to the difference in the work function of Pt and Al, a difference in V FB and larger leakage current under negative gate bias is observed for the Pt devices. The larger leakage current in Pt devices can be explained by the following: (1) the dominant leakage current mechanism is hole tunneling from the substrate to gate as opposed to electron tunneling from gate to substrate[126], and 2) a higher built-in oxide field of the Pt device results from a larger work function as illustrated in the inset of Fig

64 Figure 5-1. The C-V characteristics at 1MHz of the MOS device with Pt and Al gate on nitrided Hf-silicate film (a). The inset shows current density-voltage (J-V) measurements of both devices (b). Figure 5-2. Poole-Frenkel (ln(j/e) vs E 1/2 ) plot of Pt and Al gate on nitrided Hf-silicate film at 25 o C. Inset in figure shows a schematic band diagram for MOS capacitors with HfSiON dielectric and interlayer and metal gates (Pt and Al) under negative gate bias. 64

65 Fig. 5-2 shows the Poole-Frenkel (PF) plot for both metal electrodes with HfSiON gate dielectric. The slope of PF plot can be expressed as Δ ln( J / E) q q Slope ( σ ) = = (5-1) Δ E kt πε ( σ ) ε r 0 where k, T, ε r (σ ) and ε 0 are the Boltzmann constant, temperature, high frequency dielectric constant of the insulator under external stress, and vacuum permittivity, respectively. The high frequency dielectric constant without external stress extracted from the slope of the PF plot is 4.9. The refractive index, n, given by the square root of the high frequency dielectric constant,[127, 128] is found to be 2.23, showing that the extracted dielectric constant is within the range of refractive indices reported for HfSiON films (1.8~2.4)[129]. The normalized change in strain-altered gate leakage currents for Al and Pt HfSiON MOS capacitor are shown in Fig Regardless of electrodes, an increase in normalized leakage current is observed for both tensile and compressive stresses. Recently, Choi et al suggested that a decrease in trap activation energy results in an increase in trap-assisted gate leakage current under mechanical stress[130]. Based on a decrease in hole trap activation energy under mechanical stress [131] and a dominant hole tunneling gate leakage mechanism under negative gate bias in high-k dielectric[132], an increase in PF emission-based gate leakage may result from a decrease in hole trap activation energy in high-k dielectric under both tensile and compressive stresses. The measured normalized change in the strain altered dielectric constant of HfSiON, HfSiO x, and HfO 2 are shown in Fig Unlike HfO 2 and HfSiO x, the dielectric constant of HfSiON is observed to increase with both tensile and compressive stresses, as determined using two separate techniques, C-V curve and slope extraction from the PF plot shown in Fig

66 We propose that the incorporated nitrogen in Hf-silicate film may be the origin of the strain-induced dielectric constant change. The nitrogen incorporation creates a N p band above the valence band edge of HfSiO[119]. The N p band splitting by applied mechanical stress may lead to band gap narrowing of HfSiON, increasing the electronic transition from the N p band to the conduction band[133, 134]. This band gap narrowing should increase the HfSiON dielectric constant[119]. Figure 5-3. Changes in gate leakage current of Si MOS capacitors with HfSiON dielectric as a function of applied stress. 66

67 Figure 5-4. Changes in dielectric constant of HfSiON, HfSiO x and HfO 2, measured from C-V and PF slope change. To date, there have been no reports on strain altering the dielectric constant of SiON which is commonly used for gate dielectrics in advance logic technologies. One explanation is that for SiON, nitrogen incorporation into SiO 2 primarily occurs at the SiO 2 /Si interface. XPS measurement results show no observed band gap narrowing of SiO 2 due to N p band formation near valence band edge of SiO 2 [135]. Thus, the dielectric constant of SiON is not expected to change significantly for mechanical stress range (<100 MPa) used in this work. 5.4 Conclusions The impact of four point wafer bending uniaxial stress on gate leakage and gate dielectric constant of Si MOS capacitor with HfSiON has been studied. A measured increase in strainaltered gate leakage is attributed to a decrease in hole trap activation energy in HfSiON. An increase in HfSiON dielectric constant is also observed under both tensile and compressive 67

68 stresses. Thus, in additional to strain enhanced channel mobility, strained HfSiON may provide a slight additional improvement via an increase in oxide capacitance. 68

69 CHAPTER 6 IMPACT OF DIFFERENT GATE STACKS AND CHANNEL MATERIALS ON THRESHOLD VOLTAGE SHIFTS IN P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER MECHANICAL STRESS 6.1 Introduction Uniaxial strained-si has been adopted to increase performance in sub-90nm production technologies[24, 31, 80]. Strain-induced threshold voltage, V th, shift can be a critical issue[136]. However, little attention has been given to V th shift in uniaxial technology[137]. V th shift in Si p- MOSFETs is generally regarded as insignificant without any quantitative explanation[138]. Because scaling has reached fundamental material limits for gate stacks and channels, we can now scale with new materials and/or device architectures. TiN/HfO 2 gate stack and strained- Ge have been expected to be substitutes for poly Si/SiO 2 gate stack and strained-si because of their smaller gate leakage and higher channel mobility, respectively[139, 140]. Therefore the investigation of strain-altered V th shift of these devices is timely and worthy. In this work, uniaxial strain-induced V th shifts of both Ge and Si p-mosfets with TiN/HfO 2 gate stacks are explained and compared to poly Si gate stacks. The contribution of strain-induced mobility change to measured V th shifts is also considered. 6.2 Threshold Voltage Shift Models The V th shift for a Si p-mosfet with a poly Si gate under mechanical stress can be derived from [136, 137]; where Δ E g (σ ), m, N C and m kt N (0) C (0) kt mdp Δ Vth ( σ ) = mδe g ( σ ) ( m 1) ln( ) m ln( ) (6-1) q N ( σ ) q m ( σ ) dp C are the change in the band gap with stress, the body-coefficient, the effective densities of states (DOS) in the 3-D conduction band and the 2-D hole DOS dp 69

70 effective mass in the predominant sub-band, respectively. The same derivation can be used for Si and Ge p-mosfets with TiN gate, as shown in (6-2) kt N (0) C (0) kt mdp Δ Vth ( σ ) = ΔφM ( σ ) + ΔEC ( σ ) mδe g ( σ ) ( m 1) ln( ) m ln( ) (6-2) q N ( σ ) q m ( σ ) where Δφ M (σ ) and Δ E C (σ ) are the changes in the gate work-function [102] and channel electron C dp affinity and ΔEC and E g Δ contribute to the V th, but with different signs. Here, ΔφM is positive/negative under compression/tension[87, 102, 141]. Note that, in (6-2), a TiN gate device has both ΔEC and Δ E g, while, in (1), a poly Si gate device has Δ E g only. This is because both the Si channel and the poly Si gate are being strained in poly Si gate device[137]. Deformation potential theory is used to express ΔEC and ΔE g as a function of stress. Strain induces the hydrostatic shift and shear band splitting of conduction band edges, which can be expressed as; [53, 55, 84] Δ E = Ξ Tr( ε ) + Ξ ε (6-3) i C d ij u ii where Ξ and Ξ are dilation and shear deformation potential constants, Tr(ε ij ) is the trace of the d u strain tensor ( ε ij ) and i denotes the various valleys (X for Si and L for Ge). For Si and Ge, ΔEC and Δ E g are calculated and listed in Table 6-1[17, 55]. Strain-induced changes in DOS-related terms also shift V th (last two terms in (6-1) and (6-2)). The change in the effective DOS in the 3-D conduction band is given * 3 / 2 * 3 / 2 by N ( 0) / N ( σ ) = m (0) / m ( σ ).[142] In both Si and Ge, N C -related term is negative, C C C C * * irrespective of the type of stress, because stress along [110] causes m ( σ ) < (0) via band C m C splitting [137]. For low stress and moderate to high gate bias, the predominant sub-band in the hole inversion-layer can be determined by gate bias since the energy level splitting from 70

71 confinement is dominant[80]. Therefore, applied stress alters m (σ ) only via valence band warping, resulting in m (σ ) to increase/decrease with compression/tension[13, 80]. Therefore, m dp dp -related term is positive/negative with compression/tension. The contribution of dp N - and m C dp -related terms are significant under tension because both of terms are negative, while under compression, the two terms are opposite in sign. Both (6-1) and (6-2) were derived based on equal inversion charge at the threshold condition [136]. To relate these expressions to the measured V th shift [143], the correction term is needed to account for the change in mobility in the strained channel and given; kt μ( σ ) Δ V th ( σ ) = m ln( ) (6-4) q μ(0) 6.3 Results And Discussion Strain-induced V th shifts are calculated and compared with wafer bending data. Fig. 6-1(a) plots V th shifts of Si p-mosfets with poly Si and TiN gates, respectively. Under compression, the V th shift in TiN gate devices is ~2/3 times of that in poly Si gate devices, while it is larger than that in poly Si gate devices under tension. This mainly results from subtractive Δ EC in TiN gate devices, as explained in Sec It is also found that, for poly Si gate devices, the V th shift under compression is larger than tension, because there is larger band gap narrowing from compression and smaller contribution of DOS-related terms[84]. Fig. 6-1(b) plots V th shifts of Ge and Si p-mosfets with TiN gate. Based on the calculation using (6-2), larger V th shifts for Ge are expected under compression because, relative to Si p-mosfet, the Ge channel has larger band edge shift terms ( Δ E ( σ ) mδe ( σ ) ). C g Next, the mobility correction term is considered. Uniaxial stress along [110] causes channel mobility to change significantly relative to biaxial strain[80]. The contribution of 71

72 mobility change to the V th shift, which has been regarded as insignificant in biaxial strain, may be critical in uniaxial strain [136]. Fig. 6-2 plots the strain-induced V th shift of Ge and Si p- MOSFETs with TiN gates with the mobility correction. The inset shows that the relative change in mobility of Si is slightly larger than that of Ge, which is extracted from measured drain current change [82, 93]. Based on mobility change, we calculate the contribution of mobility change terms, listed in Table 6-2, where model-predicted contributions of band-edge shift, DOS-related terms, and ΔφM are also indicated. As expected, the contribution of mobility change to measured V th shifts is significant and even dominant for Si devices. Note that after the correction, the V th shift of Ge is slightly larger than that of Si, resulting in insignificant V th shifts of both Ge and Si p-mosfets with TiN/HfO 2 gate stacks. 6.4 Conclusion Both Ge and Si p-mosfets with TiN gates are observed to have insignificant V t variation under uniaxial stress. The simple V th shift model including the mobility correction shows good agreements with the measured data from different types of p-mosfets, demonstrating its universality [144]. 72

73 Table 6-1. Deformation potential constants used in this study [17] and tension and compression along [110] direction. DEFORMATION POTENTIAL CONSTANTS [EV] Ξ d =1.0, Ξ u =9.6 Si B=-2.33, D=-4.75 Ξ u Ξ d + a 3 =0.29 STRESS TYPE ΔEC and ΔE g of Si and Ge, calculated at 300 MPa of uniaxial E C E G TENSION COMPRESSION Ge Ξ d =-4.3, Ξ u =16.5 b=-2.16, d=-6.06 Ξ d Ξ + u a 3 =-0.83 TENSION COMPRESSION

74 Table 6-2. Model-predicted, with m=1.3, contributions of band edge shifts, DOS change, Δµ and ΔΦ M terms. (ΔΦ M is estimated from [102]) THEORETICAL VALUE EXPERIMENTAL VALUE STRESS TYPE V TH FROM BAND EDGE SHIFT V TH FROM DOS- RELATED TERMS 100MPA V TH FROM Δµ V TH FROM ΔΦ M Si TENSION COMPRESS ION Ge TENSION COMPRESS ION

75 W. Zhao 2004 S. Suthram 2008 Figure 6-1. Plots of uniaxial stressed V th shifts of p-mosfets with (a) different gate stacks (poly Si/SiO 2 vs TiN/HfO 2 ) and (b) different channels (Ge vs Si). Symbols and lines are experimental data and calculated models, respectively. Note here that ΔV th < 0 would mean that the magnitude of V th (which is negative) is increased by stress. 75

76 Figure 6-2. Plots of V th shifts of Ge and Si p-mosfets with the mobility correction as a function of stress. Symbols and lines are experimental data and calculated models, respectively. The inset shows the relative changes in mobility of Ge and Si p- MOSFETs with TiN/HfO 2 gate stack as a function of stress. 76

77 CHAPTER 7 RELIABILITY OF NITRIDED HAFNIUM SILICATE GATE DIELECTRICS UNDER [110] UNIAXIAL MECHANICAL STRESS: TIME DEPENDENT DIELECTRIC BREAKDOWN 7.1 Introduction State-of-the-art CMOS devices requires uniaxial stress to enhance the performance of transistor with high k gate stack[145]. Among the candidates for high-k dielectrics, nitrided hafnium silicate (HfSiON) is a promising material due to high crystallization temperature and thermodynamic stability with Si[146]. The reliability of HfSiON Si MOS device, such as time dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and threshold voltage (V TH ) instability, and hot carrier injection (HCI) also has been extensively studied to help improve device lifetime[147]. It has been reported that applied mechanical stress changes TDDB and negative bias temperature instability (NBTI) in SiO 2 dielectric Si MOS device[100, ] but less attention has been focused on impact of applied mechanical stress on TDDB and NBTI in HfSiON[111, 151]. Furthermore, most of these works have used process-induced strain, such as a nitride stressor, which can contain hydrogen and water and introduce ambiguity into the strain effect on device reliability[100, ]. In this work, we report on the effects of both uniaxial tensile and compressive stresses on TDDB in HfSiON Si MOS devices using controlled applied external mechanical stress. From the mechanical stress dependence and thickness independence, possible degradation mechanisms are identified. Mechanical stress-induced BTI, HCI, and V TH instability of high k MOSFETs are also briefly discussed. 77

78 7.2 Experimental Setup Samples used in this work consist of MOS capacitors with aluminum metal gate on top of 7 and 8 nm HfSiON dielectrics fabricated on p-type (100) Si substrate[155]. Samples with gate area of , , , and cm 2 are used. Constant negative gate voltage stressing is performed with a gate leakage current compliance limit of 10 pa using a Keithley 4200 DC characterization system. We define the time to breakdown (t BD ) as the first sudden increase in the gate leakage current (soft breakdown), as shown in Figure 7-1[147, ]. The steep increase in the gate leakage current upon onset of breakdown allows measurement of the breakdown event at a well-defined electric field. A custom built four point wafer bending setup is used to apply external mechanical stress along the [110] direction during constant voltage stressing (CVS)[13]. The impact of mechanical stress on the distribution of t BD and charge to breakdown (Q BD ) is monitored in the HfSiON MOS capacitor samples. Figure 7-1. Current-time curve for 7 nm HfSiON dielectric Si MOS device during CVS 78

79 7.3 Experimental Results In this section, experimental data on the distributions of t BD and Q BD in HfSiON Si MOS capacitors under both mechanical tensile and compressive stress is reported. Figure 7-2(a) shows t BD Weibull plots with different area samples with 7 nm thick HfSiON dielectrics, where an areadependent t BD distribution is observed [159]. When the results are scaled by area as in Figure 2(b), the scaled t BD Weibull curves coincide which indicates an intrinsic breakdown mechanism. The area scaled t BD is computed based on the following equation. j i A j / A i F ( t) = 1 (1 F ( t)) (7-1) where F j and Fi are the probability of failure at area is 1.2, which is close to the published value[156]. A j and A i [111, 160]. The Weibull slope (β) To understand the impact of uniaxial mechanical stress on t BD in samples, CVS is performed with V G = -5.2 and -7 V under tensile and compressive stresses, respectively. Fig.7-3 and 7-4 show impact of mechanical stress on t BD Weibull plots. Applied tensile stress reduces time to breakdown at 50% (t BD,50% ) from 44 to 15 sec and β from 1.4 to 1.1, respectively, as shown in Fig. 7-3(a) and (b). In addition, compressive stress, in Fig. 7-4(a) and (b), also reduces t BD,50% from 24 to 7.3 sec and β from 0.81 to 0.74, respectively. In summary, both applied tensile and compressive stresses degrade t BD of HfSiON dielectric, consistent with the previously reported data from process-induced strain and SiO 2 dielectrics[111, 148, 161]. Mechanical stress dependence on t BD can be investigated by (1) monitoring the relative change in gate injection current of HfSiON Si MOS device as a function of applied mechanical stress[149] and (2) mechanical stress-induced increase in HfSiON/Si interface trap generation during CVS[111]. In our previous work[155], we already observed an increase in gate injection current, based on Poole-Frenkel emission, under both tensile and compressive stresses, matching 79

80 with our mechanical stress dependence on t BD in this work. Hence, it is consistent with the observation that an increase in gate injection current results in a decrease of t BD.[149]. It has been reported that, for gate stack with high-k dielectric thicker than 7~8 nm, Q BD for gate injection is equivalent with those for SiO 2 with a thickness identical to the interfacial layer [158]. In Fig. 7-5, Q BD for 8 nm thick HfSiON is measured and compared to Q BD in samples with 7 nm thick HfSiON in order to confirm this interfacial layer breakdown mechanism. Since interface quality is independent of the thickness of HfSiON [162], it shows almost similar Q BD distributions under 84 MPa of tensile and no mechanical stresses. Therefore, impact of mechanical stress on t BD in HfSiON Si MOS device can be explained by mechanical stressaltered trap generation in Si-rich HfSiON interlayer (IL) or at IL / (100) Si interface during CVS [111]. Both tensile and compressive mechanical stresses facilitate trap generation at IL / (100) Si interface or Si-O bond breaking in IL [99, 100, 105, 109, 111]. Figure7-2. The t BD distributions and area scaled t BD distributions for different size samples under V G = -5.2 V. 80

81 Figure 7-3. Uniaxial tensile stress effect a) on t BD distributions and b) on area scaled t BD distributions under V G = -5.2 V. Figure 7-4. Uniaxial compressive stress effect a) on t BD distributions and b) on area scaled t BD distributions under V G = -7 V. 81

82 Figure 7-5. The Q BD distributions for samples with two different HfSiON dielectrics thickness (7 and 8 nm) under tensile mechanical stress 7.4 Discussion In this section, physical insight into impact of mechanical stress on reliability issues, such as BTI, HCI, thermal stress-induced subthreshold leakage and V TH instability, will be provided based on how applied mechanical stress affects high k/si interface trap generation and trap activation energy in high k dielectric. In previous section, impact of mechanical stress on TDDB of 7 nm thick HfSiON Si MOS device with negative gate voltage stressing was discussed. If TDDB occurs in thin (< 3 nm) high k or with positive gate voltage stressing, it does not involved significant interface trap generation and may be dependent on high k layer not Si rich interlayer[158]. This can result in improved TDDB with mechanical stress if mechanical stress reduces gate tunneling current[149]. Since a dominant gate tunneling mechanism in thick (> 3 nm) high k MOS device is Poole-Frenkel emission[158] and mechanical stress increases Poole-Frenkel emission or trap-assisted gate 82

83 tunneling[130, 155], TDDB under mechanical stress may be improved only in thin (< 3 nm) high k, where mechanical stress can decrease direct gate tunneling current[102]. It is widely proposed that NBTI also results from the generation of trap via Si-H bond breaking at high k/si interface[158, ]. Fig. 7-6(a) shows high resolution TEM image of HfSiON Si MOS capacitor, which contains SiO 2 -like Si rich interlayer. Since mechanical stress makes Si-H bond less stable, as illustrated in Fig. 7-6(b) and (c)[109], both [110] tensile and compressive mechanical stresses may degrade NBTI in high k Si MOSFETs [100, 166]. As discussed above, positive bias temperature instability (PBTI) may not generate interface trap but involve charge trapping in high k bulk or high k/si interface [158, 165]. This may result in improved PBTI via mechanical stress-induced increase in charge detrapping in thick (> 7 nm) HfO 2 Si MOSFET [131]. An insignificant process-induced stress dependence of PBTI in thin (3 nm) high k Si MOSFET has been already reported, resulting from negligible charge trapping in thin high k layer [151, 167]. Thermal stress-induced sub-threshold leakage, which can degrade the retention time of dynamic random access memory (DRAM) [168], also results from Si-H bond breaking at high k/si interface [168, 169]. Therefore, both [110] tensile and compressive stresses likely increase thermal stress-induced sub-threshold leakage in high k Si MOSFETs via strain-enhanced hydrogen depassivation at high k/si interface [109]. It has been reported that HCI and V TH instability likely result from a trapping of charges in the pre-existing traps in high k/si interface and/or high k dielectric without creation of additional traps [105, 107, 108, 158, 170]. Due to its technological importance, impact of external mechanical stress on HCI has been aggressively studied, showing opposite trends[105, 107, 108, 170, 171]. Two strain-related models can explain this discrepancy: (1) a decrease in charge 83

84 trapping in relative thick gate dielectric via strain-altered trap activation energy[105, 107, 108] and (2) strain-induced Si band gap narrowing and an increase in impact ionization at drain edge[170, 171]. For both uniaxial tensile and compressive stresses, a decrease in a trapping of injected hot carriers in high k likely results in an improved HCI, [130, 131] while an increase in impact ionization may multiply a number of hot carriers, leading to an degradation of HCI [84]. In high k integration, V TH instability has been one of challenges[158]. As explained above, applied mechanical stress reduces electron or/and hole trap activation energy in high k/si interface and/or high k dielectric[130, 131]. This results in (1) an increase in trap-assisted gate tunneling (or Poole-Frenkel emission) and (2) a decrease in charge trapping in high k[130, 131]. Therefore, V TH instability can be improved at the expense of an increased trap-assisted gate tunneling leakage under both uniaxial tensile and compressive stresses. Due to substantial reduction of gate leakage in high k device,[165] this trade-off will be beneficial for device performance. Table 7-1 and Fig. 7-7 summarize impact of uniaxial mechanical stress on reliability issues with thick (~ 7 nm) high k Si MOSFETs as discussed above. Most of reliability issues in strained Si technology may be evaluated with impact of mechanical stress on trap activation energy in high k and on high k/si interface trap generation. 84

85 1999 Figure 7-6. Interface trap generation under mechanical stress. a) High resolution TEM image of HfSiON Si MOS capacitor. The gate dielectric is composed of Hf rich HfSiON and Si rich interlayer. b) Schematic of Si rich interlayer/ (100) Si interface including Si-H bonding. c) The calculated energies corresponding to the hydrogen position [109]. Here, E Si-H is Si-H bonding energy and σ is applied uniaxial stress. Figure 7-7. Schematic band diagram for key strain-related parameters for reliability issues.here, E A,H and E A,E is hole and electron trap activation energy, σ is applied uniaxial stress, Q ot, I G, and N it is trapped charge density, gate leakage, and the number of interface trap, respectively. 85