EV Group Solutions for Compound Semiconductor Manufacturing

Transcription

1 EV Group Solutions for Compound Semiconductor Manufacturing

2 EV Group Solutions for Compound Semiconductor Manufacturing Introduction Compound semiconductor devices have been linked with airborne and military applications for a long time. More recently, with increasing requirements from consumer electronics, compound semiconductors found inroads to large-scale production. In particular, rising data volumes and transmission speeds for mobile devices enabled high growth rates of radio front-end devices, consisting of three basic building blocks, namely filter/duplexer, power amplifier and antenna switch. All of these parts are being manufactured to a large extent of compound semiconductors. Besides radio front-end application on GaAs substrates novel applications arise, increasing the importance of compound semiconductors for several applications. As an example, photonic interconnects for high speed, low State-of-the-art Die-Sized SAW package (DSSP ) Copyright EPCOS AG 2013 loss and largely improved bandwidth is one of them. These devices are mostly indium phosphide (InP) based. Since InP is difficult to grow on low cost wafers and with large size, wafer bonding considerably gains importance. In general, wafer bonding and more specifically direct wafer bonding with the aid of plasma activation, levels the ground for compound semiconductors to be implemented in a complementary metal oxide semiconductor (CMOS) production scale. With the maturing market position of compound semiconductors, common processing and packaging technologies from advanced CMOS and micro electro mechanical systems (MEMS) are paving its way. Advanced packaging is one prominent example, where CMOS and compound semiconductor design and processing blend together. EV Group is a recognized leader of processing technology for wafer bonding, optical lithography, nanoimprint lithography and wafer level packaging. EVG's Process Portfolio...etc. EVG Processes Wafer & Template Fabrication Substrate Bonding for SOI Substrate Cleaning Plasma Activation Resist Coating Spin/Spray Alignment Verification Proximity Lithography Nanoimprint Lithography Resist Developing Metallization RIE, DRIE Wet Etching Resist Lift-Off CVD, LPCVD, PVD,... Thermal Oxide Growing Bond Alignment Thinning, CMP Wafer Bonding Temporary Bonding/ Debonding Wafer Dicing Stress Relief Etching Electroplating Chip-to- Wafer Bonding Wafer Bumping & Redistribution 2

3 Nano Imprint Lithography Nano patterns are a novel topic for most parts of the compound semiconductor applications. Recently, nano patterns spurred a lot of attention for growth substrates, such as nano patterned sapphire substrates (npss) or for selective area growth of nanowires. However, these are not the only solutions. Photonic elements, such as wire grid polarizers, color filters or gratings, are frequently used applications, facilitating nano patterns in compound semiconductors. Nano imprint lithography (NIL) is an ideally suited replication method for such nanometer structures. The typical properties of compound semiconductor substrates high bow, varying TTV and defects after epitaxial growth have been shown to be challenging for conventional lithography methods. Same is true for high resolution capability of less than 50 nm, which is needed for many photonic applications. EVG s lineup of NIL tools fulfills all above requirements, in order to provide a cost effective, high quality, full-field nano patterning. Advantages of EVG s nano imprint lithography solution: Same tool for imprinting and stamp replication Mask lifetime comparable to lithography masks Room-temperature process without run-out or alignment issues due to thermal expansion in stamp manufacturing and imprinting Control of stamp material (Young s modulus, surface energy...) Working stamp can be used multiple times before disposal Imprint nanostructures UV curing Detach Stamp Reuse stamp Dispense liquid resin Parallel alignment of stamp and substrate Imprint at low pressure Expose with UV light through stamp and crosslink Photonic structures on the top surface greatly enhance the LED light output Detach stamp from substrate Reuse soft stamp SEM image of a photonic crystal fabricated by nanoimprint lithography 3 Micro contact printing tool in the EVG 620 EVG 7200 Automated UV-NIL System up to 200 mm EVG SmartNIL full area imprinted 150 mm Si substrate 3

4 EV Group Solutions for Compound Semiconductor Manufacturing Wafer Bonding for Compound Semiconductors Direct wafer bonding for heterogeneous integration of compound semiconductors Several applications as power, RF, biosensing, photovoltaic and photonic devices will benefit from improvements in power efficiency, performance, size, weight, reliability and cost driven by the integration of compound semiconductor materials. These improvements are often referred to as More than Moore, since they are not directly related to lithographic scaling, and they are enabling an ever increasing array of electronic devices and applications. Today s plasma-activated direct bonding processes give additional freedom for the device design and process implementation. It has been proven for several years that most compound semiconductors can be directly bonded on different substrates. This was enabled by plasma-activated fusion bonding, which lowers the required anneal temperatures below critical temperature levels that can cause wafers to break because of the stress induced by differences in the thermal expansion coefficients. This method incorporates a SiO 2 bond interface, which can be as thin as the native oxide. Some devices can benefit from this oxide layer as it reduces parasitic effects like leakage current or cross talk to the substrate. Advantages of fusion bonding for compound semiconductors: Direct stacking of heterogenous compound semiconductors Use of inexpensive carrier substrates for processing and re-use of expensive epitaxial growth wafers Generation of advanced, complex and novel devices stacks by direct wafer bonding Recent technology developments such as EVG s ComBond technology, can provide a covalent oxide-free bond interface. Furthermore, this new approach enables the joining of different materials at very low or room temperature, which keeps the thermally induced stress between the wafers to a minimum. EVG 580 ComBond Automated High-Vacuum wafer Bonding System - Enabling oxide free electrically conductive interfaces The EVG580 ComBond adds a new milestone to EVG s unique portfolio of wafer bonding equipment and technology in response to market needs for more sophisticated integration processes to combine materials with different lattice constant and coefficient of thermal expansion (CTE). Wafer bonding can combine different substrate materials while avoiding defects due to lattice and CTE mismatch that are associated with traditional epitaxial processes. Room-temperature covalent bonding, in particular, is an ideal choice since it eliminates the need for annealing processes, which generate high temperatures that can add additional stress due to CTE mismatch. However, a key limitation of room-temperature covalent bonding has been the inability to maintain tight control of the thickness and uniformity of the bond interface, including effective removal of particle contaminants and the native oxide layers. These are necessary in order to achieve an interface that has both sufficient bond strength and electrical conductivity between the bonded materials. The EVG580 ComBond wafer bonding platform combines several technology breakthroughs to enable the formation of bond interfaces between heterogeneous materials at room temperature while achieving excellent bond strength and electrical conductivity. GaAs 200mm LowTemp plasma activation chamber EVG 580 ComBond Automated High-Vacuum Wafer Bonding System 2 nm InP GaAs InP Bond Interface* *Courtesy of Fraunhofer ISE 4

5 Wafer Level Die Bonding The wafer level die transfer bonding concept separates the two processes of chip placement on the wafer and the actual chip-to-wafer bonding process. Nonetheless, a wafer level approach still has several key advantages, such as collective pre-processing of the dies and high bonding throughput. This cannot be provided easily with die-to-die bonding. However, a wafer-level die transfer process combines the best of both worlds, which is the fast distribution of the known good die (KGD) and high-quality direct bonding at the wafer level. Furthermore, this easily allows tuning of bonding conditions as it enables collective bonding at elevated temperatures or even in vacuum conditions. A key requirement to enable such a process is to apply uniform pressure on every single die, not just generally over the whole wafer. As shown in the figure on the right hand side, several issues can occur that inhibit a homogenous pressure distribution. Thus, the process has to be set up to comply with bow and warpage, unevenness of the substrate as well as die height variations. Introducing a compliant layer can compensate for these challenges and enable the application of similar force on the different die, thus providing optimal transfer rates and high bonding yield. In this way, heterogeneous integration can be scaled up to larger substrates and multiple functions can be added to the device wafer even in volume production. Multi-Substrate Bonding EV Group has implemented multi-substrate bonding in combination with a high system throughput. The unique design of EVG s multi-substrate wafer bonders maintain high system flexibility to bond different substrate sizes on the same equipment with minimal changeover time. Field proven compliant layer technology avoids chipping and breakage of valuable wafers. EVG s fully automated wafer bonding system for LED manufacturing offers flexible tool support for metal, adhesive and fusion bonds of various substrate types. Cassette-to-cassette operation, multisubstrate bonding capability and a modular design with up to four swap-in process modules make the EVG500 series the perfect solution for LED manufacturing from R&D to HVM needs. EVG s field proven wafer bonding technology, as well as the unique approach to low temperature metal wafer bonding, results in high throughput and yields. Multi-substrate bonding systems for LEDs High throughput up to 160 bonds/h (50 mm wafer equivalents) Optimized pressure and temperature uniformity for highest possible yield Automatic handling of bowed and warped wafers Low temperature metal wafer bonding Integrated pre-processing modules for low-temperature metal wafer bonding Eutectic, Transient-Liquid-Phase (TLP) and thermo-compression bonding E.g. Au-Au, Au-In, Au-Sn, Cu-Sn, Cu-Cu,... Cross section SEM image of Au:Sn bonded wafers C-SAM image of a patterned wafer pair bonded with Au:Sn EVG 500 Series Bond Module Fully Automated Wafer Bonding System for High-Volume Manufacturing 5

6 EV Group Solutions for Compound Semiconductor Manufacturing Back End Wafer Processing EVG OmniSpray for polymeric and photoresist coatings Polymer coatings enable improved functionality for compound semiconductor devices. Besides their use as insulating layers, polymer coatings exhibit advantages for other applications. The low dielectric constant (low-k) of polymers facilitated higher switching frequencies of compound semiconductor devices. In turn, this enables faster data standards. On the other hand, elevated on-chip interconnects called air bridges, are used for the same reason. To cope with reliability demands, these fragile gold structures need rigid support. In addition, polymers such as PBO or BCB are standard for scratch protection layers, as an overcoat to protect the wafer front side for the following back side processing. EVG s OmniSpray technology is a universal coating technology that accomplishes such demanding coating applications. Depending on the application, different types of polymer compounds are available on the market, such as epoxies, polyimides, BCB, PBO or silicones. Varying material characteristics, hence varying process requirements, recommend OmniSpray as universal coating technology. In addition, OmniSpray helps to reduce material usage up to 80%, considerably lowering the bill of material and working on an improved cost-of-ownership. Advantages of EVG s OmniSpray for Compound semiconductors: Reduced resist consumption (up to 80%), especially important for expensive encapsulates such as PBO, BCB or polyimide Universal technology to coat polymers with largely varying solids content and viscosities Ideal for planarization applications (spray / spin process combination) Uniform coating of deep trenches and high aspect ratio features Special setup for high viscosity polymers Ideal for thick resist coating applications Underfill Process with spray and spin coating (courtesy of Agilent Technologies) Spray coated cavities with high topography EVG proprietary OmniSpray resist atomization nozzle EVG 150 Fully-automated Resist Processing System: Coating of thick and thin resists such as required for optical lithography and adhesive packaging Spin and spray coating capability in the same bowl Spray Coating with X-Y Scanning or rotary motion Simplified operator usability and serviceability Reduced process qualification time Minimized footprint for highest fab utilization Fast changeover times for multiple substrate sizes Advanced handling and processing of bowed / warped wafers EVG 150 Fully-automated Resist Processing System up to 200mm EVG 150 Modular tool layout for highest flexibility EVG 150 Modular chemical storage units and advance tool access for optimized serviceabiliy 6

7 Back End Wafer Processing Optical Lithography Optical lithography is still a work horse for multiple applications in compound semiconductor manufacturing. Device structures on the semiconductor wafer, encapsulation based wafer level packaging, bumping, patterning of through wafer vias (TWV), are just a few of the most common applications. Compound semiconductor specific requirements: Processing of bowed/warped as well as transparent substrates Image recognition of shallow etching-generated topography: Development of special optics to align such low-contrast structures is a key for highest overlay accuracy and maximum process yield. Customized wafer chuck designs for efficient flattening of compound semiconductor wafers and hence a constant print gap Non-contact processing of delicate and brittle compound semiconductor wafer for maximum yield Processing of thin wafers: Thin wafers with sufficient thickness to be self-supportive, can be directly being processed with special handling and process options. If this is not the case, thin wafers are typically carrier mounted and the thin wafers are processed on top. Both EVG aligner platforms the EVG620/EVG6200 series as well as the IQ Aligner are designed for compound semiconductor characteristic processing specifications. EVG 620 HBL Fully-automated mask aligner for compound semiconductors: Attractive Cost-of-Ownership and low CapEx High throughput (165 wafers/h in aligned mode / 220 wafers/h for first print applications) High overlay accuracy for multiple mask processing (front-to-front side, front-to-back side) High print resolution for homogenous current distribution Advanced handling and processing of bowed / warped wafers Fast changeover times for multiple substrate sizes Image based pre-aligner for transparent or sapphire mounted wafers Thin wafer and carrier mounted wafer processing EVG 620 HBL Fully-automated mask aligner for compound semiconductor manufacturing EVG 620 Mask Alignment System: easy access for manual loading for wafers and also wafer pieces EVG 620 Handling module with 5 cassette stations allows processing of 125 wafers per process run EVG 620NT Manual Mask/ Bond Alignment System 7

8 EV Group Solutions for Compound Semiconductor Manufacturing Back Side Wafer Processing Temporary Bonding and Debonding for advanced thin wafer handling Compound semiconductor materials such as GaAs, SiC, LiTaO 3 or InP offer distinct electrical advantages, but typically suffer from the low thermal conductivity. The most effective method for heat transfer is wafer thinning. Due to the brittleness of these materials, thin compound semiconductor wafers are temporarily bonded to a rigid carrier for thinning and back side processing. The bonded wafers can be processed in standard fabs with standard equipment. Thermal management of compound semiconductor devices was the primary driver for thin wafers and devices in the past. Recently, the reduced form factor has become the most important driver. The starting point is a device wafer with complete front-end processing on the front side of the wafer. This device wafer is bonded to a carrier wafer with its front side in the bond interface. After bonding the first step is back-thinning of the wafer. Usually back-thinning is a multistep process consisting of mechanical back-grinding and subsequent stress relief etching and polishing. After back-thinning the back side of the device wafer can be processed using standard wafer fab equipment. The carrier wafer gives mechanical support and stability and protects the fragile wafer edge of the thin wafer. Finally, when all back side processing is done, the wafer gets debonded, cleaned and transferred to a film frame or to other output formats. EV Group provides production equipment for temporary bonding and debonding since We have the largest install base and are the clear market share leader. EV Group has more than 20 years of experience in wafer bonding. Temporary Bonding / Debonding Principle Temporary Bonding Debonding Device Wafer Front-End Processing (Lithography, etching, etc.) Wafer Stack mounted on Film Frame Device Wafer Debonding Carrier Wafer with Adhesive Film Temporary Bonding Device Wafer bonded on Carrier Wafer Cleaning Back Thinning and further Processing Device Wafer (thinned) on Carrier Wafer Thin Wafer on Film Frame Double end effectors for rapid wafer handling EVG 820 Adhesive Tape Punch Module Thin 6" wafer mounted onto dicing tape 8

9 LowTEMP Debonding EVG ZoneBond Open Platform EVG LowTemp ZoneBOND is a revolutionary breakthrough in thin-wafer processing. It enables room temperature debonding, which is independent of the properties of the temporary adhesive, providing a versatile supply chain with multiple adhesive suppliers. EVG ZoneBond Debonding Technology Features: EVG ZoneBond Open Platform, including license for ZoneBond with multiple adhesives Breaking the link between the debonding method and adhesive properties Fully automated carrier preparation integrated into the high volume manufacturing EVG850TB/DB system Multilayer Adhesive Debonding EVG LowTemp debonding technology includes room temperature multilayer adhesive debonding, where the separation of the carrier and device wafer is initiated mechanically. Several temporary bonding adhesives are available for this debonding solution. EVG Multilayer Adhesive Debonding: Room temperature debonding by mechanical separation Universal equipment technology enabling all common mechanical debond adhesives and techniques Full control and monitoring of the mechanical debonding process Laser-Initiated Debonding The laser debonding process being developed at EVG is based on excimer lasers. For their spectral range, standard glass carriers offer high transmission, keeping carrier cost low. In contrast to laser induced thermal debonding, the ultraviolet light emitted by excimer lasers is absorbed within a few hundred nanometers of the glass/adhesive interface, thereby leaving the thin wafer entirely unaffected. EVG Laser Debonding Technology Features: No thermal stress subjected to the device wafer Lowest cumulative costs in virtue of single adhesive layer technology requiring no additional release layer application High throughput capability using field proven excimer laser technology High thermal resistance up to 350 C Thermal Debonding Thermal Slide-Off Debonding Thermoplastic adhesives are rigid at room temperature, but have reduced viscosity at elevated temperature. This drop in viscosity enables a unique debonding mechanism - thermal slide-off debonding. At the debonding temperature, the viscosity of the adhesive is reduced, which enables a controlled debonding of the thin device wafer from the carrier wafer. Slide-Off Debonding Technology Features: High volume, production proven technology Industry leading thin wafer handling and cleaning technology for highest yield without wafer breakage Market leading solutions in thermal sliding and thin wafer handling Thermal Lift-Off Debonding Multiple dry film adhesive tapes are available for temporary bonding. Dry film adhesive tapes usually consist of a backing foil with adhesive films plus protective liners on both sides. Both adhesive films are bondable, but different debonding mechanisms are used for either side. This allows controlled debonding, whereby the separation between thin device wafer and carrier wafer happens at the interface between device wafer and tape. Next, the tape is peeled off of the carrier wafer, which enables recycling of the carriers. EVG 850TB Spin Coat Module EVG 850DB Debond Module EVG 850DB Film Frame Mount Module 9

10 EV Group Solutions for Compound Semiconductor Manufacturing Wafer Level Packaging Introduction to Wafer Level Packaging (WLP) Today, wafer level packaging (WLP) is a mainstream technology in micro electro mechanical systems (MEMS) and advanced complementary metal oxide semiconductor (CMOS). Bringing this packaging technology to compound semiconductors enables more compact packages, imperative for consumer devices. The wafer-level approach furthermore helps for cost reduction and ramping to high production volumes. Major benefits for wafer level packaging of compound semiconductors are: Batch fabrication packaging processes Compact packaging possible Increased functional density Improved circuit performance Reduce higher order assembly cost, relax module assembly requirement Hermetic packaging possible These days, WLP is grouped into an cap-based and encapsulation-based packaging approach. Encapsulation-based Wafer Level Packages Encapsulation-based wafer level packaging (WLP) is besides capping-based WLP most prominent in the market right now. Major difference to prior discussed packages formed by wafer bonding is the creation of a protecting shell by thin film deposition. Depending on the requirements of the later package, either inorganic shell materials, for vacuum and hermetic packages, or polymer materials are used. For polymers, shielding is not gas-tight. However, for consumer electronics protection from environmental influences, moisture and dirt, gives sufficient durability. 1. Spin on UV curable resist 4. UV exposure of resist 2. UV exposure of resist 5. Development of resist 3. Vertical sidewalls within the resist 6. Sealing of the package in controlled atmosphere EVG s resist processing & mask aligner technology for encapsulation-based WLP features: Coating and patterning of sacrificial spacers, defining the cavity dimension and volume Etching mask generation for openings in inorganic films such as oxide or nitride based capping layers Direct patterning of photoactive polymer encapsulates, such as SU8, BCB or ShinEtsu SINR Wet chemical sacrificial layer removal of over coating and enclosure device cavities Etch mask patterning or lithographic opening of electrical contacts EVG GEMINI Fully Automated Wafer Bonding System EVG 500 Series Bond Module SmartView Align Module 10

11 Wafer Level Packaging Capping-based Wafer Level Packaging Wafer-level capping is already a common process for MEMS and CMOS packaging. However, standard processes from these markets are most of the time not directly applicable to compound semiconductor packaging. A generic manufacturing process is depicted below. Depending on the sealing material, the according bonding temperature is directly influenced, same as the sealing characteristics. Requirements for wafer bonding of compound semiconductor WLP are stringent. Deep know-how of various bonding techniques and decision factors for each of them is one of EVG s strengths. In the case of capping-based WLP, where interlayers in the form of sealing rings are patterned prior to bonding, the following techniques and materials are most prominent in the market right now: Eutectic Bonding Solder Bonding Thermally cured adhesive bonding EVG s extensive experience of more than 25 years in the wafer bonding market guarantees for best bonding results and highest yields. EVG s core competences comprise wafer to wafer alignment, temperature distortion management for lowest bow, strain engineering, leading planarity, bonding of brittle substrates, and many more. Direct Bonding Molecular Bonding Anodic Bonding Wafer Bonding Eutectic Bonding Metal Bonding Solder Bonding Bonding with Inter-Layers Glass Frit Bonding Adhesive Bonding Metal Thermocompression Bonding UV-Cured Polymer Thermally Cured Polymer Schematic wafer level capping process flow Flow chart covering all wafer bonding technologies featured on EVG bonders with prominent CS WLP techniques highlighted in red Source: EVG KMPR cavity sidewall produced on a EVG 150 and EVG 620 (Source: Triquint, presented at CSMantech 2012) EVG Logo in 400µm SU-8 on 6" Wafer IQ Aligner Topside mask alignment 11

12 EV Group Solutions for Compound Semiconductor Manufacturing Nano Imprint Lithography Solutions EVG 620NT Semi-Automated UV-NIL, µ-cp System up to 150 mm UV Nano Imprinting Microcontact Printing EVG 720/7200 Automated UV-NIL System up to 150/200 mm UV Nano Imprinting EVG SmartNIL TM EVG 770 Automated NIL Stepper up to 300 mm UV Nano Imprinting Step-and-Repeat Imprinting Master Fabrication Cleaning and Metrology EVG 301 Semi-automated Single Wafer Cleaning System to 300 mm Megasonic Cleaning Brush cleaning DI-water / Diluted Chemicals EVG 40NT Semi-automated Measurement System up to 300 mm Overlay Alignment Verification Front-to-Backside Alignment Verification EVG 40NT Automated Measurement System up to 300 mm Overlay Alignment Verification Front-to-Backside Alignment Verification Advanced Wafer Handling Temporary Bonding Solutions EVG 805 Semi-automated Debonding System up to 300 mm EVG 820 Lamination System up to 300 mm EVG 850TB Automated Temporary Bonding System up to 300 mm EVG 850DB Automated Debonding System up to 300 mm Debonding Advanced Wafer Handling Integrated Dry Film Lamination from Temporary Bonding 50 mm mm Coat, Bake and Bond Precision Aligned Lamination on Modules Carrier Wafer Protective Film Remover (de-lamination) Debonding Wafer Cleaning Film Frame Mounting 12

13 Resist Processing Solutions EVG 101 Advanced Resist Processing System up to 300 mm Spin Coating Spray Coating EVG 120 Automated Resist Processing System up to 300 mm Spin Coating Spray Coating Bake Advanced Wafer Handling EVG 150 Automated Resist Processing System up to 300 mm Spin Coating Spray Coating Bake Advanced Wafer Handling Lithography Solutions EVG 620NT Automated Mask Alignment System up to 150 mm Mask Alignment Bond Alignment Advanced Wafer Handling EVG 620 HBL Automated Mask Alignment System up to 150 mm Mask Alignment Bond Alignment Advanced Wafer Handling IQ Aligner Automated Mask Alignment System up to 300 mm Mask Alignment Bond Alignment Advanced Wafer Handling Integrated (Nanoimprint) Lithography Solutions HERCULES L Lithography Track System resist processing & expose configuration up to 300 mm Spin Coating Spray Coating Bake Mask Alignment Advanced Wafer Handling HERCULES Lithography Track System coat/align & expose/develop configuration up to 300 mm Spin Coating Spray Coating Bake Mask Alignment Advanced Wafer Handling Developing HERCULES NIL Integrated UV-NIL Track System up to 200 mm Cleaning Spin Coating Bake SmartNIL TM Nanoimprinting 13

14 EV Group Solutions for Compound Semiconductor Manufacturing Bond Alignment Solutions EVG 620 Semi-Automated Bond Alignment System up to 150 mm EVG 6200 Semi-Automated Bond Alignment System up to 200 mm SmartView NT Automated Bond Alignment System for Universal Alignment up to 300 mm Bond Alignment Bond Alignment Bond Alignment Wafer Bonding / Hot Embossing Solutions EVG 510HE Semi-automated Hot Embossing System up to 200 mm Hot Embossing High-Temperature Embossing EVG 520IS Semi-automated Wafer Bonding System up to 200 mm Permanent Bonding Multi-Substrate Bonding EVG 540 Automated Wafer Bonding System up to 300 mm Permanent Bonding Multi-Substrate Bonding Integrated Wafer Bonding Solutions EVG 560 Automated Wafer Bonding System up to 300 mm Mechanical Alignment Permanent Bonding Multi-substrate Bonding GEMINI Automated Production Wafer Bonding System up to 300 mm Optical Alignment Permanent Bonding Multi-substrate Bonding Plasma Activation Wafer Cleaning EVG 580 ComBond Automated High-Vacuum Wafer Bonding System up to 200 mm Covalent, Oxide-free Bonding Room Temperature Bonding High-Vacuum Bonding Optical Prealigner 14

15 Overview: EVG s Process Capabilities Cleaning Spin Coating Spray Coating Nano Spray Bake Mask Alignment UV Nano Imprinting Alignment Verification Developing Bond Alignment Wafer Bonding Plasma Activation Lens Molding Edge handling for double-side cleaning; Megasonic nozzles or area transducers; Scrubber brush; Compatible with solvents, removers and diluted chemicals Thin and thick resist processing; Programmable dispense arm for various dispense modes High topography coating; Deep etched cavities; Coating of square, irregular shaped and perforated substrates Through silicon via coating; Sidewall passivation High temperature uniformity; Proximity heating; Edge handling Optical pattern recognition of low contrast samples; Topside alignment; Bottomside alignment; Transmissive and reflective IR; Shadow mask alignment Full-field nano imprinting; Step and repeat master replication Overlay measurement; Top to bottom measurement Spray, stream and puddle dispensing; Fully programmable dispenser Through wafer alignment; Backside alignment; Transmissive and reflective IR; SmartView alignment Thermocompression bonding; Eutectic bonding; Transient liquid phase bonding; Fusion bonding; Anodic bonding; Adhesive bonding; Glass frit bonding Plasma activation for semiconductor direct bonding Wafer level optics for beam shaping; Step and repeat lens master fabrication; Temporary Bonding / Debonding Advanced Wafer Handling Processing of thin wafers, bow, warped or fragile substrates; Various bonding and debonding processes Handling of thin, warped or fragile wafers; Edge wafer handling; Special endeffectors 15

16 EV Global Group Locations Solutions for Compound Semiconductor Manufacturing Headquarters Worldwide Sales and Customer Support EV Group Europe & Asia/Pacific GmbH DI Erich Thallner Strasse St.Florian am Inn Austria Phone: Fax: Sales@EVGroup.com Germany EV Group E. Thallner GmbH Hartham Neuhaus Germany Phone: Fax: Sales@EVGroup.com Europe Tech Support Phone: TechSupportEU@EVGroup.com Japan EV Group Japan KK Yokohama Business Park East Tower 1F 134, Godo-cho, Hodogaya-ku, Yokohama-shi, Kanagawa, Phone: Fax: Sales@EVGroup.jp Japan Tech Support Phone: (Yokohama) Phone: (Fukuoka) TechSupportJP@EVGroup.com Korea EV Group Korea Ltd. Room 503, Seokun Tower, 178, Pangyoyeok-ro, Bundang-gu, Seongnam-si, Gyeonggi-do, , South Korea Phone: Fax: Sales@EVGroup.co.kr North America EV Group Inc South River Parkway Tempe, AZ Phone: Fax: SalesUS@EVGroup.com EV Group Inc. 100 Great Oaks Blvd; Suite #119 Albany, NY SalesUS@EVGroup.com North America Tech Support Phone: TechSupportUS@EVGroup.com Taiwan Sales EVG-JOINTECH CORP. No. 400, Hwang-Pei Road Chung-Li City, Phone: Fax: Sales@EVG-Jointech.com.tw Taiwan Customer Support EV Group Taiwan Ltd. North Office: No. 400, Hwang-Pei Road Chung-Li City, South Office: Rm203, NO.12, Nanke 2nd RD, Xinshi Dist., Tainan City, Phone: Fax: (North Office) Fax: (South Office) CustomerSupportTW@EVGroup.com China EV Group China Ltd. Room , Building No. 3, No. 498 Guo Shou Jing Road, Zhangjiang High-Tech Park, Pudong New Area, Shanghai, PR China, Shanghai Phone: Fax: Sales@EVGroup.cn ServiceCN@EVGroup.com Data, design and specifications may not simultaneously apply; or depend on individual equipment configuration, process conditions and materials and may vary accordingly. EVG reserves the right to change data, design and specifications without prior notice. All trademarks, logos, website addresses or equipment names that contain the letters or words EVG or EV Group or any combination thereof, as well as the following names and acronyms are registered trademarks and/or the property of EV Group: ComBond, CoverSpin, EZB, EZ Bond, EZD, EZ Debond, EZR, EZ Release, GEMINI, HERCULES, HyperIntegration, IQ Aligner, LowTemp, NanoAlign, NanoFill, NanoSpray, NIL-COM, NILPhotonics, OmniSpray, SmartEdge, SmartNIL, SmartView, The Triple i Company Invent-Innovate-Implement, Triple i. Other product and company names may be registered trademarks of their respective owners. ZoneBOND is a registered trademark of Brewer Science, Inc. Other product and company names may be registered trademarks of their respective owners. Printed on paper from sustainable sources EV Group (EVG). All rights reserved. V01/16 16