CD4536BMS. CMOS Programmable Timer. Description. Features. Functional Diagram. Pinout. December 1992

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1 53MS ecember 99 Features High Voltage Tye (V atig) Fli-Flo Stage - outs from to Last Stages Selectable by Select ode yass Iut llows yassig First Stages O-hi Oscillator Provisio lock Ihibit Iut Schmitt Trigger i clock Lie Permits Oeratio with Very Log ise ad Fall Times O-hi Moostable Outut Provisio Tyical fl = 3MHz at V = V Test Mode llows Fast Test Sequece Set ad eset Iuts aable of rivig Two Low Power TTL Loads, Oe Lower Power Schottky Load, or Two HTL Loads Over the ated Temerature age % Tested for uiescet urret at V 5V, V ad 5V Parametric atigs Stadardized, Symmetrical Outut haracteristics Meets ll equiremets of JEE Tetative Stadard o. 3, Stadard Secificatios for escritio of Series MOS evices Piout escritio MOS Programmable Timer 53MS is a rogrammable timer cosistig of rile biary couter stages. The saliet feature of this device is its flexibility. The device ca cout from to or the first stages ca be byassed to allow a outut, selectable by a -bit code, from ay oe of the remaiig stages. It ca be drive by a exteral clock or a oscillator that ca be costructed usig o-chi comoets. Iut I serves as either the exteral clock iut or the iut to the o-chi oscillator. OUT ad OUT are coectio termials for the exteral comoets. I additio, a o-chi moostable circuit is rovided to allow a variable ulse width outut. Various timig fuctios ca be achieved usig combiatios of these caabilities. logic o the -YPSS iut eables a byass of the first stages ad makes stage 9 the first couter stage of the last stages. Selectio of of oututs is accomlished by the decoder ad the iuts,, ad. MOO I is the timig iut for the o-chi moostable oscillator. Groudig of the MOO I termial through a resistor of kω or higher, disables the oe-shot circuit ad coects the decoder directly to the EOE OUT termial. resistor to V ad a caacitor to groud from the MOO I termial eables the oe-shot circuit ad cotrols its ulse width. fast test mode is eabled by a logic o -YPSS, SET, ad ESET. This mode divides the -stage couter ito three -stage sectios to facilitate a fast test sequece. The 53MS is sulied i these -lead outlie ackages: raze Seal IP Frit Seal IP eramic Flatack HX HF HW Fuctioal iagram SET ESET I OUT OUT -YPSS LOK IHIIT MS TOP VIEW V MOO I OS IHIIT EOE OUT IY SELET -YPSS 9 IY SELET SET ESET 5 MOO I LOK I IHIIT OS IHIIT 7 3 S OUT 5 OUT T 3 EOE OUT = V = UTIO: These devices are sesitive to electrostatic discharge; follow roer I Hadlig Procedures. --ITESIL or oyright Itersil ororatio File umber 335

2 Secificatios 53MS bsolute Maximum atigs Suly Voltage age, (V) V to +V (Voltage efereced to Termials) Iut Voltage age, ll Iuts V to V +.5V Iut urret, y Oe Iut ±m Oeratig Temerature age o to +5 o Package Tyes, F, K, H Storage Temerature age (TSTG) o to +5 o Lead Temerature (urig Solderig) o t istace / ± /3 Ich (.59mm ±.79mm) from case for s Maximum eliability Iformatio Thermal esistace θ ja θ jc eramic IP ad FIT Package..... o /W o /W Flatack Package o /W o /W Maximum Package Power issiatio (P) at +5 o For T = -55 o to + o (Package Tye, F, K) mW For T = + o to +5 o (Package Tye, F, K)......erate Liearity at mw/ o to mw evice issiatio er Outut Trasistor mw For T = Full Package Temerature age (ll Package Tyes) Juctio Temerature o TLE. ELETIL PEFOME HTEISTIS GOUP LIMITS PMETE SYMOL OITIOS (OTE ) SUGOUPS TEMPETUE MI MX UITS Suly urret I V = V, VI = V or G +5 o - µ +5 o - µ V = V, VI = V or G 3-55 o - µ Iut Leakage urret IIL VI = V or G V = +5 o o - - V = V 3-55 o - - Iut Leakage urret IIH VI = V or G V = +5 o - +5 o - V = V 3-55 o - Outut Voltage VOL5 V = 5V, o Load,, 3 +5 o, +5 o, -55 o - 5 mv Outut Voltage VOH5 V = 5V, o Load (ote 3),, 3 +5 o, +5 o, -55 o.95 - V Outut urret (Sik) IOL5 V = 5V, VOUT =.V +5 o.53 - m Outut urret (Sik) IOL V = V, VOUT =.5V +5 o. - m Outut urret (Sik) IOL5 V = 5V, VOUT =.5V +5 o m Outut urret (Source) IOH5 V = 5V, VOUT =.V +5 o m Outut urret (Source) IOH5 V = 5V, VOUT =.5V +5 o - -. m Outut urret (Source) IOH V = V, VOUT = 9.5V +5 o - -. m Outut urret (Source) IOH5 V = 5V, VOUT = 3.5V +5 o m Threshold Voltage VTH V = V, ISS = -µ +5 o V P Threshold Voltage VPTH = V, I = µ +5 o.7. V Fuctioal F V =.V, VI = V or G 7 +5 o VOH > VOL < V V = V, VI = V or G 7 +5 o V/ V/ V = V, VI = V or G +5 o V = 3V, VI = V or G -55 o Iut Voltage Low (ote ) VIL V = 5V, VOH >.5V, VOL <.5V,, 3 +5 o, +5 o, -55 o -.5 V Iut Voltage High (ote ) Iut Voltage Low (ote ) Iut Voltage High (ote ) OTES: VIH V = 5V, VOH >.5V, VOL <.5V,, 3 +5 o, +5 o, -55 o V VIL VIH V = 5V, VOH > 3.5V, VOL <.5V V = 5V, VOH > 3.5V, VOL <.5V. ll voltages refereced to device G, % testig beig imlemeted.. Go/o Go test with limits alied to iuts.,, 3 +5 o, +5 o, -55 o - V,, 3 +5 o, +5 o, -55 o - V 3. For accuracy, voltage is measured differetially to V. Limit is.5v max. 7-37

3 Secificatios 53MS TLE. ELETIL PEFOME HTEISTIS PMETE SYMOL OITIOS (OTE, ) Proagatio elay lock to -yass High Proagatio elay lock to -yass Low Proagatio elay lock to TPHL TPLH TPHL TPLH GOUP SUGOUPS TEMPETUE MI LIMITS MX UITS V = 5V, VI = V or G 9 +5 o - s, +5 o, -55 o - 7 s V = 5V, VI = V or G 9 +5 o - 5 s, +5 o, -55 o - 75 s TPHL3 V = 5V, VI = V or G 9 +5 o - s TPLH3, +5 o, -55 o - s Proagatio elay TPHL V = 5V, VI = V or G 9 +5 o - s eset to, +5 o, -55 o - s Trasitio Time TTHL V = 5V, VI = V or G 9 +5 o - s TTLH, +5 o, -55 o - 7 s Maximum lock Iut FL V = 5V, VI = V or G 9 +5 o.5 - MHz Frequecy, +5 o, -55 o.37 - MHz OTES:. V = 5V, L = 5F, L = K, Iut T, TF < s o ad +5 o limits guarateed, % testig beig imlemeted. TLE 3. ELETIL PEFOME HTEISTIS LIMITS PMETE SYMOL OITIOS OTES TEMPETUE MI MX UITS Suly urret I V = 5V, VI = V or G, -55 o, +5 o - 5 µ +5 o - 5 µ V = V, VI = V or G, -55 o, +5 o - µ +5 o - 3 µ V = 5V, VI = V or G, -55 o, +5 o - µ +5 o - µ Outut Voltage VOL V = 5V, o Load, +5 o, +5 o, mv 55 o Outut Voltage VOL V = V, o Load, +5 o, +5 o, - 55 o Outut Voltage VOH V = 5V, o Load, +5 o, +5 o, - 55 o Outut Voltage VOH V = V, o Load, +5 o, +5 o, - 55 o - 5 mv.95 - V V Outut urret (Sik) IOL5 V = 5V, VOUT =.V, +5 o.3 - m -55 o. - m Outut urret (Sik) IOL V = V, VOUT =.5V, +5 o.9 - m -55 o. - m Outut urret (Sik) IOL5 V = 5V, VOUT =.5V, +5 o. - m -55 o. - m Outut urret (Source) IOH5 V = 5V, VOUT =.V, +5 o m -55 o - -. m Outut urret (Source) IOH5 V = 5V, VOUT =.5V, +5 o m -55 o - -. m Outut urret (Source) IOH V = V, VOUT = 9.5V, +5 o m -55 o - -. m 7-3

4 Secificatios 53MS Outut urret (Source) IOH5 V =5V, VOUT = 3.5V, +5 o - -. m -55 o - -. m Iut Voltage Low VIL V = V, VOH > 9V, VOL < V, +5 o, +5 o, -55 o - 3 V Iut Voltage High VIH V = V, VOH > 9V, VOL < V, +5 o, +5 o, -55 o +7 - V Proagatio elay lock to -yass High Proagatio elay lock to -yass Low Proagatio elay lock to Proagatio elay to + Proagatio elay Set to Proagatio elay eset to Trasitio Time Maximum lock Iut Frequecy. Ulimited Iut ise or Fall Time Miimum lock Pulse Width TPHL TPLH TPHL TPLH TPHL3 TPLH3 TPHL TPLH V = V,, 3 +5 o - s V = 5V,, 3 +5 o - 7 s V = V,, 3 +5 o - s V = 5V,, 3 +5 o - s V = V,, 3 +5 o - 3 s V = 5V,, 3 +5 o - s V = 5V,, 3 +5 o - 3 V = V,, 3 +5 o - 5 V = 5V,, 3 +5 o - TPLH V = 5V,, 3 +5 o - V = V,, 3 +5 o - 5 V = 5V,, 3 +5 o - TPHL V = V,, 3 +5 o - s V = 5V,, 3 +5 o - 5 s TTHL V = V,, 3 +5 o - s TTLH V = 5V,, 3 +5 o - s FL V = V,, 3 +5 o.5 - MHz V = 5V,, 3 +5 o.5 - MHz TW V = 5V,, 3 +5 o - s V = V,, 3 +5 o - 5 s V = 5V,, 3 +5 o - s Miimum Set Pulse Width TW V = 5V,, 3 +5 o - s V = V,, 3 +5 o - s V = 5V,, 3 +5 o - s Miimum eset Pulse Width Miimum Set ecovery Time TLE 3. ELETIL PEFOME HTEISTIS (otiued) PMETE SYMOL OITIOS OTES TEMPETUE TW V = 5V,, 3 +5 o - µs V = V,, 3 +5 o - µs V = 5V,, 3 +5 o -.5 µs TEM V = 5V,, 3 +5 o - 5 µs V = V,, 3 +5 o - µs V = 5V,, 3 +5 o -. µs Miimum eset ecovery TEM V = 5V,, 3 +5 o - 7 µs Time V = V,, 3 +5 o - 3 µs V = 5V,, 3 +5 o - µs Iut aacitace I y Iut, +5 o F OTES:. ll voltages refereced to device G.. The arameters listed o Table 3 are cotrolled via desig or rocess ad are ot directly tested. These arameters are characterized o iitial desig release ad uo desig chages which would affect these characteristics. 3. L = 5F, L = K, Iut T, TF < s. MI LIMITS MX UITS 7-39

5 Secificatios 53MS TLE. POST IITIO ELETIL PEFOME HTEISTIS LIMITS PMETE SYMOL OITIOS OTES TEMPETUE MI MX UITS Suly urret I V = V, VI = V or G, +5 o - 5 µ Threshold Voltage VTH V = V, ISS = -µ, +5 o V Threshold Voltage VT V = V, ISS = -µ, +5 o - ± V elta P Threshold Voltage VTP = V, I = µ, +5 o.. V P Threshold Voltage VTP = V, I = µ, +5 o - ± V elta Fuctioal F V = V, VI = V or G V = 3V, VI = V or G +5 o VOH > V/ Proagatio elay Time TPHL TPLH OTES:. ll voltages refereced to device G.. L = 5F, L = K, Iut T, TF < s. VOL < V/ V = 5V,, 3, +5 o -.35 x +5 o Limit 3. See Table for +5 o limit.. ead ad ecord V s TLE 5. U-I LIFE TEST ELT PMETES +5 o PMETE SYMOL ELT LIMIT Suly urret - MSI- I ±.µ Outut urret (Sik) IOL5 ± % x Pre-Test eadig Outut urret (Source) IOH5 ± % x Pre-Test eadig TLE. PPLILE SUGOUPS OFOME GOUP MIL-ST-3 METHO GOUP SUGOUPS E EO Iitial Test (Pre ur-i) % 5, 7, 9 I, IOL5, IOH5 Iterim Test (Post ur-i) % 5, 7, 9 I, IOL5, IOH5 Iterim Test (Post ur-i) % 5, 7, 9 I, IOL5, IOH5 P (ote ) % 5, 7, 9, eltas Iterim Test 3 (Post ur-i) % 5, 7, 9 I, IOL5, IOH5 P (ote ) % 5, 7, 9, eltas Fial Test % 5, 3,,,, Grou Samle 55,, 3, 7,,, 9,, Grou Subgrou -5 Samle 55,, 3, 7,,, 9,,, eltas Subgrous,, 3, 9,, Subgrou - Samle 55, 7, 9 Grou Samle 55,, 3,,, 9 Subgrous, 3 OTE:. 5% Parameteric, 3% Fuctioal; umulative for Static ad. TLE 7. TOTL OSE IITIO MIL-ST-3 TEST E EO OFOME GOUPS METHO PE-I POST-I PE-I POST-I Grou E Subgrou 55, 7, 9 Table, 9 Table 7-

6 Secificatios 53MS TLE. U-I IITIO TEST OETIOS FUTIO OPE GOU V 9V ± -.5V Static ur-i, 5, 3-3, -,, 5 ote Static ur-i ote yamic ur- I ote Irradiatio ote OTE:, 5, 3-3,, 7, 9-, - -,, -,, 5 9-,, 5, 3 3, 5, 3-3,, 7, 9-, - OSILLTO 5kHz 5kHz. Each i excet V ad G will have a series resistor of K ± 5%, V = V ±.5V. Each i excet V ad G will have a series resistor of 7K ± 5%; Grou E, Subgrou, samle size is dice/wafer, failures, V = V ±.5V Logic iagram * -YPSS V ESET * SET * S LOK * LIS IH 7 L FF5 *IPUTS POTETE Y MOS POTETIO ETWOK E F LE L L FF FF FF3 FF L S T OS * IH I * 3 T OUT * OUT * 5 OTE: f, S (5 ) x T 3T T FIGUE. G 7-

7 53MS Logic iagram (otiued) E F LIS L L FF9 FF FF FF FF7 FF FF OF EOE (TSMISSIO-GTE TEE LOGI) P EOE OUT 3 9 * * * * G 5 * MOO I ETIL FO FF3-, -, 7- ETIL FO FF, FF, FF, FF9, FF5 LE (LIS FO FF9 FF5) P P P P V P P L f e f e LE L FF a b b L FF, a c S LIS L FF9 d d c LIS L S FF5 FF: S SHOW EXEPT OT OUGHT OUT FF9: SME S FF EXEPT IS OUGHT OUT, GO TO TGf TGe ESP. FF, FF: ELETE TGe, TGf, IVf; FEE TO ; ELETE LE, LIS FF5: IVa IVd EOME -IPUT GTES, WITH E IPUTS S; FEE TO TGf TO TGe PEVIOUS IPUT; ELETE OUTPUT FIGUE. (otiued) 7-

8 53MS TUTH TLE I SET ESET LOK IH OS IH OUT OUT EOE OUT o hage dvace to ext State X X X o hage X o hage dvace to ext State = Low Level = High Level X = o t are Tyical Performace haracteristics OUTPUT LOW (SIK) UET (IOL) (m) MIET TEMPETUE (T ) = +5 o GTE-TO-SOUE VOLTGE (VGS) = 5V V 5V OUTPUT LOW (SIK) UET (IOL) (m) MIET TEMPETUE (T ) = +5 o GTE-TO-SOUE VOLTGE (VGS) = 5V V 5V 5 5 I-TO-SOUE VOLTGE (VS) (V) FIGUE. TYPIL OUTPUT LOW (SIK) UET HTEISTIS 5 5 I-TO-SOUE VOLTGE (VS) (V) FIGUE 3. MIIMUM OUTPUT LOW (SIK) UET HTEISTIS I-TO-SOUE VOLTGE (VS) (V) MIET TEMPETUE (T ) = +5 o GTE-TO-SOUE VOLTGE (VGS) = -5V -V -5V OUTPUT HIGH (SOUE) UET (IOH) (m) I-TO-SOUE VOLTGE (VS) (V) MIET TEMPETUE (T ) = +5 o GTE-TO-SOUE VOLTGE (VGS) = -5V -V -5V OUTPUT HIGH (SOUE) UET (IOH) (m) FIGUE. TYPIL OUTPUT HIGH (SOUE) UET HTEISTIS FIGUE 5. MIIMUM OUTPUT HIGH (SOUE) UET HTEISTIS 7-3

9 53MS Tyical Performace haracteristics (otiued) POPGTIO ELY TIME (tphl, tplh) (µs).5.5 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V V 5V POPGTIO ELY TIME (tphl, tplh) (µs) 3 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V V 5V LO PITE (L) (F) FIGUE. TYPIL POPGTIO ELY TIME S FUTIO OF LO PITE (LOK TO, -YPSS HIGH) LO PITE (L) (F) FIGUE 7. TYPIL POPGTIO ELY TIME S FUTIO OF LO PITE (LOK TO, -YPSS LOW) POPGTIO ELY TIME (tphl, tplh) (µs) MIET TEMPETUE (T ) = +5 o.5 SUPPLY VOLTGE (V) = 5V V.5 5V POPGTIO ELY TIME (tphl, tplh) (µs) MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V 5 V 5V 5 LO PITE (L) (F) FIGUE. TYPIL POPGTIO ELY TIME S FUTIO OF LO PITE (LOK TO, -YPSS HIGH) FEUEY EVITIO ( f) (%) MIET TEMPETUE (T ) = +5 o EXTEL ESISTE (E) = 5kΩ EXTEL PITE (X) = F S =, f = 79Hz S = kω, f = 59Hz SUPPLY VOLTGE (V) (V) FIGUE. TYPIL OSILLTO FEUEY EVITIO S FUTIO OF SUPPLY VOLTGE LO PITE (L) (F) FIGUE 9. TYPIL POPGTIO ELY TIME S FUTIO OF LO PITE ( TO + ) OSILLTO FEUEY (F) (KHz) 3 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = V f = 3tc T f vs tc T = F S = tc f vs T tc = 5kΩ S = kω EXTEL PITE (T) (F) 3 EXTEL ESISTE (tc) (kω) FIGUE. TYPIL OSILLTO FEUEY EVITIO S FUTIO OF TIME OSTT ESISTE PITE 7-

10 53MS Tyical Performace haracteristics (otiued) FEUEY EVITIO ( f) (%) tc = 5kΩ S = X = F 5V V 5V SUPPLY VOLTGE (V) = 5V V 5V FEUEY EVITIO ( f) (%) tc = 5kΩ E = kω X = F 5V V 5V SUPPLY VOLTGE (V) = 5V V 5V MIET TEMPETUE (T ) o FIGUE. TYPIL OSILLTO FEUEY EVITIO S FUTIO OF MIET TEMPETUE (S = ) PULSE WITH (µs) 3. MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V X = mω K 5K K 3 5 EXTEL PITE (X) (F) FIGUE. TYPIL PULSE WITH S FUTIO OF EXTEL PITE (V = 5V) MIET TEMPETUE (T ) o FIGUE 3. TYPIL OSILLTO FEUEY EVITIO S FUTIO OF MIET TEMPETUE (S = kω) PULSE WITH (µs) 3 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = V X = mω. kω 5kΩ kω 3 5 EXTEL PITE (X) (F) FIGUE 5. TYPIL PULSE WITH S FUTIO OF EXTEL PITE (V = V) PULSE WITH (µs) 3 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V X = mω kω 5kΩ kω. 3 5 EXTEL PITE (X) (F) FIGUE. TYPIL PULSE WITH S FUTIO OF EXTEL PITE (V = 5V) TSITIO TIME (tthl, ttlh) (s) 5 5 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V LO PITE (L) (F) V 5V FIGUE 7. TYPIL TSITIO TIME S FUTIO OF LO PITE 7-5

11 licatios 53MS Tyical Performace haracteristics (otiued) POWE ISSIPTIO (P) (µw) 5 3 MIET TEMPETUE (T ) = +5 o SUPPLY VOLTGE (V) = 5V. 3 PULSE IPUT FEUEY (khz) FIGUE. TYPIL YMI POWE ISSIPTIO S FUTIO OF IPUT PULSE FEUEY V 5V L = 5F L = 5F >K 9 SET ESET -YPSS IH 5 MOO I OS IH I V OUT OUT EOE OUT X X T -T +T -T 5 9MS V L OE OUT (L ) OUTPUT 9MS FIGUE 9. PPLITIO SHOWIG USE OF 9MS 53MS TO GET EOE PULSE LOK PULSES FTE ESET PULSE LOK kω SET ESET -YPSS IH MOO I OS IH I V EOE OUT OUT OUT t LOK L SET ESET -YPSS IH MOO I OS IH I V EOE OUT OUT OUT t FIGUE. TIME ITEVL OFIGUTIO USIG EXTE- L LOK; SET LOK IHIIT FUTIOS FIGUE. TIME ITEVL OFIGUTIO USIG EXTE- L LOK; ESET OUTPUT MOOSTLE TO HIEVE PULSE OUTPUT 7-

12 53MS licatios (otiued) V STT SET ESET -YPSS IH MOO I OS IH I OUT OUT EOE OUT FIGUE. TIME ITEVL OFIGUTIO USIG O- HIP OSILLTO ESET IPUT TO IITITE TIME ITEVL t S tc f.3 tc S tc f I Hz, I Ω, I F LOK ( ) ( ) ( ) 3µs MI OTE: SHE PULSE EPESETS EOE OUTPUT I MOOSTLE MOE. IF OUTPUT PULSE IS EUIE FULL OUTOW FTE EMOVL OF ESET PULSE, SEE FIGUE 9 FO USE OF 9MS FIGUE 3. TIMIG IGM Fuctioal lock iagram EOE OUT SELETIO TLE UME OF STGES I IVIE HI -YPSS = -YPSS = = Low Level = High Level SET ESET -YPSS OS IHIIT OS IHIIT LOGI I 3 OUT OUT 5 LOK 7 IHIIT LOK IHIIT LOGI = V = STGES - -YPSS LOGI IY SELET MOO I 9 5 STGES EOE 3 EOE OUT FIGUE. 7-7

53MS FUTIOL TEST SEUEE IPUTS OUTPUTS OMMETS EOE OUT I SET ESET -YPSS THU LL STEPS E I ESET MOE outer is i three -stage sectio i arallel mode First to trasitio of clock - - - 55 to trasitios are

13 53MS FUTIOL TEST SEUEE IPUTS OUTPUTS OMMETS EOE OUT I SET ESET -YPSS THU LL STEPS E I ESET MOE outer is i three -stage sectio i arallel mode First to trasitio of clock to trasitios are clocked i the couter The 55 to trasitio outer coverted back to stages i series mode. Set ad eset must be coected together ad simultaeously go from to I Switches to a outer iles from a all state to a all state Fuctioal Test Sequece Test Fuctio has bee icluded for the reductio of test time required to exercise all couter stages. This test fuctio divides the couter ito three -stage sectios ad 55 couts are loaded i each of the -stage sectios i arallel. ll fli-flos are ow at a. The couter is ow retured to the ormal stes i series cofiguratio. Oe more ulse is etered ito I which will cause the couter to rile from a all state to a all state. hi imesios ad Pad Layout ITESIL imesios i arethesis are i millimeters ad are derived from the basic ich dimesios as idicated. Grid graduatios are i mils ( -3 ich). METLLIZTIO: Thickess: kå kå, L. PSSIVTIO:.kÅ - 5.kÅ, Silae O PS:. iches X. iches MI IE THIKESS:.9 iches -. iches ll Itersil semicoductor roducts are maufactured, assembled ad tested uder ISO9 quality systems certificatio. Itersil roducts are sold by descritio oly. Itersil ororatio reserves the right to make chages i circuit desig ad/or secificatios at ay time without otice. ccordigly, the reader is cautioed to verify that data sheets are curret before lacig orders. Iformatio furished by Itersil is believed to be accurate ad reliable. However, o resosibility is assumed by Itersil or its subsidiaries for its use; or for ay ifrigemets of atets or other rights of third arties which may result from its use. o licese is grated by imlicatio or otherwise uder ay atet or atet rights of Itersil or its subsidiaries. For iformatio regardig Itersil ororatio ad its roducts, see web site htt://

14 This datasheet has bee dowloaded from: atasheets for electroic comoets.

DATASHEET CD4030BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad Exclusive-OR Gate. FN3305 Rev 0.

DATASHEET CD4030BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad Exclusive-OR Gate. FN3305 Rev 0. DATASHEET CD3BMS CMOS Quad Exclusive-OR Gate FN335 Rev. Features Piout High Voltage Tye (V Ratig) Medium-Seed Oeratio - tphl, tplh = 5s (ty) at =, CL = 5F CD3BMS TOP VIEW 1% Tested for Quiescet Curret