DATASHEET CD4030BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad Exclusive-OR Gate. FN3305 Rev 0.
|
|
- Penelope Donna Morris
- 5 years ago
- Views:
Transcription
1 DATASHEET CD3BMS CMOS Quad Exclusive-OR Gate FN335 Rev. Features Piout High Voltage Tye (V Ratig) Medium-Seed Oeratio - tphl, tplh = 5s (ty) at =, CL = 5F CD3BMS TOP VIEW 1% Tested for Quiescet Curret at V A 1 1 Stadardized Symmetrical Outut Characteristics B 13 H 5V, ad 15V Parametric Ratigs J = A B 3 1 G Maximum Iut Curret Of 1 A at 18V Over Full Package-Temerature Rage; - 1A at 18V ad +5 o C K = C D C M = G H L = E F Noise Margi (Over Full Package Temerature Rage): - 1V at = 5V - V at = -.5V at = 15V D F E Meets All Requiremets of JEDEC Tetative Stadard No. 13B, Stadard Secificatios for Descritio of B Series CMOS Devices Fuctioal Diagram Alicatios Eve ad Odd-Parity Geerators ad Checkers A B 1 3 J Logical Comarators Adders/Subtractors C D 5 K Geeral Logic Fuctios Descritio E F L The CD3BMS tyes cosist of four ideedet Exclusive-OR gates. The CD3BMS rovides the system desiger with a meas for direct imlemetatio of the Exclusive-OR fuctio. G H M The CD3BMS is sulied i these 1-lead outlie ackages: Braze Seal DIP HH Frit Seal DIP H1B Ceramic Flatack H3W J = A B K = C D = 7 = 1 M = G H L = E F FN335 Rev. Page 1 of 7
2 CD3BMS Absolute Maximum Ratigs DC Suly Voltage Rage, () V to +V (Voltage Refereced to Termials) Iut Voltage Rage, All Iuts V to +.5V DC Iut Curret, Ay Oe Iut 1mA Oeratig Temerature Rage to +15 o C Package Tyes D, F, K, H Storage Temerature Rage (TSTG) o C to +15 o C Lead Temerature (Durig Solderig) o C At Distace 1/1 1/3 Ich (1.59mm.79mm) from case for 1s Maximum Reliability Iformatio Thermal Resistace ja jc Ceramic DIP ad FRIT Package o C/W o C/W Flatack Package o C/W o C//W Maximum Package Power Dissiatio (PD) at +15 o C For TA = to +1 o C (Package Tye D, F, K) mW For TA = +1 o C to +15 o C (Package Tye D, F, K)..... Derate Liearity at 1mW/ o C to mw Device Dissiatio er Outut Trasistor mW For TA = Full Package Temerature Rage (All Package Tyes) Juctio Temerature o C TABLE 1. DC ELECTRICAL PERFORMANCE GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Suly Curret IDD = V, VIN = or GND 1 +5 o C - A +15 o C - A = 18V, VIN = or GND 3 - A Iut Leakage Curret IIL VIN = or GND = 1 +5 o C -1 - A +15 o C -1 - A = 18V A Iut Leakage Curret IIH VIN = or GND = 1 +5 o C - 1 A +15 o C - 1 A = 18V 3-1 A Outut Voltage VOL15 = 15V, No Load 1,, 3 +5 o C, +15 o C, - 5 mv Outut Voltage VOH15 = 15V, No Load (Note 3) 1,, 3 +5 o C, +15 o C, V Outut Curret (Sik) IOL5 = 5V, VOUT =.V 1 +5 o C.53 - ma Outut Curret (Sik) IOL1 =, VOUT =.5V 1 +5 o C 1. - ma Outut Curret (Sik) IOL15 = 15V, VOUT = 1.5V 1 +5 o C ma Outut Curret (Source) IOH5A = 5V, VOUT =.V 1 +5 o C ma Outut Curret (Source) IOH5B = 5V, VOUT =.5V 1 +5 o C ma Outut Curret (Source) IOH1 =, VOUT = 9.5V 1 +5 o C ma Outut Curret (Source) IOH15 = 15V, VOUT = 13.5V 1 +5 o C ma N Threshold Voltage VNTH =, ISS = -1 A 1 +5 o C V P Threshold Voltage VPTH = V, IDD = 1 A 1 +5 o C.7.8 V Fuctioal F =.8V, VIN = or GND 7 +5 o C VOH > VOL < V = V, VIN = or GND 7 +5 o C / / = 18V, VIN = or GND 8A +15 o C = 3V, VIN = or GND 8B Iut Voltage Low (Note ) VIL = 5V, VOH >.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, V Iut Voltage High (Note ) Iut Voltage Low (Note ) Iut Voltage High (Note ) VIH = 5V, VOH >.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, V VIL VIH = 15V, VOH > 13.5V, VOL < 1.5V = 15V, VOH > 13.5V, VOL < 1.5V 1. All voltages refereced to device GND, 1% testig beig imlemeted.. Go/No Go test with limits alied to iuts. 1,, 3 +5 o C, +15 o C, - V 1,, 3 +5 o C, +15 o C, 11 - V 3. For accuracy, voltage is measured differetially to. Limit is.5v max. FN335 Rev. Page of 7
3 CD3BMS TABLE. AC ELECTRICAL PERFORMANCE GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1, ) SUBGROUPS TEMPERATURE MIN MAX UNITS Proagatio Delay TPHL = 5V, VIN = or GND 9 +5 o C - 8 s TPLH 1, o C, s Trasitio Time TTHL = 5V, VIN = or GND 9 +5 o C - s TTLH 1, o C, - 7 s 1. CL = 5F, RL = K, Iut TR, TF < s.. ad +15 o C limits guarateed, 1% testig beig imlemeted. TABLE 3. ELECTRICAL PERFORMANCE PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Suly Curret IDD = 5V, VIN = or GND 1,, +5 o C - 1 A +15 o C - 3 A =, VIN = or GND 1,, +5 o C - A +15 o C - A = 15V, VIN = or GND 1,, +5 o C - A +15 o C - 1 A Outut Voltage VOL = 5V, No Load 1, +5 o C, +15 o C, - 5 mv Outut Voltage VOL =, No Load 1, +5 o C, +15 o C, Outut Voltage VOH = 5V, No Load 1, +5 o C, +15 o C, Outut Voltage VOH =, No Load 1, +5 o C, +15 o C, - 5 mv.95 - V V Outut Curret (Sik) IOL5 = 5V, VOUT =.V 1, +15 o C.3 - ma. - ma Outut Curret (Sik) IOL1 =, VOUT =.5V 1, +15 o C.9 - ma 1. - ma Outut Curret (Sik) IOL15 = 15V, VOUT = 1.5V 1, +15 o C. - ma. - ma Outut Curret (Source) IOH5A = 5V, VOUT =.V 1, +15 o C ma - -. ma Outut Curret (Source) IOH5B = 5V, VOUT =.5V 1, +15 o C ma - -. ma Outut Curret (Source) IOH1 =, VOUT = 9.5V 1, +15 o C ma ma Outut Curret (Source) IOH15 =15V, VOUT = 13.5V 1, +15 o C - -. ma - -. ma Iut Voltage Low VIL =, VOH > 9V, VOL < 1V Iut Voltage High VIH =, VOH > 9V, VOL < 1V Proagatio Delay TPHL TPLH 1, +5 o C, +15 o C, 1, +5 o C, +15 o C, - 3 V 7 - V = 1,, 3 +5 o C - 13 s = 15V 1,, 3 +5 o C - 1 s FN335 Rev. Page 3 of 7
4 CD3BMS TABLE 3. ELECTRICAL PERFORMANCE (Cotiued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE Trasitio Time TTHL = 1,, 3 +5 o C - 1 s TTLH = 15V 1,, 3 +5 o C - 8 s Iut Caacitace CIN Ay Iut 1, +5 o C F 1. All voltages refereced to device GND.. The arameters listed o Table 3 are cotrolled via desig or rocess ad are ot directly tested. These arameters are characterized o iitial desig release ad uo desig chages which would affect these characteristics. 3. CL = 5F, RL = K, Iut TR, TF < s. MIN MAX UNITS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Suly Curret IDD = V, VIN = or GND 1, +5 o C A N Threshold Voltage VNTH =, ISS = -1 A 1, +5 o C V N Threshold Voltage VTN =, ISS = -1 A 1, +5 o C - 1 V Delta P Threshold Voltage VTP = V, IDD = 1 A 1, +5 o C..8 V P Threshold Voltage VTP = V, IDD = 1 A 1, +5 o C - 1 V Delta Fuctioal F = 18V, VIN = or GND = 3V, VIN = or GND 1 +5 o C VOH > / Proagatio Delay Time TPHL TPLH 1. All voltages refereced to device GND.. CL = 5F, RL = K, Iut TR, TF < s. VOL < / = 5V 1,, 3, +5 o C x +5 o C Limit 3. See Table for +5 o C limit.. Read ad Record V s TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 O C PARAMETER SYMBOL DELTA LIMIT Suly Curret - MSI-1 IDD. A Outut Curret (Sik) IOL5 % x Pre-Test Readig Outut Curret (Source) IOH5A % x Pre-Test Readig TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Iitial Test (Pre Bur-I) 1% 5 1, 7, 9 IDD, IOL5, IOH5A Iterim Test 1 (Post Bur-I) 1% 5 1, 7, 9 IDD, IOL5, IOH5A Iterim Test (Post Bur-I) 1% 5 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 5 1, 7, 9, Deltas Iterim Test 3 (Post Bur-I) 1% 5 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 5 1, 7, 9, Deltas Fial Test 1% 5, 3, 8A, 8B, 1, 11 Grou A Samle 55 1,, 3, 7, 8A, 8B, 9, 1, 11 FN335 Rev. Page of 7
5 CD3BMS TABLE. APPLICABLE SUBGROUPS (Cotiued) CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Grou B Subgrou B-5 Samle 55 1,, 3, 7, 8A, 8B, 9, 1, 11, Deltas Subgrous 1,, 3, 9, 1, 11 Subgrou B- Samle 55 1, 7, 9 Grou D Samle 55 1,, 3, 8A, 8B, 9 Subgrous 1, 3 NOTE: 1. 5% Parameteric, 3% Fuctioal; Cumulative for Static 1 ad. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS MIL-STD-883 METHOD TEST READ AND RECORD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Grou E Subgrou 55 1, 7, 9 Table 1, 9 Table TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND 9V -.5V Static Bur-I 1 3,, 1, 11 1,, 5-9, 1, 13 1 Note 1 Static Bur-I Note 1 Dyamic Bur- I Note 1 Irradiatio Note NOTE: 3,, 1, ,, 5,, 8, 9, 1-1 OSCILLATOR 5kHz 5kHz ,, 1, 11,, 9, 13 1, 5, 8, 1 3,, 1, ,, 5,, 8, 9, Each i excet ad GND will have a series resistor of 1K 5%, = 18V.5V. Each i excet ad GND will have a series resistor of 7K 5%; Grou E, Subgrou, samle size is dice/wafer, failures, =.5V Schematic Diagram TRUTH TABLE FOR 1 OF INDENTICAL GATES B* (5, 9, 1) 1(, 8, 13) A* J 3(, 1, 11) A B J = High Level = Low Level *INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 1. 1 OF IDENTICAL GATES FN335 Rev. Page 5 of 7
6 CD3BMS Tyical Performace Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT TRANSITION TIME (tthl, ttlh) (s) 15 SUPPLY VOLTAGE () = 5V 1 15V LOAD CAPACITANCE (CL) (F) PROPAGATION DELAY TIME (tphl, tplh) (s) 3 SUPPLY VOLTAGE () = 5V 1 15V 8 LOAD CAPACITANCE (CL) (F) 1 FIGURE. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE FN335 Rev. Page of 7
7 CD3BMS Tyical Performace Characteristics (Cotiued) PROPAGATION DELAY TIME (tphl, tplh) (s) 3 1 LOAD CAPACITANCE (CL) = 5F SUPPLY VOLTAGE () (V) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNC- TION OF SUPPLY VOLTAGE POWER DISSIPATION PER GATE (PD) ( W) SUPPLY VOLTAGE () = 15V V LOAD CAPACITANCE 1 CL = 5F CL = 15F INPUT FREQUENCY (fi) (khz) FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY Chi Dimesios ad Pad Layout METALLIZATION: Thickess: 11kÅ 1kÅ, AL. PASSIVATION: 1.kÅ - 15.kÅ, Silae BOND PADS:. iches X. iches MIN DIE THICKNESS:.198 iches -.18 iches Dimesios i aretheses are i millimeters ad are derived from the basic ich dimesios as idicated. Grid graduatios are i mils (1-3 ich) Coyright Itersil Americas LLC All Rights Reserved. All trademarks ad registered trademarks are the roerty of their resective owers. For additioal roducts, see Itersil roducts are maufactured, assembled ad tested utilizig ISO91 quality systems as oted i the quality certificatios foud at Itersil roducts are sold by descritio oly. Itersil may modify the circuit desig ad/or secificatios of roducts at ay time without otice, rovided that such modificatio does ot, i Itersil's sole judgmet, affect the form, fit or fuctio of the roduct. Accordigly, the reader is cautioed to verify that datasheets are curret before lacig orders. Iformatio furished by Itersil is believed to be accurate ad reliable. However, o resosibility is assumed by Itersil or its subsidiaries for its use; or for ay ifrigemets of atets or other rights of third arties which may result from its use. No licese is grated by imlicatio or otherwise uder ay atet or atet rights of Itersil or its subsidiaries. For iformatio regardig Itersil Cororatio ad its roducts, see FN335 Rev. Page 7 of 7
CD4070 CD4077 CMOS Quad Exclusive OR and Exclusive NOR Gates
CD7 CD77 CMOS Quad Exclusive OR ad Exclusive NOR Gates Features High Voltage Tyes (V Ratig) Piouts CD7BMS TOP VIEW CD7BMS - Quad Exclusive OR Gate CD77BMS - Quad Exclusive NOR Gate Medium Seed Oeratio
More informationDATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter
DATASHEET CD19BMS CMOS Quad Low-to-High Voltage Level Shifter Features High Voltage Type (V Rating) Independence of Power Supply Sequence Considerations - can Exceed - Input Signals can Exceed Both and
More informationDATASHEET CD4014BMS, CD4021BMS. Description. Features. Applications: Functional Diagram. Pinout. CMOS 8-Stage Static Shift Registers
ATASHEET C1BMS, C1BMS CMOS -Stage Static Shift Registers Features High Voltage Tyes (V Ratig) Medium Seed Oeratio 1MHz (Ty.) Clock Rate at V-VSS = V Fully Static Oeratio Master-Slave Fli-Flos lus Outut
More informationDATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers
DATASHEET CD9BMS CMOS Quad -Input NAND Schmitt Triggers FN Rev. December 199 Features High Voltage Types (V Rating) Schmitt Trigger Action on Each Input With No External Components Hysteresis Voltage Typically.9V
More informationDATASHEET CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS. Features. Pinouts. Description. CMOS NOR Gate. FN3289 Rev 0.00 Page 1 of 9.
TST 000MS, 00MS, 00MS, 0MS MOS NOR ate N Rev 0.00 November eatures Piouts igh-voltage Tyes (0V Ratig) Proagatio elay Time = 0s (ty.) at L = 0, = V N 000MS TOP VIW uffered Iuts ad Oututs N Stadard Symmetrical
More informationDATASHEET CD4073BMS, CD4081BMS, CD4082BMS. Features. Pinout. Description. CMOS AND Gate. FN3324 Rev 1.00 Page 1 of 11. October FN3324 Rev 1.
TST 0MS, 0MS, 0MS MOS N ate eatures igh-voltage Tyes (0V Ratig) 0MS Trile -Iut N ate (No loger available or suorted) 0MS Quad -Iut N ate 0MS ual -Iut N ate (No loger available or suorted) Medium Seed Oeratio:
More informationNAND R/S - CD4044BMS Q VDD
DATASHT CD0BMS, CD0BMS CMOS Quad State R/S Latches FN Rev 0.00 December Features High Voltage Types (0V Rating) Quad NOR R/S Latch- CD0BMS Quad NAND R/S Latch - CD0BMS State Outputs with Common Output
More informationDATASHEET CD4071BMS, CD4072BMS, CD4075BMS. Features. Pinout. Description. CMOS OR Gate. FN3323 Rev 0.00 Page 1 of 11. December FN3323 Rev 0.
MOS OR ate NOT ROMMN OR NW SINS NO ROMMN RPLMNT cotact our Techical Suort eter at --INTRSIL or www.itersil.com/tsc TST N Rev 0.00 eatures igh-voltage Tyes (0V Ratig) 0MS Quad -Iut OR ate 0MS ual -Iut OR
More informationCD4071, CD4072 CD4075
, MOS OR ate eatures igh-voltage Tyes (V Ratig) MS Quad -Iut OR ate MS ual -Iut OR ate MS Trile -Iut OR ate Medium Seed Oeratio: - tpl, tpl = s (ty) at V % Tested for Quiescet urret at V Maximum Iut urret
More informationCD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
CD010BMS, CD011BMS, CD01BMS, CD013BMS December 199 File Number 3358 CMOS Sychroous Programmable -Bit Couters CD010BMS, CD011BMS, CD01BMS ad CD013BMS are -bit sychroous rogrammable couters. he EAR fuctio
More informationCD4000BMS, CD4001BMS CD4002BMS, CD4025BMS
000MS, 00MS 00MS, 0MS November MOS NOR ate eatures Piouts igh-voltage Tyes (0V Ratig) Proagatio elay Time = 0s (ty.) at L = 0, = V N 000MS TOP VIW uffered Iuts ad Oututs N Stadard Symmetrical Outut haracteristics
More informationCD40104BMS, CD40194BMS CMOS 4-Bit Bidirectional Universal Shift Register
ecember 199 Features High Voltage Tye (V Ratig) Medium Seed f = 1MHz (ty.) at V = 1V Fully Static Oeratio Sychroous Parallel or Serial Oeratio Three State Oututs (C1MS) Asychroous Master Reset (C19MS)
More informationDATASHEET CD4020BMS, CD4024BMS, CD4040BMS. Pinouts. Features. Applications. Description. CMOS Ripple-Carry BinaryCounter/Dividers
DATASHEET CD00BMS, CD0BMS, CD00BMS CMOS ipple-carry BinaryCounter/Dividers FN3300 ev 1.00 Features Pinouts High Voltage Types (0V ating) Medium Speed Operation Fully Static Operation Buffered Inputs and
More informationDATASHEET CD4015BMS. Pinout. Features. Functional Diagram. Applications. Description
ATASHEET CBMS CMOS ual -Stage Static Shift egister With Serial Input/Parallel Output FN39 ev. Features Pinout High-Voltage Type (V ating) Medium Speed Operation MHz (typ.) Clock ate at V - VSS = OCK B
More informationDATASHEET CD4555BMS, CD4556BMS. Features. Pinouts. Applications. Functional Diagrams. Description. CMOS Dual Binary to 1 of 4Decoder/Demultiplexers
DTSHT CD555MS, CD556MS CMOS Dual inary to of Decoder/Demultiplexers FN336 Rev 0.00 Features High Voltage Type (0V Rating) Pinouts CD556MS TOP VIW CD555MS: Outputs High on Select CD556MS: Outputs Low on
More informationCD4536BMS. CMOS Programmable Timer. Description. Features. Functional Diagram. Pinout. December 1992
53MS ecember 99 Features High Voltage Tye (V atig) Fli-Flo Stage - outs from to Last Stages Selectable by Select ode yass Iut llows yassig First Stages O-hi Oscillator Provisio lock Ihibit Iut Schmitt
More informationDATASHEET CD4017BMS, CD4022BMS. Features. Applications. Pinouts. Functional Diagrams. CMOS Counter/Dividers. FN3297 Rev 0.00 Page 1 of 10.
ATASHEET BMS, BMS MOS ounter/ividers BMS - ecade ounter with ecoded Outputs BMS - Octal ounter with 8 ecoded Outputs BMS and BMS are -stage and -stage Johnson counters having and 8 decoded outputs, respectively.
More informationDATASHEET CD4049UBMS. Features. Applications. Pinout. Functional Diagram. Schematic. CMOS Hex Buffer/Converter. FN3315 Rev 1.
DTSHEET CD09UBMS CMOS Hex Buffer/Converter The CD09UBMS is an inverting hex buffer and features logic level conversion using only one supply (voltage (VCC). The input signal high level (VIH) can exceed
More informationSN54HC682, SN74HC682 8-BIT MAGNITUDE COMPARATORS
SCLS0C MARCH 9 REVISED MAY 99 Compare Two -Bit Words 00-kΩ Pullup Resistors Are on the Q Inputs Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
More informationFeatures OUT A NC 27 NC IN 8A IN 16 IN 7A IN 15 IN 6A IN 14 IN 5A IN 13 IN 4A IN 12 IN 3A IN 11 IN 2A IN 10 IN 1A IN 9 ENABLE GND ADDRESS A0 V REF
DATASHEET HS-0RH, HS-0RH Radiation Hardened Single /Differential Channel CMOS Analog Multiplexers with Active Overvoltage rotection F Rev..00 The HS-0RH and HS-0RH are radiation hardened analog multiplexers
More informationDATASHEET HS-0548RH, HS-0549RH. Features. Applications. Pinouts. Ordering Information
DATASHEET HS-0RH, HS-0RH Radiation Hardened Single /Differential Channel CMOS Analog Multiplexers with Active Overvoltage rotection F Rev.00 August 00 The HS-0RH and HS-0RH are radiation hardened analog
More informationQuad 2-input NAND gate
Quad 2-input NAND gate BU40B / BU40BF / BU40BF The BU40B, BU40BF, and BU40BF are dual-input positive logic NAND gates. Four circuits are contained on a single chip. An inverter-based buffer has been added
More informationDATASHEET HI-506A, HI-507A, HI-508A, HI-509A. Features. Applications
DATASHEET HI-506A, HI-507A, HI-508A, HI-509A 16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage rotection F3143 Rev.6.00 The HI-506A, HI-507A,
More informationSN54HC20, SN74HC20 DUAL 4-INPUT POSITIVE-NAND GATES
SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic
More informationDATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer
DATASHEET HI-518 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer F3147 Rev 4.00 The Hl-518 is a monolithic, dielectrically isolated, high speed, high performance CMOS analog multiplexer.
More informationF3 F F1 GND
4-BIT ARITHMETIC LOGIC UNIT The MC54/74F82 performs three arithmetic and three logic operatio on two 4-bit words, A and B. Two additional elect input codes force the Function outputs LOW or HIGH. An Overflow
More informationYuZhuo Fu Office location:417 room WeiDianZi building,no 800 DongChuan road,minhang Campus
Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio Digital IC outlie CMOS at a glace CMOS static behavior
More informationDigital Integrated Circuits. Inverter. YuZhuo Fu. Digital IC. Introduction
Digital Itegrated Circuits Iverter YuZhuo Fu Itroductio outlie CMOS at a glace CMOS static behavior CMOS dyamic behavior Power, Eergy, ad Eergy Delay Persective tech. /48 outlie CMOS at a glace CMOS static
More informationDigital Integrated Circuits
Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio outlie CMOS at a glace CMOS static behavior CMOS dyamic
More informationDATASHEET HS Features. Pinouts. ARINC 429 Bus Interface Line Driver Circuit. FN2963 Rev 3.00 Page 1 of 7. May 30, FN2963 Rev 3.
DATASHEET ARI 429 Bus Interface Line Driver Circuit FN2963 Rev 3.00 The is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of ARI 429. This device
More informationRegenerative Property
DESIGN OF LOGIC FAMILIES Some desirable characteristics to have: 1. Low ower dissiatio. High oise margi (Equal high ad low margis) 3. High seed 4. Low area 5. Low outut resistace 6. High iut resistace
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE) tpd = 24 ns (TYP.
M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE). HIGH SPEED tpd = 24 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
More informationFeatures Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
More informationSN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR 1-OF-10 DECODER/ DRIVER OPEN-COLLECTOR FAST AND LS TTL DATA 5-240
-OF-0 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. tpd = 13 ns (TYP.
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. HIGH SPEED tpd = 13 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC133 M74HC INPUT NAND GATE. tpd = 13 ns (TYP.) at VCC =5V
M54HC133 M74HC133 13 INPUT NAND GATE. HIGH SPEED tpd = 13 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
More informationHigh Speed Quad SPST CMOS Analog Switch
High Speed Quad SPST CMOS Analog Switch HI-21HS/883 The HI-21HS/883 is a monolithic CMOS analog switch featuring very fast switching speeds and low ON resistance. This integrated circuit consists of four
More informationMORE TUTORIALS FOR VERILOG DIGITAL ELECTRONICS SYSTEM DESIGN HOMEWORK ASSIGNMENTS DATASHEETS FOR PARTS 10/3/2018
//8 DIGITA EECTRONICS SYSTEM DESIGN FA 8 PROFS. IRIS BAHAR & ROD BERESFORD OCTOBER, 8 ECTURE 9: CMOS TRANSIENT BEHAIOR MORE TUTORIAS FOR ERIOG O the course website you ca fid some useful liks to additioal
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC85 M74HC85 4-BIT MAGNITUDE COMPARATOR. tpd = 22 ns (TYP.) at VCC =5V
M54HC85 M74HC85 4-BIT MAGNITUDE COMPARATOR. HIGH SPEED tpd = 22 ns (TYP.) at VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. tpd = 15 ns (TYP.
M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. HIGH SPEED tpd = 15 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY
More informationSEMICONDUCTOR TECHNICAL DATA
SEICONDUCTOR TECHNICAL DATA The is a COS look ahead carry generator capable of anticipating a carry across four binary adders or groups of adders. The device is cascadable to perform full look ahead across
More informationSN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops.
More informationLecture #25. Amplifier Types
ecture #5 Midterm # formatio ate: Moday November 3 rd oics to be covered: caacitors ad iductors 1 st -order circuits (trasiet resose) semicoductor material roerties juctios & their alicatios MOSFEs; commo-source
More informationP-MOS Device and CMOS Inverters
Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short
More informationMM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
More informationHCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIVER HCC/HCF4543B
HCC4543B HCF4543B BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIER DISPLAY BLANKING OF ALL ILLEGAL INPUT COMBINATIONS LATCH STORAGE OF CODE CAPABILITY OF DRIING TWO LOW POWER TTL LOADS, TWO HTL LOADS, OR ONE LOW
More informationDATASHEETS FOR PARTS DIGITAL ELECTRONICS SYSTEM DESIGN NMOS I-V SUMMARY EXAM SCHEDULE 10/5/2018. cutoff V V. linear.
//8 IGIT EECTRONICS SYSTEM ESIGN F 8 PROFS. IRIS HR & RO ERESFOR OCTOER, 8 ECTURE : CMOS TRNSIENT EHIOR TSHEETS FOR PRTS ll arts rovided for you i our kits come with datasheets Pi layout i ackage Schematic
More informationMM74C14 Hex Schmitt Trigger
MM74C14 Hex Schmitt Trigger General Description The MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. The
More informationPO54G74A, PO74G74A. Pin Configuration. Logic Block Diagram. Pin Description. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: 1D 2
DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS FEATURES:. Patented technology. Specified From 0 C to 12 C, C to 12 C. Operating frequency is faster than 600MHz. VCC Operates from 1.6V to 3.6V. Propagation
More informationDATASHEET. Features. Applications EL7155. High Performance Pin Driver. FN7279 Rev 3.00 Page 1 of 10. October 24, FN7279 Rev 3.
DATASHEET EL71 High Performance Pin Driver FN779 Rev 3. The EL71 high performance pin driver with 3-state is suited to many ATE and level-shifting applications. The 3.A peak drive capability makes this
More informationTC74HC373AP,TC74HC373AF,TC74HC373AFW
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC373AP/AF/AFW TC74HC373AP,TC74HC373AF,TC74HC373AFW Octal D-Type Latch with 3-State Output The TC74HC373A is a high speed CMOS OCTAL LATCH
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM MAY 1999 FEATURES High-speed access time: 10, 12, 15, 20, 25 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
More informationMM74C14 Hex Schmitt Trigger
MM74C14 Hex Schmitt Trigger General Description The MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. The
More informationRM3283. Dual ARINC 429 Line Receiver
Dual RINC 9 Line Receiver www.fairchildsemi.com Features Two separate analog receiver channels Converts RINC 9 levels to serial data Built-in TTL compatible complete channel test inputs TTL and CMOS compatible
More informationSEMICONDUCTOR TECHNICAL DATA
SEICONDUCTOR TECHNICL DT The C7 is a static clocked serial shift register whose length may be programmed to be any number of bits between and. The number of bits selected is equal to the sum of the subscripts
More informationDATASHEET HI-390. Features. Ordering Information. Pinout Switch States shown for a Logic 1 Input. Applications. Functional Diagram
HI-39 Dual SPDT CMOS nalog Switch NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLCEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DTSHEET FN7 Rev 1. ugust The Hl-39
More information. HIGH SPEED .LOW POWER DISSIPATION .OUTPUT DRIVE CAPABILITY M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING) t PD = 16 ns (TYP.
M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING). HIGH SPEED t PD = 16 ns (TYP.) at V CC =5V.LOW POWER DISSIPATION ICC =4µAATTA =25 C.OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS
More informationMM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
More informationEEC 118 Lecture #4: CMOS Inverters. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #4: CMOS Iverters ajeeva Amirtharajah Uiversity of Califoria, Davis Jeff Parhurst Itel Cororatio Outlie eview: Iverter Trasfer Characteristics Lecture 3: Noise Margis, ise & Fall Times,
More informationSN54HC153, SN74HC153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
Permit Multiplexing from n Lines to One Line Perform Parallel-to-Serial Conversion Strobe (Enable) Line Provided for Cascading (N Lines to n Lines) Package Options Include Plastic Small-Outline (D), Thin
More informationHIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
DESCRIPTION The / optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline
More informationAVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) TL7702ACD TL7715ACD TL7702ACP TL7715ACP TL7702ACY TL7715ACY
Power-On Reset Generator Automatic Reset Generation After Voltage Drop Wide Supply Voltage Range Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally
More informationNTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC4511 M74HC4511 BCD TO 7 SEGMENT LATCH/DECODER DRIVER. tpd = 28 ns (TYP.
M54HC4511 M74HC4511 BCD TO 7 SEGMENT LATCH/DECODER DRIVER. HIGH SPEED tpd = 28 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
More information74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
More informationTC74HC148AP,TC74HC148AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC148AP,TC74HC148AF 8-to-3 Line Priority Encoder The TC74HC148A is a high speed CMOS 8-to-3 LINE ENCODER fabricated with silicon gate C2MOS
More informationMM54HC08 MM74HC08 Quad 2-Input AND Gate
MM54HC08 MM74HC08 Quad 2-Input AND Gate General Description These AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
More informationNTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
More informationFeatures. Pinout. PART NUMBER PART MARKING TAPE & REEL PKG PKG. DWG. # EL7156CNZ (Note) (No longer available, recommended replacement: EL7156CSZ)
DATASHEET EL76 High Performance Pin Driver The EL76 high performance pin driver with three-state is suited to many ATE and level-shifting applications. The 3.A peak drive capability makes this part an
More information1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
More informationMM74C906 Hex Open Drain N-Channel Buffers
Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel
More informationCD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING) tpd = 11 ns (TYP.
M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING). HIGH SPEED tpd = 11 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
More informationMM74HC157 Quad 2-Input Multiplexer
Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and
More informationSN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SNH8, SNH8 -LINE TO 8-LINE DEODERS/DEMULTIPLEXERS Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify ascading and/or Data Reception
More informationMM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
More informationMM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
More informationHCC40147B HCF40147B 10 TO 4 LINE BCD PRIORITY ENCODER
HCC40147B HCF40147B 10 TO 4 LINE BCD PRIORITY ENCODER ENCODES 10 LINE TO 4 LINE BCD ACTIE LOW INPUTS AND OUTPUTS STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERIZATION 100 % TESTED FOR QUIESCENT CURRENT. AT
More informationFeatures. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
More informationIS61C K x 16 HIGH-SPEED CMOS STATIC RAM
ISC K x HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 0,,, and 0 ns CMOS low power operation 0 mw (typical) operating 0 µw (typical) standby TTL compatible interface levels Single V ± 0%
More informationDATASHEET CA3162. Features. Description. Ordering Information. Pinout. Functional Block Diagram. A/D Converters for 3-Digit Display
DATASHEET CA A/D Converters for -Digit Display Features Dual Slope A/D Conversion Multiplexed BCD Display Ultra Stable Internal Band Gap Voltage Reference Capable of Reading 99mV Below Ground with Single
More informationTC74HC74AP,TC74HC74AF,TC74HC74AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC74AP/AF/AFN TC74HC74AP,TC74HC74AF,TC74HC74AFN Dual D-Type Flip Flop Preset and Clear The TC74HC74A is a high speed CMOS D FLIP FLOP fabricated
More informationBCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
More informationMM74HC32 Quad 2-Input OR Gate
Quad 2-Input OR Gate General Description The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
More informationMM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
More informationHN58C256 Series word 8-bit Electrically Erasable and Programmable CMOS ROM
32768-word 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-092G (Z) Rev. 7.0 Nov. 29, 1994 Description The Hitachi HN58C256 is a electrically erasable and programmable ROM organized as 32768-word
More informationCD4510BMS, CD4516BMS. CMOS Presettable Up/Down Counters. Features. Applications. Functional Diagram. Pinout. Data Sheet December 1992 File Number 3338
Data Sheet December File Number MOS resettable Up/Down ounters DBMS resettable BD Up/Down ounter and the DBMS resettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with
More informationMM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
More informationIS61LV K x 16 LOW VOLTAGE CMOS STATIC RAM
ISLV K x LOW VOLTAGE CMOS STATIC RAM FEATURES High-speed access time: 0,,, and 0 ns CMOS low power operation 0 mw (typical) operating 0 µw (typical) standby TTL compatible interface levels Single.V ± 0%
More informationPRELIMINARY SPECIFICATION
Positive Adjustable V tor AVAILABLE AS MILITARY / SPACE SPECIFICATIONS SMD 5962-99517 pending Radiation Tolerant MIL-STD-88, 1.2.1 QML pending FEATURES Guaranteed 0.5A Output Current Radiation Guaranteed
More informationCD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
More informationSN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
Contain Four Flip-Flops With Double-ail Outputs Buffered Clock and Direct Clear Inputs Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline
More informationMM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
More informationSN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B DECEMBER 1982 REVISED MAY 1997
Package Optio Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J)
More informationADC Bit, 50MHz Video A/D Converter
ADC- -Bit, 0MHz Video A/D Converter FEATURES Low power dissipation (0mW max.) Input signal bandwith (00MHz) Optional synchronized clamp function Low input capacitance (pf typ.) +V or +V /+.V power supply
More informationMM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
More informationFeatures. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4071BM CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM CD4081BC Quad 2-Input AND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
More informationRP mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator. General Description. Features. Applications. Ordering Information. Marking Information
RP122 3mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator General Description The RP122 is designed for portable RF and wireless applications with demanding performance and space requirements. The RP122
More information2N6027, 2N6028. Programmable Unijunction Transistor. Programmable Unijunction Transistor Triggers. PUTs 40 VOLTS, 300 mw
26027, referred Device rogrammable Unijunction Transistor rogrammable Unijunction Transistor Triggers Designed to enable the engineer to program unijunction characteristics such as R BB,, I V, and I by
More information