Novel Approach of Semiconductor BEOL Processes Integration

Transcription

1 Novel Approach of Semiconductor BEOL Processes Integration Chun-Jen Weng Proceedings of the XIth International Congress and Exposition June 2-5, 2008 Orlando, Florida USA 2008 Society for Experimental Mechanics Inc. Department of Science and Technology Management Leader University Tainan, 709 Taiwan, R.O.C. Keywords : BEOL, Process Integration, Lithography, Gap-Fill, Semiconductor ABSTRACT The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimizing the sources of process-induced defects is critical to achieving and maintaining high device yields. This paper presents comprehensive the investigating a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub-micron processes integration. As duel damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub-micron CMOS semiconductor BEOL (Back-End-Of-Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included. INTRODUCTION For efficient yield of integrated circuits (IC's) wafer fabrication, successful development and implementation of new processes technologies requires optimization of all parameters that can impact final device yield. Key areas of focus are transistor performance characteristics, device module integration, process integration, and process-induced defects. The newly developed process flow revealed that the major defect source is in key fact capable of producing kiler defects at high densities. The works of defect review of the investigation and characteristics of the defect follows with a critical area analysis calculation to estimate the yield impact. In semiconductor industry, the tight geometries found in small feature sizes, higher pattern density and high aspect ratio contribute to the faster chips the market demands, but also require improved performance with respect to defect density. The striation phenomena were always occurred on sub-micron semiconductor processes,

2 and the higher pattern density and high aspect ratio result in pattern abnormal and collapse. The abnormal phenomena will leads to yield loss on electrical device test and productivity yield losses. Dual damascene processes demand cleanliness since defects at trough etch result in opens, but could also cause problems with later via etch process steps. Therefore, for deep sub-micron era, high pattern density technology is desired for achieving a high performance device. The use of etching and lithography technology to improve sub micron process has been known for years and many semiconductor process technologies have been proposed. However, these difficulties on technologies accompany an increase of significant process steps in conventional Si process. Jean et al. [1] reveal that process development characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology. It has been common knowledge that pattern collapse of this BEOL duel damascene process could be prevented by optimal the process. To control pattern collapse, Koba et al. [2] indicated and demonstrated that tri-layer resist process had a high applicability for device fabrication in BEOL. Nohdo et al. [3] also indicated Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm process. Masazumi et al. [4] describes process optimization of UV curing for ultra Low-k SiOC (ULK-SiOC, k=2.65) and High stress silicon nitride (HS-SiN) liner. Moreover, Lee et al. [5] investigated resist pattern collapse with top rounding resist profile. They find that the resist deformation phenomenon has been a serious problem for under 100 nm line width patterns. The simulated results show that the pattern collapse phenomenon is reduced for the top rounding resist profile rather than for vertical profiles. However, technology and development of silicon transistor (front-end) processing, there are probably a further four working on issues related to interconnect (BEOL) processing. Many problems have been cited in next-generation semiconductor manufacturing processes as devices become ever smaller. A particularly serious problem is pattern collapse, a phenomenon wherein the capillary effect causes photo-resist patterns to collapse during the developing process, which results from the increasingly small photo-resist. This phenomenon is likely to occur when the aspect ratio increasing, defined as the ratio of photo-resistant film thickness to the width of a pattern. Chris et al.[6] discuss pattern collapse, and develop a simple 1D model for collapse, and investigate the impact of collapse on the focus-exposure process window on lithography process. However, for the gap fill process, Tilke et al. [7] investigate FEOL STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond. They prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn't attack the STI liners as compared to HDP, a variety of different STI liners can be implemented. Su, Y.N.et al., [8] proposed a hybrid BEOL dual damascene interconnect approach with organic ultra-low-k for gap filling has been demonstrated. The traditional PR approach with via-first process for dual damascene suffers from ashing damage for CVD ultra-low-k. The approach is able to circumvent the issues mentioned above without introducing process complication. The technology advances and new processes in the lithography area coupled with the increasing market pressures have placed greater demands on defect management. It is important to identify and resolve defects in the lithography area before committing product wafers in order to be competitive in Fabs processes. Moreover, Back-end-of-line (BEOL) defects (e.g., high-resistance via or interconnect defects) have increasing occurrence probability than front-end-of-line (FEOL) defects in nanometer technologies. Edelstein [9] present advanced Cu/Low-k BEOL Integration, Reliability, and Extendibility. The focus will be on BEOL architecture, integration techniques, their impact on reliability, and their outlooks for 32 nm. Chen et al. [10] investigates defect reduction of copper

3 BEOL for advanced ULSI interconnect. Leavey et al. [11] investigate on advanced process control based on lithographic defect inspection and reduction. They proposed methodology based on post-lithographic defect inspection and defective die count analysis was employed which provided effective process monitoring and yield maintenance. The methodology allows rapid decision-making with a minimum of information for post-litho lot disposition. Peterson et al. [12] investigate the Sample Planner cost model was applied to the full range of available defect inspection technologies and sampling strategies based on the commonly known defect mechanisms that occur in the lithography area. From this a recommended optimum sampling and monitoring strategy was obtained. Lee et al. [13] study Investigation and elimination of sphere defects in the isolation module. Their experiments were performed to identify the defect source and determine the mechanism of defect formation. This paper describes some of the defect reduction activities performed during the evaluation of two new device technologies. In-line inspections were implemented in key process modules to monitor for process and integration-related defect issues. Consequently, an optimal and novel metrology that enables the yield enhancement of CMOS without accompanying the increase of process steps has been strongly desired in semiconductor processes integration. In semiconductor sub-micron process integration and development, it is difficult to maintain high effects on yield and device performance due to process control, because of the complicate structure and stress induced on semiconductor wafer. Therefore, for deep sub-micron semiconductor era, process technology is desired for achieving a high performance device. The present invention relates to a process for forming semiconductor process integration and defect defects reduction. More particularly, the present invention relates to a lithography gap-filling process for forming semiconductor BEOL processes fabrication. METHODS The biggest changes occur with respect to the low-k dielectric in logic devices and copper interconnects for semiconductor process integration. The major reliability challenges that must be overcome to achieve the scaling targets for future integrated circuits (ICs) are at the BEOL process. A novel method for processing IC designs for different metal BEOL processes is provided for enabling fabricating using a metal fabrication process an IC originally having a backend design for a different metal fabrication process. The method can be used to convert a backend design of an IC from an old metal process (such as Cu micro process) to a new metal process (such as Cu sub-micro process), without redesigning the IC for the new metal BEOL fabrication process. A gap-filling process, comprising the steps of: providing a substrate having a dielectric layer thereon, wherein the dielectric layer has an opening therein; forming a gap-filling material layer over the dielectric layer and inside the opening, wherein material constituting the gap-filling material layer is a photo-resist material or a bottom anti-reflection coating material; removing a portion of the gap-filling material from the gap-filling material layer to expose the dielectric layer; and conducting a gap-filling material treatment for forming a protective layer on an exposed surface of the gap-filling material layer, wherein the protective layer is not formed over the entire substrate but formed on the exposed surface of the gap-fitting material layer; wherein the gap-filling material treatment includes conducting an ultra-violet curing or a chemical immersion. As semiconductor process is complicated and trade off among each module processes, the process tuning and electrical device become more difficult. Weng et al. [14] [15] proposed a gap-filling process patents on BEOL process. A gap-filling material

4 treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity BEOL process. The investigation of semiconductor process module integration and technology on optimal integrated lithography processes on sub-micron semiconductor process integration were also studied in [16,17]. The studies aim at investigating a novel metrology semiconductor process module integration and technology on optimal integrated lithography processes on nano-semiconductor process integration and solution to the problem of defect reduction on semiconductor wafer. The optimal integrated process sets up a gap-filling material treatment to etch back the gap-filling material layer so that the pattern collapse and striation phenomena were overcome during wafer fabrication process. For semiconductor BEOL copper process, Weng et al. [18] proposed a double coat method on forming damascene structures. A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. Gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photo-resist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photo-resist pattern to form a plurality of trenches. According to the invention, via hole is filled with a gap filler prior to forming the trench, therefore the edge of via hole is not damaged during the etching process for forming the trench. In wafer process manufacturing flow, each process step contributes to the end product's variance. A variational sensitivity analysis helps identify the process steps where optimal process integration can benefit the overall quality of the process flow. Accordingly, one object of the present invention is to provide a gap-filling process capable of producing a gap-filling material layer with an improved surface planarity so that a subsequently formed bottom anti-reflection coating or photo-resist layer over the gap-filling material layer also has a better surface planarity. In this invention, the gap-filling material layer is etched to form a planar surface. Hence, any layer deposited over the gap-filling material layer can have a high level of planarity that facilitates the formation of a correct pattern in subsequent photolithographic and etching operation. Moreover, a substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. Gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photo-resist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photo-resist pattern to form a plurality of trenches RESULTS AND DISCUSS Wafer processing has traditionally depended on a series of localized regulatory controllers to assure process consistency. Especially, BEOL (Back-end-of-line) characterization is increasingly difficult on advanced semiconductor process technology. BEOL module process is the greatest constraint for process integration of the BEOL copper process technology development. However, for the nano-meter technology node, it's process that presents a significant metrology challenge. Moreover, the formation of ultra-fine patterns in BEOL sub-micron generation (90 nm, 65nm, 45nm and beyond)

5 semiconductor fabrication processes will not be without its technological challenges. Damascene structure refers to the practice of forming inter-connecting wires first developed by the ancient artisans of dual damascene structure. Dual damascene structure, including single damascene structure and dual damascene structure, is essential nowadays in the fabrication of inter-connecting wires in semiconductor devices, especially in the fabrication of copper inter-connecting wires. For implementing of damascene structure, a photo-resist pattern is first formed onto a dielectric layer positioned on a substrate to define the positions of via holes to be etched. The serious problem is wafer pattern missing during damascene structure of wafer fabrication. Pattern missing and collapse describes a phenomenon whereby a capillary effect causes photo-resistant patterns to disintegrate during the developing process, due to the use of increasingly photo-resistant and high aspect ration pattern. As semiconductor fabrication process is complicated, optimal process integration of dual damascene manufacturing method of a BEOL metal trench was presented in this study. Figure 1 shows the standard film deposition and physical structure after BEOL copper CMP process. As metal interconnect line aspect ration and pattern density increased, these schemes could be complicate and challengeable with etching and lithography process infrastructure. At the BEOL scheme, leading device makers implemented the first porous low-k chemical vapor deposition (CVD) films at the critical levels, which represented an enormous integration and engineering challenge for the Fabs. Accordingly, the photo-resist pattern used to define via holes becomes more sophisticated, and therefore has a poor adhesion to the dielectric layer. This makes the photo-resist pattern collapse easily during the etching process. As copper semiconductor wafer process, the physical dimension shows as Fig.1. The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the sun-micro CMOS technology was presented. The aspect ration is increasing as electrical device needed. Significant modifications and improvements have been implemented to overcome those challenges as design rules shrink, via/trench processes optimization. Metal interconnect Dielectric material BEOL wide Metal / Via narrow Metal / Via FEOL Fig.1 Semiconductor standard film deposition and physical structure after BEOL copper CMP process. One of the significant difficults in multi-level interconnects that may be implemented by process tuning and optimal integration. As semiconductor fabrication process is complicated, standard copper dual damascene manufacturing method of a BEOL metal trench was presented in Fig 2. A dual damascene process can be used to form an interconnection on semiconductor. In this process, the copper vias are processed using copper damascene just after the contact layer and before the back-end-of-line (BEOL)

6 interconnect stack. This demonstration is important because of the density and interconnect sizes achieved by the potential extension to wafer-scale stacking. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. Vias were formed and patterned on the dielectric layer so that an opening is formed to expose the gate device therein. The metal trench penetrating through the dielectric layer is formed, and the device layer within the contact window is exposed. A dual damascene process is challenge on via and metal lithography and trench process especially for physical and electrical device. Film VIA Photoresistant VIA Etching Clean SiOx SiNx SiOx SiNx Metal / Via Metal / Via Trench Trench Etching Clean Copper Fig.2 standard semiconductor BEOL process flow Accordingly, a metrology of process integration capable of producing a gap-filling material layer with an improved surface planarity so that a subsequently formed bottom anti-reflection coating or photo-resist layer over the gap-filling material layer also has a better surface planarity. After enormous tuning on module process and electrical device check, this study present study relates to a process for forming semiconductor devices. More particularly, the present study and investigation relate to a gap-filling process for forming semiconductor devices. Gap-filling process is a technique that has many applications in semiconductor production. In semiconductor manufacturing, the gap-filling process is often used after openings are formed. Different material is deposited into the openings according to the type of structure desired. For example, insulating material is deposited into the trenches of a shallow trench isolation (STI) structure and conductive material is deposited into the contact window of an inter-metal dielectric (ILD) structure, the via of an inter-metal dielectric (IMD) structure or the metallic interconnect opening of a dual damascene structure. Subsequently, an etching process is performed to etch the dielectric layer not covered by the photo-resist pattern so as to form a plurality via holes. Finally, the photo-resist pattern is stripped, a metal layer is then deposited to fill up via holes, and a polishing process is performed to form a plurality of inter-connecting wires. As device integration improves day by day, the pattern of via holes becomes denser and each via hole has an increasingly high aspect ratio. Accordingly, the photo-resist pattern used to define via holes becomes more sophisticated, and therefore has a poor adhesion to the dielectric layer. This makes the photo-resist pattern collapse easily during the etching process. During lithography process, striation phenomena was random occurred on wafer edge which results from high aspect ratio and pattern density-depend issued during photo resistant-coating process for thick metal layer, as Fig3. This striation phenomenon is not

7 easy to observe by in microscope checking pattern CD (Critical Dimension) on semiconductor process line. However, the phenomena will cause serious defects and yield loss after WAT (Wafer Accept Test). The liquid-coating striation causes not flat on coated material, which will cause pattern missing and collapse on lithograph and etching process. Accordingly, the photo-resistant pattern is tightly fastened during the etching process, and thus the trench is perfectly formed as desired. The striation phenomena were distributed radically, which is key factor on low-yield and pattern missing. The abnormal pattern issue results in influence of serious defects line process development control strategies Defects monitor Pattern Missing Fig.3 Striation and defects result from pattern missing around wafer The integration of new BEOL low-k dielectrics and copper, for example, continue to present many technical challenges. Whether it's in the front end or the back end of the process line, the cleaning, stripping, and other preparation of the wafer surface becomes more challenging as geometries shrink to 65 and 45 nm and beyond. The majority of BEOL challenges fall into the yield and reliability category and can be the most difficult to diagnose and solve. These issues include pattern missing, peeling, dielectric breakdown, and defectivity. As damascene structure, a photo-resist pattern missing, etching selectivity and chemical mechanical polish are especially challengeable during damascene structure of wafer fabrication. As BEOL film stack depends on the electrical device required and module process needed, the dielectric film buffer is extreme high for etching selectivity and CMP buffer loss as Fig.4. Consequently, the high film stack and high high-aspect-ratio line used in damascene processes of BEOL manufacturing challenges. SiOx Process buffer ~2000A Etching process loss buffer~ 1000A CMP process loss buffer~1000 A SiOx SiNx SiOX SiNx Trench~6500 A VIA~6500A Copper Copper Unit:A Fig.4 Semiconductor film deposition module process buffer and physical structure after BEOL copper CMP process

8 BEOL dual damascene lithography Gap-filling process is a technique that has many applications in semiconductor production. In semiconductor manufacturing, the gap-filling process is often used after openings are formed. Different material is deposited into the openings according to the type of structure desired. As the method of forming damascene structures, dielectric layer has a plurality of via holes. Gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photo-resist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photo-resist pattern to form a plurality of trenches. For the process buffering of etching and CMP (Chemical Mechanical Polishing) process losses, the dielectric film layer deposition is extremely high, consequently, the aspect ratio always over 2. After back-end-of-line (BEOL) etching, the selectivity of removing resist and residues with regard to removing low-k and without degrading the dielectric properties is very challenging. For the etching rate and etching selectivity buffer on dielectric film and photo resistant property, the thickness of photo resistance is always extremely higher than dielectric film thickness. For the etching loading effects and etching selectivity issue, pattering top rounding, and trenching pattern abnormal, which will result in defects increased, pattern missing and device mismatch. Fig.5 and Fig6 were also shown the etching abnormal on interconnects pattern developing. The lithographic evaluation showed that the lithographic performance was good, but with much higher etching resistance and higher etch selectivity to the bottom. Trench Pattern Lithography Process Etching PR GFP PR GFP Pattern abnormal Fig.5 Trench pattern develop process issue-trench top and rounding Dense pattern center Edge C Isolation pattern center Edge Fig.6 Comparison of trench pattern on process issue on isolation and dense pattern

9 Accordingly, the photo-resist pattern developed later will have a better and sharp shape as desired. Via hole is filled with a gap filler prior to forming the trench, therefore the edge of via hole is not damaged during the etching process for forming the trench. In addition, photo-resist and ARC films are consecutively formed over the dielectric layer for not only absorbing light beams in the exposure process, but particularly for increasing the adhesion of the photo-resist pattern. Accordingly, the photo-resist pattern is tightly fastened during the etching process, and thus the trench is perfectly formed as desired. As feature sizes continue to shrink BEOL processes are required to deliver high resolution and, sufficiently wide process windows. Considering the etching selectivity, loading effects, and aspect ratio, the photo-resistant easily to collapse after lithography developed process. Fig.7 shows the in-line process abnormal pattern phenomena check. The abnormal pattern collapse phenomena were shown in the right part, which results in the electrical pattern missing and open during wafer electrical accept test and yield loss in mass production. Consequently, Fig7 indicates the dense patterns were easy to collapse than isolation interconnect pattern. Therefore, the etch selectivity in pattern transfer becomes a critical concern from lithography photo resistant pattern developing. The abnormal process development phenomena indicate that photo-resistant abnormal phenomena may result pattern top rounding, electrical bridge, and pattern collapse on pattern developing process. The photo-resistant remain effects the pattern physical structure, moreover, the photo-resistant remain of dense pattern issues shown as Fig.5 to 7 the cross section of isolation and dense pattern. Top View PR Cross-section View Isolation v.s. Dense pattern Fig.7 Trench pattern abnormal process-photo resistant collapse on dense pattern Accordingly, the object of the present invention is to provide a gap-filling process capable of producing a gap-filling material layer with an improved surface planarity so that a subsequently formed bottom anti-reflection coating or photo-resist layer over the gap-filling material layer also has a better surface planarity. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity. However, as pattern density and aspect ration increased, photo-resistant recess issue occurred around the density patterns as Fig 8. Gap fill resistant recess issue will result in photo-resistant deeply recess and not enough.

10 Photo resistant gap fill Photo resistant Coating treatment PR Fig.8 Photo-resistant gap fill striation mechanism The gap-filling material treatment may include etching the dielectric layer and the gap-filling material layer to planarize the gap-filling material layer. In addition, the gap-filling material treatment may also include performing a plasma processing, an ultraviolet curing or a chemical immersion of the gap-filling material layer to form a protective layer over the gap-filling material layer. Furthermore, the gap-filling material treatment may involve etching the dielectric layer and the gap-filling material layer to planarize the gap-filling material layer and then performing a plasma processing, an ultraviolet curing or a chemical immersion of the gap-filling material layer to form a protective layer over the gap-filling material layer. To achieve these and other advantages and in accordance with the purpose of this stduy, as embodied and broadly described herein, the invention provides a gap-filling process. A substrate having a dielectric layer thereon is provided. An opening is formed in the dielectric layer. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material layer is removed to expose the dielectric layer. In present study, we show the result of evaluating sub-micro BEOL integration process by using the test patterns that can cover critical layout situations. Especially, it was focused on the new integrated process. The key steps in our process integration and improvement decomposition methodology are design attribute and process space analysis. By exploring the process integration, method allows to overcome the most challenging patterns to print due to various process issues. Accordingly, The gap-filling material treatment may include etching the dielectric layer and the gap-filling material layer to planarize the gap-filling material layer. In addition, the gap-filling material treatment may also include performing a plasma processing, an ultraviolet curing or a chemical immersion of the gap-filling material layer to form a protective layer over the gap-filling material layer. Furthermore, the gap-filling material treatment may involve etching the dielectric layer and the gap-filling material layer to planarize the gap-filling material layer and then performing a plasma processing, an ultraviolet curing or a chemical immersion of the gap-filling material layer to form a protective layer over the gap-filling material layer. In this investigation, the gap-filling material layer is etched to form a planar surface. Hence, any layer deposited over the gap-filling material layer can have a high level of planarity that facilitates the formation of a correct pattern in subsequent photolithographic and etching operation. Since a protective layer is formed over the gap-filling material layer, intermixing of material between the bottom anti-reflection coating or the photo-resist layer with the gap-filling material layer is stopped. Thus, the gap-filling material layer and the bottom anti-reflection coating or the photo-resist layer can have a high degree of surface planarity. Ultimately, an accurate pattern is reproduced after a photolithographic and etching operation. The invention of BEOL process integration was brief summary as in Fig.9. Between photo resistant and BARC coating, the photo resistant (Gap Fill for pattern) treatment by light etching to round

11 via trench edge and lightly level surface before photo resistant coating and pattern development. Photo resistant gap fill Add Etching / CMP process treatment dielectric film surface Etching Treatment Surface BARC / Photo resistant Coating for trench process PR Fig.9 A Metrology Nano technology on Lithography Gap Fill Processes In this process integration study, the gap-filling material layer is etched to form a planar surface. Hence, any layer deposited over the gap-filling material layer can have a high level of planarity that facilitates the formation of a correct pattern in subsequent photolithographic and etching operation. In summary, this invention sets up a gap-filling material treatment to etch back the gap-filling material layer so that the gap-filling material layer and the cap layer (also the dielectric layer) on each side of the depressed cavity in the upper surface is removed. Since the gap-filling material layer has a plane upper photolithographic and etching processes. Since the gap-filling material layer and the subsequently formed bottom anti-reflection coating or material layer have a high degree of planarity, a correct pattern is reproduced after photo lithographic and etching processes. After new gap fill process integration metrology developed, there is not any pattern collapses and mission on dense and isolated pattern around wafer center and edge on process even high aspect ratio metal interconnect. Fig.10 indicates the pattern the high-density pattern after lithography process ADI (After Development Inspection) and ADI (After Etching Inspection) on process in-line check points. There is no pattern collapse, missing phenomena found. The top rounding on metal interconnects and pattern short, which results from absence of lithography photo-resistant thickness or photo-resistant development collapse from pattern high aspect ration need were also recovered by present process integration metrology. Figure 11 was shown the lithography photo-resistant development remains are enough for etching process even dense density pattern. After via etching process, via interconnects profile are good, and the etching selectivity issue by photo-resistant was not found. As electrical device needs, the semiconductor BEOL process is challengeable and marginal in module process integration. Moreover, the physical dimension of interconnects trench pattern were also shown in Fig.12. From SEM cross-section check, the top and bottom trench patterns were not found rounding and abnormal physical geometry, the may not results in electrical device mismatch. After semiconductor copper metal process, the TEM physical cross-sections were also checks on copper meal interconnects as Fig.13 shown. From Fig.10 to Fig 13, there is no pattern missing and abnormal physical geometry on interconnect line by step-by-step in-line check and verification.

12 ADI AEI C M B C M B Fig.10 In-line inspection after lithography and etching process Fig.11 In-line pattern cross-section inspection after via etching process View A View B Fig12 In-line pattern cross-section inspection after trench etching process Center Edge Fig.13 In-line pattern TEM cross-section inspection after copper process For the electrical test verification, the electrical open/short and resistance were also included in present study. This test pattern is always to check the semiconductor process in-line electrical and physical checking. The V D =1V, V S =V SUB =0V, then electrical resistance (Rc) measured as Fig.14. Fig.15 indicates electrical device test on open/short for copper metal trace line for electrical device requirements. These data distribute tight and no open electrical test data found. To prevent the metal short of the isolated pattern next to or surrounding by the wide metal, the minimum space with wide neighboring metal was defined. Using this proposed process integration methodology, semiconductor lithography gap fill process has been successfully evaluated and optimized. Furthermore, the

13 metrology was adopted in semiconductor process. PAD PAD VD=1V VS=0V Fig.14 Electrical device open/short pattern Wafer 1 Wafer 2 Wafer 3 Fig.15 Electrical device open/short data comparison CONCLUSIONS Accordingly, one object of the present invention is to provide a gap-filling process capable of producing a gap-filling material layer with an improved surface planarity so that a subsequently formed bottom anti-reflection coating or photo-resist layer over the gap-filling material layer also has a better surface planarity. In summary, this invention sets up a gap-filling material treatment to etch back the gap-filling material layer so that the gap-filling material layer and the cap layer (also the dielectric layer) on each side of the depressed cavity in the upper surface is removed. Since the gap-filling material layer has a plane upper surface, any subsequently formed bottom anti-reflection coating or material layer can have a similar high degree of planarity. Ultimately, a correct pattern is reproduced after photo lithographic and etching processes. The pattern collapse and striation phenomena would be overcome during wafer fabrication processes. Consequently, the productivity yield will be also increased. ACKNOWLEDGMENT The author gratefully acknowledge supporting and assistance of NSC E in this study REFERENCES [1] Jeng et al., BEOL process integration of 65nm Cu/low k interconnects, Interconnect Technology Conference, Proceedings of the IEEE 2004 International Volume, Issue, 7-9, pp , 2004.

14 [2] Koba. et al., Tri-layer resists process for fabricating 45-nm L&S patterns by EPL, Proceedings of the SPIE, Volume 6151, pp , [3] Nohdo et al., BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography, Proceedings of the SPIE, Volume 5751, pp , [4] Masazumi et al., Process Optimization of UV Curing for Ultra Low-k Dielectrics and High-Stress SiN Liners, Materials, Processes, Integration and Reliability in Advanced Interconnects for Micro- and Nano-electronics, MRS Proceedings Volume 990, [5] Lee et al., Resist pattern collapse with top rounding resist profile, Micro-processes and Nano-technology Conference, Digest of Papers. Micro processes and Nano-technology, [6] Chris A. Mack, The Lithography Expert: Pattern collapse, Micro-lithography World November, [7] Tilke, A.T. et al., STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond, Advanced Semiconductor Manufacturing Conference, ASMC The 17th Annual SEMI/IEEE, Page(s):71 76, [8] Su, Y.N et al, Low k damage control & its reliability for organic hybrid dual damascene, Physical and Failure Analysis of Integrated Circuits, IPFA Proceedings of the 11th International Symposium on the 5-8 July 2004 Page(s):69 70, [9] Edelstein, Daniel C., Advanced Cu/Low-k BEOL Integration, Reliability, and Extendibility, International Interconnect Technology Conference, IEEE 2007, /IITC , [10] Chen et al., Defect reduction of copper BEOL for advanced ULSI interconnect, Interconnect Technology Conference, Interconnect Technology Conference, Proceedings of the IEEE 2001 International4-6 June 2001 Page(s):21 23, [11] Leavey, J. Boyle, J. Skumanich, A., Advanced process control based on lithographic defect inspection and reduction, Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI, Sept. 2000, page(s): 33 40, [12] Peterson, I. Stoller, M. Gudmundsson, D. Nurani, R. Ashkenaz, S. Breaux, L., Comprehensive cost-effective photo defect monitoring strategy, Semiconductor Manufacturing Symposium, 2001 IEEE International, page(s): 67 70, 2001 [13] Lee, F. Newtran, M. Hulseweh, T., Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI, Sept. 2000, page(s): [14]C.J. Weng et al., Gap-filling process, United States Patent 6,833,318, Dec., [15]C.J. Weng et al., Gap-filling process, China Patent CN C, Oct, [16] C.J. Weng, A Novel Sub-Micron Semiconductor Gap Fill Integrated Processes, No.61, IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tainan, Taiwan on Dec , [17] C.J. Weng et al., A Metrology of Semiconductor BEOL Nano-Technology Lithography and Gap Fill Processes Integration, D20, The 7th International Semiconductor Technology Conference (ISTC2008), Shanghai, China, March 15-17, 2008 [18] C.J. Weng et al., Method of forming damascene structures, United States Patent 7,189,640 Mar., 2007.