Menu. Master-Slave Flip-Flop

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1 Menu Clocks and Master-lave Flip-Flops J-K and other Flip-Flops Truth table & excitation table Adders (see [Lam: pg 130]) Counters Look into my... 1 CLK Master-lave Flip-Flop Master-lave Latch/Flip-Flop E Complex Circuit CLK t c = time when signals change t w = digital systems do their work here, others finish their work in this phase Most digital systems expect their inputs to be stable very early in the t c phase of the clock. As drawn, it is possible for and/or to change while CLK = 1 (during t c ). (active-high and -low) may change during time t c even though other hardware expect them to be stable!! t c t w 2 1

2 Master-lave Flip-Flop : How do we solve this problem? A: Use 2 latch s, one master, one slave. ignals do not change during t c. (This is a digital-only solution; the 3 rd option discussed earlier.) : Why? A: Now {(H), (L)} will not change until t w. Hence, inputs to other systems are stable during t c. CLK Master E E lave t c t w CLK Master-lave - Flip-Flop t w t c 3 Master-lave JK FF Gated - Latch (H) re-et (L) E Master-lave J-K FF (Falling Edge Clock) J K E(H) (H) Master E re-clear lave E (H) J-K FF with falling edge-clock J K > With master-slave FFs we have a completely digital solution to the stable input problem. No oscillation occurs!!!! LogicWorks JK_from_M-_*.cct 4 2

3 Master-lave J-K FF (ising Edge Clock) Master J K E lave J K E Flip-Flops J-K FF with rising edge-clock J K J-K FF with falling edge-clock J K T-FF using JK -FF using JK -FF using T J K J K How about constructing a JK with a? Hint: = J / /K 5 -FF using Two MUXs esigned by Alex Kagioglu, a UF EEL 4712 student, 2008 (H) CLK 2-input MUX 0 Y CLK 1 0 el 2-input MUX 1 el Y (H) d-ff_mux.bdf d-ff_mux.vwf mux2to1.vwf 6 3

J-K Flip-Flop Excitation Table for J-K FF

Abbreviated Abbreviated Excitation Table

ising edge triggered JK-FF Timing iagram J

4 J-K Flip-Flop Excitation Table for J-K FF Next tate Truth Table for J-K FF Abbreviated Next tate Truth Table for J-K FF Abbreviated Excitation Table for J-K FF K-Map gives = J / /K ( = / ) 7 ising edge triggered JK-FF Timing iagram J K Lam: Figure

5 ising edge triggered -FF Timing iagram Lam: Figure Adder Circuits using Memory 1: Is addition sequential? A1: No. (At least not from what we previously learned.) It can be implemented with a combinational circuit. But we CAN make a sequential adder: X i (H) Y i (H) CLK A B C i C i1 FA UM i (H) C i1 (H) > In this circuit a 1-bit FA with a -FF can be used to add an arbitrary N-bit number (e.g., a 32 bit number). But a 32 bit adder without memory requires, for example, eight bit parallel adders. 10 5

6 X i (H) Y i (H) CLK Adder Circuits using Memory A B C i C i1 FA UM i (H) C i1 (H) Lam: Figure 5.5 (Ex 5.1) 11 N-bit Adder (Using Memory and 1-bit FA) 2: How big can N be? What is the cost? A2: As big as you want --- same (IC) cost. Observations: >(1) We can often realize complex combinational logic with simple sequential logic >(2) We can realize impossible combinational functions with sequential logic (e.g., counting) >(3) The trade-off is parallel (combinational) vs. sequential circuits, and time vs. hardware complexity arallel circuits obtain a sum in 1 clock tick; serial circuits require N clock ticks. 12 6

7 teps for Counter esign ecall we mentioned in lecture #2 that counting requires memory. In the next few page we will design a 3-input (8 state or 2 3 ) counter. There are several steps in the design of sequential circuits: > evelop a state diagram > Make a next state truth table (NTT) > ick FFs and get excitation info to NTT > Add outputs to NTT > Get equations for FF inputs and outputs > esign circuits based on the equations A counter turns out to have very simple steps! We will show that some of the steps above are trivial Assumption: A clock pulse is used to clock the counter > (example/analogy) A car counter used by the road department 13 Counter esign tep 1 esign a counter that counts the following sequence: = 100, 010, 111, 110, 011, 000, 101, 001,100,... tart Note the strange counting sequence: 4, 2, 7, 6, 3, 0, 5, 1, 4, 2, 7,

8 3-bit counter (with 2 3 =8 states) needs 3 FF s From the desired counter sequence, for 2 (the next state for 2 ) we obtain the sequence, , i.e., column 2 of the counter sequence but delayed (starting in row 2) by 1 row > 1 : > 0 : > ut this in a next state truth table (NTT) For each FF, we develop state equations > For -FFs i = i, i.e., what comes in goes out immediately after the clock Notice that the counting order truth table (shown here) is preferred Counter esign tep 2 tart Current Next Counter esign tep 3a 2 2 Using these sequences, we fill 3 K-maps, one for each of 2, 1, & 0. / 2 / = / 2 / 0 / 2 / = 2 / 2 / 1 Current Next

9 Counter esign tep 3b 1 1 Using these sequences, we fill 3 K-maps, one for each of 2, 1, & 0. 2 / 0 1 / 0 1 = 2 / 0 1 / = Current Next Counter esign tep 3c 0 0 Using these sequences, we fill 3 K-maps, one for each of 2, 1, & 0. / 2 / 0 1 / 0 2 / = / 2 / 0 1 / 0 2 / 1 0 = 0 Current Next

10 Counter esign tep 4,5,6 2 = / 2 / / 2 / 1 = f 2 ( 2, 1, 0 ) = 2 1 = 2 / 0 1 / = f 0 ( 2, 1, 0 ) = 1 2, 1, 0 2, 1, 0 Comb 2 Comb = / 2 / 0 1 / 0 2 / 1 0 = f 0 ( 2, 1, 0 ) = 0 2, 1, 0 Comb one! CLK 19 Activation-Levels for tate Bits What if one (or more) of the state bits ( i ) is active-low? >As you may recall, when we first started discussing circuits we feedback, I stated that with these types of circuits it is often easier to deal with voltages rather than with logic. ecommendations: >esign the next state circuits for counters (and other state machines) with all active-high state-bits >Then design the output circuits using the appropriate (specified) activation levels 20 10

11 tate Machine esign Inputs Inputs Clk s Next tate Comb. Logic Clk Flip- Flops s Output Comb. Logic Outputs s For Moore machines, there are no dashed line Inputs ; Mealy machines have these inputs For counters, state bits ( s) are generally some of the outputs, but might be active-low or active-high 21 Another Counter esign: tep 1 esign a counter that counts the following sequence: = 000, 001, 101, 100, 010, 110, 111, 011, 000,... Note that naming of the state bits ( ) different than 1st example Observation: imple! Each bubble (node) is a state. The only input is a pulse,. Note the counting sequence: 0, 1, 5, 4, 2, 6, 7, 3, 0, 1, 5, tart

Another Counter esign: tep 2 3 bit counter (8 states or 2 3 =8) 3 FF s From the desired counter sequence, for 1 (the next state from 1 ) we obtain the sequence, 0 1 1 0 1 1 0 0, i.e., column 1 of the counter sequence but delayed (starting in row 2) by 1 row.

12 Another Counter esign: tep 2 3 bit counter (8 states or 2 3 =8) 3 FF s From the desired counter sequence, for 1 (the next state from 1 ) we obtain the sequence, , i.e., column 1 of the counter sequence but delayed (starting in row 2) by 1 row. > 2 : > 3 : > ut this in a next state truth table (NTT) For each FF, we develop state equations > For -FFs i = i, i.e., what comes in goes out Counting: 0, 1, 5, 4, 2, 6, 7, 3, 0, 1, 5, Another Counter esign: tep 3 1 Using these sequences we fill 3 K-maps, one for each of 1, 2, & = = 2 3 = 1 2 = = 2 3 = = ( 1 2 ) = 1 2 =

13 Another Counter esign: tep TE 3 TE 4 Choose FF s to realize i, i=1,2,3. Choose -FF because i = i. imple!!! 1 = 1, 2 = 2, and 3 = 3. What are the output equations? O 1 = 1, O 2 = 2, and O 3 = 3 imple! You could get the outputs from i, but the i s are better with regard to a starting count Another Counter esign: tep 6 TE 5 ealize using -FF, T-FF, -FF or JK-FFs Observation: This circuit contains feedback! ince the flip-flops are edge triggered, after the signal propagates through the combinational network, they do not feedback around to change the states. counter2.cct / 3 2 / Combinational Network CLK Vcc eset GN 26 13

14 Another Counter esign: tep 6 TE 6 Check it with LogicWorks >Build it >imulate it Counter2.cct BOUNCING!! 27 witch Bouncing 28 14

15 witch Bouncing 29 igital witch ebounce Circuit (with T) The - latch should be made with NAN s or NO s > - latch below is made with a -FF used as an - latch 5V Vcc ON OFF C CLN_IN(H) CLN_IN(L) ebounced_witch.cct 30 15

16 Bouncing with T 6V 4V 2V 0V 0ms 1ms 2ms 31 ebounce Circuit esponse 6V 4V 2V 0V 0ms 1ms 2ms 32 16

17 Wrong Time cale for Bouncing with T 6V 4V 2V 0V 0ns 50ns 100ns 150ns 200ns 33 Analog witch ebounce Circuit (with T) Not a good solution, but one that will probably work for HC chips. hould use a chmitt Trigger (74 14) with below Vcc ebounced witch.cct 34 17

18 & A : Can we obtain a cheaper solution using other FF s? A: ossibly. ome like to use JK FFs because you can make any FF using JK. : But shouldn t you use T or -vs- JK because they are slightly faster? A: It is true that a master/slave JK is slightly slower. Typical t 20 ~ 50 ns. Inverters (level shifters) have t 5-10 ns. Unless you have a very high frequency 20 ~ 50 ns (1 ns = 10-9 sec) it is still fast (50-20MHz)! : You start the counter at 000. Anywhere else? A: Yes. The i s are pre-cleared to start at 000. Any other state is relatively simple to obtain using pre-clear/pre-set. : Who would build such a counter? (i.e., to go ) A: Nobody (probably). I wanted to show you that it can be designed using any count sequence you wish. this is a pedagogical example! 35 rocedure for equential tate Machine esign evelop a state diagram > Use bubbles for states, arrows for transitions Create a next state truth table ick FF and add to NTT Add outputs to NTT Use K-maps to find equations to drive the FF inputs to generate the required outputs esign the circuit based on the equations >Use selected FF s and other logic gates 36 18

19 s s tate Machine Counter esign teps art 1 s s s s Next state truth table just adds a i = i s Fill up K-Maps for i using the original order { } s (ex) When =000, 1 =0, 2 =0, and 3 = =101, 1 =1, 2 =0, and 3 =0 37 tate Machine Counter esign teps art 2 ince using -FF (because i = i ) then = 1 = 1, 2 = 2, and 3 = 3. 1 = 2 3, 2 = / 3, and 3 = /( 1 2 ) ince the outputs are the s, i.e., O i = i (or O i = i ) O 1 = 1, O 2 = 2, and O 3 = 3 ET 38 19

tate Machine Counter esign w/ FF s Let s do it with FF s. CLK ince we only want to count, O i = i O 1 = 1, O 2 = 2, and O 3 = 3.

20 tate Machine Counter esign w/ FF s Let s do it with FF s. CLK ince we only want to count, O i = i O 1 = 1, O 2 = 2, and O 3 = tate Machine Counter esign w/ FFs [Example] esign the counter{ } From the previous example we have: Use Excitation Table to Complete the esign 40 20

tate Machine Counter esign w/ FFs [Example] esign the counter{0 1 5 4 2 6 7 3 0}

7 3 0 start ecall: 1 goes 0 0 1 1 0 1 1 0 0 Each arrow is an 1 goes 0 1 1 0 1 1 0 0

21 tate Machine Counter esign w/ FFs [Example] esign the counter{ } From the previous example we have: 41 tate Machine Counter esign w/ FFs start ecall: 1 goes Each arrow is an 1 goes entry in the K-map next For 1 = f( i s) For 1 = f( i s) 1 = = / 1 = /( 2 3 ) 42 21

tate Machine Counter esign w/ FFs For 1 For 1 1 = 2 3 1 = / 1 = /( 2 3 ) 2 3 This is a -FF! CLK 1 o you suppose that we can trivially obtain 2, 2 and 3, 3 since we see a -FF?

22 tate Machine Counter esign w/ FFs For 1 For 1 1 = = / 1 = /( 2 3 ) 2 3 This is a -FF! CLK 1 o you suppose that we can trivially obtain 2, 2 and 3, 3 since we see a -FF? ulse Now do similar for 2 and 3 43 U esign an Up/own Counter Let us design a more general Up/own Counter U U This is a 2-input 4-state system. * Inputs:, U * tates: 1, 0 U = own ulse U = Up ulse U 1 U X X X X 44 22

esign an Up/own Counter 1 U 00 11 U U 01 10 U = own ulse U = Up ulse U 1 Could add an output when the count is at a certain value > Modify NTT > Get

next state) >Outputs depend on type of flip-flop(s) desired and will require use of excitation tables and use of i & i If using JK-FFs: Outputs: J 1,

23 esign an Up/own Counter 1 U U U U = own ulse U = Up ulse U 1 Could add an output when the count is at a certain value > Modify NTT > Get new equation 0 45 Next tate Truth Table You can make a next state truth table >Inputs: 1 and 0 (the state), U, >Intermediate outputs: 1 and 0 (the next state) >Outputs depend on type of flip-flop(s) desired and will require use of excitation tables and use of i & i If using JK-FFs: Outputs: J 1, K 1 and J 0, K 0 If using -FFs Outputs: 1, 0 If using one JK-FF for MB and one -FF for LB Outputs: J 1, K 1 and 0 This option is very common in exams! 46 23

24 The End! 47 24

Digital Logic Design - Chapter 4

Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback