SN54/74LS05 HEX INVERTER HEX INVERTER FAST AND LS TTL DATA 5-1 LOW POWER SCHOTTKY ORDERING INFORMATION GUARANTEED OPERATING RANGES

Transcription

1 EX INERTER SN54/S05 CC EX INERTER OW POWER SCOTTKY * * * * * * *OPEN COECTOR OUTPUTS 7 GND 4 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C O Output oltage igh 54, 5.5 IO Output Current ow ma FAST AND S TT DATA 5-

2 SN54/S05 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma IO Output IG Current 54, 00 µa CC = MIN, O = MAX O II Output OW oltage Input IG Current 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 ICC Power Supply Current Total, Output IG 2.4 ma CC = MAX Total, Output OW 6.6 AC CARACTERISTICS (TA = C) imits tp Turn-Off Delay, Input to Output 7 32 CC = tp Turn-On Delay, Input to Output 5 28 C = 5 pf, R = 2.0 kω FAST AND S TT DATA 5-2

3 TRIPE 3-INPUT NAND GATE SN54/S0 CC TRIPE 3-INPUT NAND GATE OW POWER SCOTTKY GND 4 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

4 SN54/S0 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current Total, Output IG.2 ma CC = MAX Total, Output OW 3.3 Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp Turn-Off Delay, Input to Output CC = tp Turn-On Delay, Input to Output 0 5 C = 5 pf FAST AND S TT DATA 5-2

5 TRIPE 3-INPUT AND GATE SN54/S CC TRIPE 3-INPUT AND GATE OW POWER SCOTTKY GND 4 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

6 SN54/S DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current Total, Output IG 3.6 ma CC = MAX Total, Output OW 6.6 Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp Turn-Off Delay, Input to Output CC = tp Turn-On Delay, Input to Output 0 20 C = 5 pf FAST AND S TT DATA 5-2

7 SCMITT TRIGGERS DUA GATE/EX INERTER The SN54S/ S3 and SN54S/ S4 contain logic gates/ inverters which accept standard TT input signals and provide standard TT output levels. They are capable of traforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contai a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TT totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input traitio, and provide different input threshold voltages for positive and negative-going traitio. This hysteresis between the positive-going and negative-going input thresholds (typically 800 m) is determined internally by resistor ratios and is essentially ieitive to temperature and supply voltage variatio. OGIC AND CONNECTION DIAGRAMS SN54/S3 SN54/S4 SCMITT TRIGGERS DUA GATE/ EX INERTER 4 OW POWER SCOTTKY J SUFFIX CERAMIC CASE CC SN54/ S N SUFFIX PASTIC CASE SN54/ S4 CC GND 8 4 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD D SUFFIX SOIC CASE 75A-02 Ceramic Plastic SOIC GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

8 SN54/S3 SN54/S4 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits T+ Positive-Going Threshold oltage CC = T Negative-Going Threshold oltage 0.6. CC = T+ T ysteresis CC = IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = 400 µa, IN =I 54, CC = MIN, IO = 4.0 ma, IN = CC = MIN, IO = 8.0 ma, IN = 2.0 IT+ Input Current at Positive-Going Threshold 0.4 ma CC =, IN = T+ IT Input Current at Negative-Going Threshold 0.8 ma CC =, IN = T II Input IG Current.0 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX, OUT = 0 ICC Power Supply Current Total, Output IG Total, Output OW S S ma CC = MAX S S4 2 2 Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) Symbol Parameter S3 S4 Unit Test Conditio tp Propagation Delay, Input to Output CC = tp Propagation Delay, Input to Output C = 5 pf Max 3 IN 0.6 tp 0.8 tp OUT Figure. AC Waveforms FAST AND S TT DATA 5-2

9 SN54/S3 SN54/S4 O, OUTPUT OTAGE (OTS) CC = 5 TA = C IN, INPUT OTAGE (OTS) Figure 2. IN versus OUT Trafer Function 2 TA = C T, TRESOD OTAGE (OTS) T, YSTERESIS (OTS) T+ T T CC, POWER SUPPY OTAGE (OTS) Figure 3. Threshold oltage and ysteresis versus Power Supply oltage.9 T, TRESOD OTAGE (OTS) T, YSTERESIS (OTS) T+ T 0.7 T TA, AMBIENT TEMPERATURE ( C) Figure 4. Threshold oltage ysteresis versus Temperature FAST AND S TT DATA 5-3

10 DUA 4-INPUT NAND GATE SN54/S20 CC DUA 4-INPUT NAND GATE OW POWER SCOTTKY GND 4 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

11 SN54/S20 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current Total, Output IG 0.8 ma CC = MAX Total, Output OW 2.2 Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp Turn-Off Delay, Input to Output CC = tp Turn-On Delay, Input to Output 0 5 C = 5 pf FAST AND S TT DATA 5-2

12 8-INPUT NAND GATE SN54/S30 CC INPUT NAND GATE OW POWER SCOTTKY GND 4 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

13 SN54/S30 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current 20 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.4 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current Total, Output IG 0.5 ma CC = MAX Total, Output OW. Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp Turn-Off Delay, Input to Output CC = tp Turn-On Delay, Input to Output 3 20 C = 5 pf FAST AND S TT DATA 5-2

14 BCD TO 7-SEGMENT DECODER/DRIER The SN54/S47 are ow Power Schottky BCD to 7-Segment Decoder/ Drivers coisting of NAND gates, input buffers and seven AND-OR-IN- ERT gates. They offer active OW, high sink current outputs for driving indicators directly. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INERT gates. The remaining NAND gate and three input buffers provide lamp test, blanking input/ ripple-blanking output and ripple-blanking input. The circuits accept 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive a 7-segment display indicator. The relative positive-logic output levels, as well as conditio required at the auxiliary inputs, are shown in the truth tables. Output configuratio of the SN54/ S47 are designed to withstand the relatively high voltages required for 7-segment indicators. These outputs will withstand 5 with a maximum reverse current of 0 µa. Indicator segments requiring up to 24 ma of current may be driven directly from the SNS47 high performance output traistors. Display patter for BCD input counts above nine are unique symbols to authenticate input conditio. The SN54/ S47 incorporates automatic leading and/ or trailing-edge zero-blanking control (RBI and RBO). amp test (T) may be performed at any time which the BI/RBO node is a IG level. This device also contai an overriding blanking input (BI) which can be used to control the lamp inteity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs. amp Inteity Modulation Capability (BI/RBO) Open Collector Outputs amp Test Provision eading/ Trailing Zero Suppression Input Clamp Diodes imit igh-speed Termination Effects CONNECTION DIAGRAM DIP (TOP IEW) CC f g a b c d e SN54/S47 BCD TO 7-SEGMENT DECODER/ DRIER OW POWER SCOTTKY 6 J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD D SUFFIX SOIC CASE 75B-03 Ceramic Plastic SOIC OGIC SYMBO B C T BI / RBO RBI D A GND PIN NAMES OADING (Note a) IG OW A, B, C, D RBI T BI/RBO a, to g BCD Inputs Ripple-Blanking Input amp-test Input Blanking Input or Ripple-Blanking Output Outputs U U U U...2 U.. Open-Collector 8 0. U.. 0. U.. 0. U U U.. 5 (7.5) U.. NOTES: a) Unit oad (U..) = 40 µa IG,.6 ma OW. b) Output current measured at OUT = 0.5 The Output OW drive factor is 7.5 U.. for Military (54) and 5 U.. for Commercial () Temperature Ranges. A B C D T RBI a b c d e f g CC = PIN 6 GND = PIN 8 BI/ RBO FAST AND S TT DATA 5-

15 SN54/S47 OGIC DIAGRAM a a A INPUT B b b C c c D d d OUTPUT BANKING INPUT OR RIPPE-BANKING OUTPUT e e AMP-TEST INPUT RIPPE-BANKING INPUT f g f g NUMERICA DESIGNATIONS RESUTANT DISPAYS TRUT TABE INPUTS OUTPUTS DECIMA OR T RBI D C B A BI/RBO a b c d e f g NOTE FUNCTION 0 A X A 2 X 3 X 4 X 5 X 6 X 7 X 8 X 9 X 0 X X 2 X 3 X 4 X 5 X BI X X X X X X B RBI C T X X X X X D = IG oltage evel = OW oltage evel X = Immaterial NOTES: (A) BI/RBO is wire-and logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a IG level when output functio 0 through 5 are desired, and ripple-blanking input (RBI) must be open or at a IG level if blanking of a decimal 0 is not desired. X = input may be IG or OW. (B) When a OW level is applied to the blanking input (forced condition) all segment outputs go to a OW level regardless of the state of any other input condition. (C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at OW level, with the lamp test input at IG level, all segment outputs go to a IG level and the ripple-blanking output (RBO) goes to a OW level (respoe condition). (D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a IG level, and a OW level is applied to lamp test input, all segment outputs go to a OW level. FAST AND S TT DATA 5-2

16 GUARANTEED OPERATING RANGES SN54/S47 Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range 54 IO Output Current igh BI/ RBO 54, 50 µa IO Output Current ow BI/ RBO BI/RBO O (off) Off-State Output oltage a to g 54, 5 IO (on) On-State Output Current a to g 54 2 ma On-State Output Current a to g 24 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 Guaranteed Input IG Theshold oltage for I Input OW oltage Guaranteed Input OW Threshold oltage 0.8 for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O Output IG oltage, BI / RBO CC = MIN, IO = 50 µa, IN = IN or I per Truth Table Output OW oltage 54, IO =.6 ma CC = MIN, IN = IN or O BI/RBO IO = 3.2 ma I per Truth Table IO (off) Off-State Output Current a thru g 0 µa C ma CC = MAX, IN = IN or I per Truth Table, O (off) = 5 On-State Output oltage 54, IO (on) = 2 ma CC = MAX, IN = I O (on) a thru g IO (on) = 24 ma or I per Truth Table II II Input IG Current Input OW Current BI / RBO Any Input except BI / RBO 20 µa CC = MAX, IN = ma CC = MAX, IN = ma CC = MAX, IN = 0.4 IOS BI / RBO Output Short Circuit Current (Note ) ma CC = MAX, OUT = 0 ICC Power Supply Current ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp tp tp tp Propagation Delay, Address Input to Segment Output Propagation Delay, RBI Input To Segment Output CC = C = 5 pf AC WAEFORMS IN IN tp tp tp tp OUT OUT Figure Figure 2 FAST AND S TT DATA 5-3

17 DUA JK NEGATIE EDGE-TRIGGERED FIP-FOP The SN54S/ S73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes IG, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is IG and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is traferred to the outputs on the negative-going edge of the clock pulse. SN54/S73A DUA JK NEGATIE EDGE-TRIGGERED FIP-FOP OW POWER SCOTTKY 3 (8) OGIC DIAGRAM (Each Flip-Flop) 2 (9) 4 J SUFFIX CERAMIC CASE K 3 (0) CEAR 2 (6) J 4 (7) 4 N SUFFIX PASTIC CASE (5) COCK () 4 D SUFFIX SOIC CASE 75A-02 ORDERING INFORMATION MODE SEECT TRUT TABE SN54SXXJ SNSXXN SNSXXD Ceramic Plastic SOIC OPERATING MODE Reset (Clear) Toggle oad 0 (Reset) oad (Set) old INPUTS OUTPUTS CD J K, h = IG oltage evel, I = OW oltage evel X = Don t Care l, h (q) = ower case letters indicate the state of the referenced input (or output) one set-up time l, h (q) = prior to the IG to OW clock traition. X h l h l X h h l l q q q q 4 3 J K OGIC SYMBO CD CC = PIN 4 GND = PIN J K CD FAST AND S TT DATA 5-

18 SN54/S73A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current J, K Clear Clock J, K Clear Clock µa CC = MAX, IN = 2.7 ma CC = MAX, IN = 7.0 II Input OW Current J, K Clear, Clock ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 6.0 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C, CC = ) imits fmax Maximum Clock Frequency Mz Figure tp Propagation Delay, 5 20 CC = Figure C = 5 pf tp Clock to Output 5 20 AC SETUP REUIREMENTS (TA = C) imits tw Clock Pulse Width igh 20 Figure tw Clear Pulse Width Figure 2 CC =50 ts Setup Time 20 Figure th old Time 0 FAST AND S TT DATA 5-2

19 SN54/S73A AC WAEFORMS J or K * ts() th() =0 tw() tp ts() tw() fmax tp th() =0 tp tp *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure. Clock to Output Delays, Data Set-Up and old Times, Clock Pulse Width tw SET tw CEAR tp tp tp tp Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths FAST AND S TT DATA 5-3

20 4-BIT D ATC The TT/MSI SN54/S75 and SN54/S77 are latches used as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is traferred to the output when the Enable is IG and the output will follow the data input as long as the Enable remai IG. When the Enable goes OW, the information (that was present at the data input at the time the traition occurred) is retained at the output until the Enable is permitted to go IG. The SN54/S75 features complementary and output from a 4-bit latch and is available in the 6-pin packages. For higher component deity applicatio the SN54/ S77 4-bit latch is available in the 4-pin package with outputs omitted. SN54/S75 SN54/S77 4-BIT D ATC OW POWER SCOTTKY CONNECTION DIAGRAMS DIP (TOP IEW) 0 E0 GND J SUFFIX CERAMIC CASE SN54/ S D0 D E2 3 CC D2 D3 3 6 N SUFFIX PASTIC CASE E0 GND NC D SUFFIX SOIC CASE 75B-03 SN54/ S D0 D E2 3 CC D2 D3 NC 4 J SUFFIX CERAMIC CASE PIN NAMES OADING (Note a) IG OW D D4 E0 E Data Inputs Enable Input atches 0, Enable Input atches 2, 3 atch Outputs (Note b) Complimentary atch Outputs (Note b) 0.5 U U U.. 0 U.. 0 U.. 0. U...0 U...0 U.. 5 (2.5) U.. 5 (2.5) U.. NOTES: a) Unit oad (U..) = 40 µa IG. b) The Output OW drive factor is 2.5 U.. for Military (54) and 5 U.. for Commercial () Temperature Ranges. 4 4 N SUFFIX PASTIC CASE D SUFFIX SOIC CASE 75A-02 TRUT TABE (Each latch) tn D tn+ NOTES: t n = bit time before enable negative-going traition t n+ = bit time after enable negative-going traition ORDERING INFORMATION SN54SXXJ Ceramic SNSXXN Plastic SNSXXD SOIC FAST AND S TT DATA 5-

21 SN54/S75 OGIC SYMBOS SN54/S75 SN54/S D0 E0 D D2 D3 E CC = PIN 5 GND = PIN D0 E0 D D2 D3 E CC = PIN 4 GND = PIN NC = PIN 7, DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current D Input E Input D Input E Input µa CC = MAX, IN = 2.7 ma CC = MAX, IN = 7.0 II Input OW Current D Input E Input ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 2 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C, CC = ) imits tp tp Propagation Delay, Data to tp tp tp tp Propagation Delay, Data to Propagation Delay, Enable to CC = C = 5 pf tp tp Propagation Delay, Enable to FAST AND S TT DATA 5-2

22 SN54/S77 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current D Input E Input D Input E Input µa CC = MAX, IN = 2.7 ma CC = MAX, IN = 7.0 II Input OW Current D Input E Input ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 3 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C, CC = ) imits tp tp tp tp Propagation Delay, Data to Propagation Delay, Enable to CC = C = 5 pf FAST AND S TT DATA 5-3

23 SN54/S75 SN54/S77 DATA ENABE TO OTER ATC OGIC DIAGRAM (SN54/S75 ONY) GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma AC SETUP REUIREMENTS (TA = C, CC = ) imits tw Enable Pulse Width igh 20 ts Setup Time 20 CC = th old Time 0 AC WAEFORMS D E ts th tp tp tp tp tp tp tp tp DEFINITION OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock traition from IG-to-OW in order to be recognized and traferred to the outputs. OD TIME (th) is defined as the minimum time following the clock traition from IG-to-OW that the logic level must be maintained at the input in order to eure continued recognition. A negative OD TIME indicates that the correct logic level may be released prior to the clock traition from IG-to-OW and still be recognized. FAST AND S TT DATA 5-4

24 4-BIT MAGNITUDE COMPARATOR The SN54/S85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A, B), each word having four Parallel Inputs (A0 A3, B0 B3); A3, B3 being the most significant inputs. Operation is not restricted to binary codes, the device will work with any monotonic code. Three Outputs are provided: A greater than B (OA>B), A less than B (OA<B), A equal to B (OA=B). Three Expander Inputs, IA>B, IA<B, IA=B, allow cascading without external gates. For proper compare operation, the Expander Inputs to the least significant position must be connected as follows: IA<B= IA>B =, IA=B =. For serial (ripple) expaion, the OA>B, OA<B and OA=B Outputs are connected respectively to the IA>B, IA<B, and IA=B Inputs of the next most significant comparator, as shown in Figure. Refer to Applicatio section of data sheet for high speed method of comparing large words. The Truth Table on the following page describes the operation of the SN54/ S85 under all possible logic conditio. The upper lines describe the normal operation under all conditio that will occur in a single device or in a series expaion scheme. The lower five lines describe the operation under abnormal conditio on the cascading inputs. These conditio occur when the parallel expaion technique is used. Easily Expandable Binary or BCD Comparison OA>B, OA<B, and OA=B Outputs Available 6 6 SN54/S85 4-BIT MAGNITUDE COMPARATOR OW POWER SCOTTKY J SUFFIX CERAMIC CASE N SUFFIX PASTIC CASE CONNECTION DIAGRAM DIP (TOP IEW) CC A3 B2 A2 A B A0 B D SUFFIX SOIC CASE 75B B3 IA<B IA=B IA>B OA>B OA=B O A<B GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. ORDERING INFORMATION SN54SXXJ Ceramic SNSXXN Plastic SNSXXD SOIC OGIC SYMBO PIN NAMES OADING (Note a) IG OW A0 A3, B0 B3 IA=B IA<B, IA>B OA>B OA<B OA=B Parallel Inputs A = B Expander Inputs A < B, A > B, Expander Inputs A Greater Than B Output (Note b) B Greater Than A Output (Note b) A Equal to B Output (Note b).5 U...5 U U.. 0 U.. 0 U.. 0 U U U.. 0. U.. 5 (2.5) U.. 5 (2.5) U.. 5 (2.5) U.. NOTES: a) TT Unit oad (U..) = 40 µa IG/.6 ma OW. b) The Output OW drive factor is 2.5 U.. for Military (54) and 5 U.. for Commercial () Temperature Ranges A0 A A2 A3 B0 B B2 B3 IA>B IA<B IA=B CC = PIN 6 GND = PIN 8 OA>B OA<B OA=B FAST AND S TT DATA 5-

25 SN54/S85 OGIC DIAGRAM A3(5) B3 () (5) OA>B (3) A2 B2 (4) (2) A<B (3) A=B (4) A>B (2) A B () (6) OA=B (7) OA<B (0) A0 B0 (9) COMPARING INPUTS TRUT TABE CASCADING INPUTS OUTPUTS A3,B3 A2,B2 A,B A0,B0 IA>B IA<B IA=B OA>B OA<B OA=B A3>B3 X X X X X X A3<B3 X X X X X X A3=B3 A2>B2 X X X X X A3=B3 A2<B2 X X X X X A3=B3 A2=B2 A>B X X X X A3=B3 A2=B2 A<B X X X X A3=B3 A2=B2 A=B A0>B0 X X X A3=B3 A2=B2 A=B A0<B0 X X X A3=B3 A2=B2 A=B A0=B0 A3=B3 A2=B2 A=B A0=B0 A3=B3 A2=B2 A=B A0=B0 X X A3=B3 A2=B2 A=B A0=B0 A3=B3 A2=B2 A=B A0=B0 = IG evel = OW evel X = IMMATERIA GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage 54 TA Operating Ambient Temperature Range 54 IO Output Current igh 54, 0.4 ma IO Output Current ow ma C FAST AND S TT DATA 5-2

26 SN54/S85 A 0 A A 2 A 3 B 0 B B 2 B 3 A n3 A n2 A n A n B n3 B n2 B n B n A 0 A A 2 A 3 B 0 B B 2 B 3 A 0 A A 2 A 3 B 0 B B 2 B 3 I A > B O A > B I A > B O A > B I A < B SN54/S85 O A < B I A < B SN54/S85 O A < B I A = B O A = B I A = B O A = B = OW EE = IG EE Figure. Comparing Two n-bit Words A > B A < B A = B APPICATIONS Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique shown in Figure, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded to any number of bits, see Table. WORD ENGT Table NUMBER OF PKGS. 4 Bits 5 24 Bits Bits 8 3 NOTE: The SN54/S85 can be used as a 5-bit comparator only when the outputs are used to drive the A 0 A 3 and B 0 B 3 inputs of another SN54/S85 as shown in Figure 2 in positio #, 2, 3, and 4. INPUTS (SB) A 0 A A 2 A 3 B 0 B B 2 B 3 (MSB) A 20 A 2 A 22 A 23 B 20 B 2 B 22 B 23 A 0 A A 2 A 3 B 0 B B 2 B 3 I A > B O A > B I A < B #5 O A < B A 9 B 9 A 0 A A 2 A 3 B 0 B B 2 B 3 I A > B O A > B I A < B # O A < B I A = B O A = B I A = B O A = B NC INPUTS A 5 A 6 A 7 A 8 B 5 B 6 B 7 B 8 A 0 A A 2 A 3 B 0 B B 2 B 3 A 5 A 6 A 7 A 8 B 5 B 6 B 7 B 8 A 0 A A 2 A 3 B 0 B B 2 B 3 A 0 A A 2 A 3 B 0 B B 2 B 3 A 0 A A 2 A 3 B 0 B B 2 B 3 A 4 B 4 I A > B I A < B I A = B #4 O A > B O A < B O A = B NC A 9 B 9 I A > B I A < B I A = B #3 O A > B O A < B O A = B NC A 4 B 4 I A > B I A < B I A = B #2 O A > B O A < B O A = B NC A 0 A A 2 A 3 B 0 B B 2 B 3 I A > B I A < B I A = B #6 O A > B O A < B O A = B OUTPUTS MSB = MOST SIGNIFICANT BIT SB = EAST SIGNIFICANT BIT = OW EE = IG EE NC = NO CONNECTION Figure 2. Comparison of Two 24-Bit Words FAST AND S TT DATA 5-3

27 SN54/S85 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current A < B, A > B Other Inputs A < B, A > B Other Inputs µa CC = MAX, IN = 2.7 ma CC = MAX, IN = 7.0 II Input OW Current A < B, A > B Other Inputs IOS Output Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 20 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C, CC = ) imits ma CC = MAX, IN = 0.4 tp tp Any A or B to A < B, A > B tp tp Any A or B to A = B tp tp A < B or A = B to A > B CC = C = 5 pf tp tp A = B to A = B tp tp A > B or A = B to A < B AC WAEFORMS IN IN tp tp tp tp OUT OUT Figure 3 Figure 4 FAST AND S TT DATA 5-4

28 UAD 2-INPUT EXCUSIE OR GATE SN54/S86 CC UAD 2-INPUT EXCUSIE OR GATE OW POWER SCOTTKY J SUFFIX CERAMIC CASE GND TRUT TABE IN OUT A B Z 4 4 N SUFFIX PASTIC CASE ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD D SUFFIX SOIC CASE 75A-02 Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma FAST AND S TT DATA 5-

29 SN54/S86 DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II Input IG Current 40 µa CC = MAX, IN = ma CC = MAX, IN = 7.0 II Input OW Current 0.8 ma CC = MAX, IN = 0.4 IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 0 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = C) imits tp tp tp tp Propagation Delay, Other Input OW Propagation Delay, Other Input IG CC = C = 5 pf FAST AND S TT DATA 5-2

30 DECADE COUNTER; DIIDE-BY-TWEE COUNTER; 4-BIT BINARY COUNTER The SN54/S90, SN54/S92 and SN54/S93 are high-speed 4-bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either a divide-by-five (S90), divide-by-six (S92) or divide-by-eight (S93) section which are triggered by a IG-to-OW traition on the clock inputs. Each section can be used separately or tied together ( to ) to form BCD, bi-quinary, modulo-2, or modulo-6 counters. All of the counters have a 2-input gated Master Reset (Clear), and the S90 also has a 2-input gated Master Set (Preset 9). ow Power Coumption...Typically 45 mw igh Count Rates...Typically 42 Mz Choice of Counting Modes... BCD, Bi-uinary, Divide-by-Twelve, Binary Input Clamp Diodes imit igh Speed Termination Effects SN54/S90 SN54/S92 SN54/S93 DECADE COUNTER; DIIDE-BY-TWEE COUNTER; 4-BIT BINARY COUNTER 4 OW POWER SCOTTKY J SUFFIX CERAMIC CASE PIN NAMES OADING (Note a) IG OW 0 Clock (Active OW going edge) Input to 0.5 U...5 U.. 2 Section Clock (Active OW going edge) Input to 0.5 U U.. 5 Section (S90), 6 Section (S92) Clock (Active OW going edge) Input to 0.5 U...0 U.. 8 Section (S93) MR, MR2 Master Reset (Clear) Inputs 0.5 U.. 0. U.. MS, MS2 Master Set (Preset-9, S90) Inputs 0.5 U.. 0. U.. 0 Output from 2 Section (Notes b & c) 0 U.. 5 (2.5) U.., 2, 3 Outputs from 5 (S90), 6 (S92), 8 (S93) Sectio (Note b) 0 U.. 5 (2.5) U.. NOTES: a. TT Unit oad (U..) = 40 µa IG/.6 ma OW. b. The Output OW drive factor is 2.5 U.. for Military, (54) and 5 U.. for commercial () b. Temperature Ranges. c. The 0 Outputs are guaranteed to drive the full fan-out plus the input of the device. d. To iure proper operation the rise (t r ) and fall time (t f ) of the clock must be less than N SUFFIX PASTIC CASE ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD D SUFFIX SOIC CASE 75A-02 Ceramic Plastic SOIC OGIC SYMBO S90 S92 S MS 0 MR MR MR CC = PIN 5 GND = PIN 0 NC = PINS 4, CC = PIN 5 GND = PIN 0 NC = PINS 2, 3, 4, CC = PIN 5 GND = PIN 0 NC = PIN 4, 6, 7, 3 FAST AND S TT DATA 5-

31 SN54/S90 SN54/S92 SN54/S93 OGIC DIAGRAM MS MS2 0 MR MR J SD K CD J SD K CD S90 J SD K CD R S D S CD = PIN NUMBERS CC = PIN 5 GND = PIN 0 CONNECTION DIAGRAM DIP (TOP IEW) MR MR2 NC CC MS MS NC GND NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM J 4 0 K CD 6 MR MR2 7 J K CD S92 J K CD J K CD = PIN NUMBERS CC = PIN 5 GND = PIN 0 CONNECTION DIAGRAM DIP (TOP IEW) NC NC NC CC MR MR NC GND NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM S93 CONNECTION DIAGRAM DIP (TOP IEW) 0 4 J K CD J K CD J K CD J K CD MR MR2 NC NC MR MR CC NC NC GND = PIN NUMBERS CC = PIN 5 GND = PIN 0 NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. FAST AND S TT DATA 5-2

32 SN54/S90 SN54/S92 SN54/S93 FUNCTIONA DESCRIPTION The S90, S92, and S93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each device coists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (S90), divide-by-six (S92), or divide-by-eight (S93) section. Each section has a separate clock input which initiates state changes of the counter on the IG-to-OW clock traition. State changes of the outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The 0 output of each device is designed and specified to drive the rated fan-out plus the input of the device. A gated AND asynchronous Master Reset (MR MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS MS2) is provided on the S90 which overrides the clocks and the MR inputs and sets the outputs to nine (). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. S90 A. BCD Decade (842) Counter The input must be externally connected to the 0 output. The 0 input receives the incoming count and a BCD count sequence is produced. B. Symmetrical Bi-quinary Divide-By-Ten Counter The 3 output must be externally connected to the 0 input. The input count is then applied to the input and a divide-byten square wave is obtained at output 0. C. Divide-By-Two and Divide-By-Five Counter No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function (0 as the input and 0 as the output). The input is used to obtain binary divide-by-five operation at the 3 output. S92 A. Modulo 2, Divide-By-Twelve Counter The input must be externally connected to the 0 output. The 0 input receives the incoming count and 3 produces a symmetrical divide-by-twelve square wave output. B. Divide-By-Two and Divide-By-Six Counter No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function. The input is used to obtain divide-by-three operation at the and 2 outputs and divide-by-six operation at the 3 output. S93 A. 4-Bit Ripple Counter The output 0 must be externally connected to input. The input count pulses are applied to input 0. Simultaneous divisio of 2, 4, 8, and 6 are performed at the 0,, 2, and 3 outputs as shown in the truth table. B. 3-Bit Ripple Counter The input count pulses are applied to input. Simultaneous frequency divisio of 2, 4, and 8 are available at the, 2, and 3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. FAST AND S TT DATA 5-3

33 5-4 FAST AND S TT DATA SN54/S90 SN54/S92 SN54/S93 S90 MODE SEECTION RESET/ SET INPUTS OUTPUTS MR MR2 MS MS X X X X X X X X X Count Count Count Count X X X = IG oltage evel = OW oltage evel X = Don t Care S92 AND S93 MODE SEECTION RESET INPUTS OUTPUTS MR MR Count Count Count = IG oltage evel = OW oltage evel X = Don t Care S90 BCD COUNT SEUENCE COUNT OUTPUT NOTE: Output 0 is connected to Input for BCD count. S92 TRUT TABE COUNT OUTPUT NOTE: Output 0 is connected to Input. S93 TRUT TABE COUNT OUTPUT NOTE: Output 0 is connected to Input.

34 SN54/S90 SN54/S92 SN54/S93 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II II Input IG Current Input OW Current MS, MR 0 (S90, S92) (S93) 20 µa CC = MAX, IN = ma CC = MAX, IN = IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 5 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. ma CC = MAX, IN = 0.4 FAST AND S TT DATA 5-5

35 SN54/S90 SN54/S92 SN54/S93 AC CARACTERISTICS (TA = C, CC =, C = 5 pf) imits S90 S92 S93 Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit fmax 0 Input Clock Frequency Mz fmax Input Clock Frequency Mz tp tp Propagation Delay, 0 Input to 0 Output tp tp 0 Input to 3 Output tp tp Input to Output tp tp Input to 2 Output tp tp Input to 3 Output tp MS Input to 0 and 3 Outputs tp MS Input to and 2 Outputs tp MR Input to Any Output AC SETUP REUIREMENTS (TA = C, CC = ) imits S90 S92 S93 Symbol Parameter Min Max Min Max Min Max Unit tw 0 Pulse Width tw Pulse Width tw MS Pulse Width 5 tw MR Pulse Width trec Recovery Time MR to RECOERY TIME (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock traition from IG-to-OW in order to recognize and trafer IG data to the outputs AC WAEFORMS * tp tw tp Figure *The number of Clock Pulses required between the t P and t P measurements can be determined from the appropriate Truth Tables. MR & MS MS tw trec tw trec tp 0 3 (S90) tp Figure 2 Figure 3 FAST AND S TT DATA 5-6

36 DECADE COUNTER; DIIDE-BY-TWEE COUNTER; 4-BIT BINARY COUNTER The SN54/S90, SN54/S92 and SN54/S93 are high-speed 4-bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either a divide-by-five (S90), divide-by-six (S92) or divide-by-eight (S93) section which are triggered by a IG-to-OW traition on the clock inputs. Each section can be used separately or tied together ( to ) to form BCD, bi-quinary, modulo-2, or modulo-6 counters. All of the counters have a 2-input gated Master Reset (Clear), and the S90 also has a 2-input gated Master Set (Preset 9). ow Power Coumption...Typically 45 mw igh Count Rates...Typically 42 Mz Choice of Counting Modes... BCD, Bi-uinary, Divide-by-Twelve, Binary Input Clamp Diodes imit igh Speed Termination Effects SN54/S90 SN54/S92 SN54/S93 DECADE COUNTER; DIIDE-BY-TWEE COUNTER; 4-BIT BINARY COUNTER 4 OW POWER SCOTTKY J SUFFIX CERAMIC CASE PIN NAMES OADING (Note a) IG OW 0 Clock (Active OW going edge) Input to 0.5 U...5 U.. 2 Section Clock (Active OW going edge) Input to 0.5 U U.. 5 Section (S90), 6 Section (S92) Clock (Active OW going edge) Input to 0.5 U...0 U.. 8 Section (S93) MR, MR2 Master Reset (Clear) Inputs 0.5 U.. 0. U.. MS, MS2 Master Set (Preset-9, S90) Inputs 0.5 U.. 0. U.. 0 Output from 2 Section (Notes b & c) 0 U.. 5 (2.5) U.., 2, 3 Outputs from 5 (S90), 6 (S92), 8 (S93) Sectio (Note b) 0 U.. 5 (2.5) U.. NOTES: a. TT Unit oad (U..) = 40 µa IG/.6 ma OW. b. The Output OW drive factor is 2.5 U.. for Military, (54) and 5 U.. for commercial () b. Temperature Ranges. c. The 0 Outputs are guaranteed to drive the full fan-out plus the input of the device. d. To iure proper operation the rise (t r ) and fall time (t f ) of the clock must be less than N SUFFIX PASTIC CASE ORDERING INFORMATION SN54SXXJ SNSXXN SNSXXD D SUFFIX SOIC CASE 75A-02 Ceramic Plastic SOIC OGIC SYMBO S90 S92 S MS 0 MR MR MR CC = PIN 5 GND = PIN 0 NC = PINS 4, CC = PIN 5 GND = PIN 0 NC = PINS 2, 3, 4, CC = PIN 5 GND = PIN 0 NC = PIN 4, 6, 7, 3 FAST AND S TT DATA 5-

37 SN54/S90 SN54/S92 SN54/S93 OGIC DIAGRAM MS MS2 0 MR MR J SD K CD J SD K CD S90 J SD K CD R S D S CD = PIN NUMBERS CC = PIN 5 GND = PIN 0 CONNECTION DIAGRAM DIP (TOP IEW) MR MR2 NC CC MS MS NC GND NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM J 4 0 K CD 6 MR MR2 7 J K CD S92 J K CD J K CD = PIN NUMBERS CC = PIN 5 GND = PIN 0 CONNECTION DIAGRAM DIP (TOP IEW) NC NC NC CC MR MR NC GND NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM S93 CONNECTION DIAGRAM DIP (TOP IEW) 0 4 J K CD J K CD J K CD J K CD MR MR2 NC NC MR MR CC NC NC GND = PIN NUMBERS CC = PIN 5 GND = PIN 0 NC = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. FAST AND S TT DATA 5-2

38 SN54/S90 SN54/S92 SN54/S93 FUNCTIONA DESCRIPTION The S90, S92, and S93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each device coists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (S90), divide-by-six (S92), or divide-by-eight (S93) section. Each section has a separate clock input which initiates state changes of the counter on the IG-to-OW clock traition. State changes of the outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The 0 output of each device is designed and specified to drive the rated fan-out plus the input of the device. A gated AND asynchronous Master Reset (MR MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS MS2) is provided on the S90 which overrides the clocks and the MR inputs and sets the outputs to nine (). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. S90 A. BCD Decade (842) Counter The input must be externally connected to the 0 output. The 0 input receives the incoming count and a BCD count sequence is produced. B. Symmetrical Bi-quinary Divide-By-Ten Counter The 3 output must be externally connected to the 0 input. The input count is then applied to the input and a divide-byten square wave is obtained at output 0. C. Divide-By-Two and Divide-By-Five Counter No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function (0 as the input and 0 as the output). The input is used to obtain binary divide-by-five operation at the 3 output. S92 A. Modulo 2, Divide-By-Twelve Counter The input must be externally connected to the 0 output. The 0 input receives the incoming count and 3 produces a symmetrical divide-by-twelve square wave output. B. Divide-By-Two and Divide-By-Six Counter No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function. The input is used to obtain divide-by-three operation at the and 2 outputs and divide-by-six operation at the 3 output. S93 A. 4-Bit Ripple Counter The output 0 must be externally connected to input. The input count pulses are applied to input 0. Simultaneous divisio of 2, 4, 8, and 6 are performed at the 0,, 2, and 3 outputs as shown in the truth table. B. 3-Bit Ripple Counter The input count pulses are applied to input. Simultaneous frequency divisio of 2, 4, and 8 are available at the, 2, and 3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. FAST AND S TT DATA 5-3

39 5-4 FAST AND S TT DATA SN54/S90 SN54/S92 SN54/S93 S90 MODE SEECTION RESET/ SET INPUTS OUTPUTS MR MR2 MS MS X X X X X X X X X Count Count Count Count X X X = IG oltage evel = OW oltage evel X = Don t Care S92 AND S93 MODE SEECTION RESET INPUTS OUTPUTS MR MR Count Count Count = IG oltage evel = OW oltage evel X = Don t Care S90 BCD COUNT SEUENCE COUNT OUTPUT NOTE: Output 0 is connected to Input for BCD count. S92 TRUT TABE COUNT OUTPUT NOTE: Output 0 is connected to Input. S93 TRUT TABE COUNT OUTPUT NOTE: Output 0 is connected to Input.

40 SN54/S90 SN54/S92 SN54/S93 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit CC Supply oltage TA Operating Ambient Temperature Range C IO Output Current igh 54, 0.4 ma IO Output Current ow ma DC CARACTERISTICS OER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits I Input IG oltage 2.0 I Input OW oltage Guaranteed Input IG oltage for Guaranteed Input OW oltage for IK Input Clamp Diode oltage CC = MIN, IIN = 8 ma O O Output IG oltage Output OW oltage CC = MIN, IO = MAX, IN = I or I per Truth Table 54, IO = 4.0 ma CC = CC MIN, IN =I or I IO = 8.0 ma per Truth Table II II Input IG Current Input OW Current MS, MR 0 (S90, S92) (S93) 20 µa CC = MAX, IN = ma CC = MAX, IN = IOS Short Circuit Current (Note ) ma CC = MAX ICC Power Supply Current 5 ma CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. ma CC = MAX, IN = 0.4 FAST AND S TT DATA 5-5

41 SN54/S90 SN54/S92 SN54/S93 AC CARACTERISTICS (TA = C, CC =, C = 5 pf) imits S90 S92 S93 Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit fmax 0 Input Clock Frequency Mz fmax Input Clock Frequency Mz tp tp Propagation Delay, 0 Input to 0 Output tp tp 0 Input to 3 Output tp tp Input to Output tp tp Input to 2 Output tp tp Input to 3 Output tp MS Input to 0 and 3 Outputs tp MS Input to and 2 Outputs tp MR Input to Any Output AC SETUP REUIREMENTS (TA = C, CC = ) imits S90 S92 S93 Symbol Parameter Min Max Min Max Min Max Unit tw 0 Pulse Width tw Pulse Width tw MS Pulse Width 5 tw MR Pulse Width trec Recovery Time MR to RECOERY TIME (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock traition from IG-to-OW in order to recognize and trafer IG data to the outputs AC WAEFORMS * tp tw tp Figure *The number of Clock Pulses required between the t P and t P measurements can be determined from the appropriate Truth Tables. MR & MS MS tw trec tw trec tp 0 3 (S90) tp Figure 2 Figure 3 FAST AND S TT DATA 5-6

42 DMS23 Dual Retriggerable One-Shot with Clear and Complementary Outputs General Description The DMS23 is a dual retriggerable monostable multivibrator capable of generating output pulses from a few nanoseconds to extremely long duration up to 00% duty cycle Each device has three inputs permitting the choice of either leading edge or trailing edge triggering Pin (A) is an activelow traition trigger input and pin (B) is an active-high traition trigger input The clear (CR) input terminates the output pulse at a predetermined time independent of the timing components The clear input also serves as a trigger input when it is pulsed with a low level pulse traition ( ) To obtain the best trouble free operation from this device please read the operating rules as well as the NSC one-shot application notes carefully and observe recommendatio Features Y Y DC triggered from active-high traition or active-low traition inputs Retriggerable to 00% duty cycle Y Compeated for CC and temperature variatio Y Triggerable from CEAR input Y DT TT compatible Y Input clamp diodes March 99 Functional Description The basic output pulse width is determined by selection of an external resistor (R X ) and capacitor (C X ) Once triggered the basic pulse width may be extended by retriggering the gated active-low traition or active-high traition inputs or be reduced by use of the active-low or CEAR input Retriggering to 00% duty cycle is possible by application of an input pulse train whose cycle time is shorter than the output cycle time such that a continuous IG logic state is maintained at the output DMS23 Dual Retriggerable One-Shot with Clear and Complementary Outputs Connection Diagram Function Table Dual-In-ine Package Inputs Outputs CEAR A B X X X X X X u v u e igh ogic evel e ow ogic evel X e Can Be Either ow or igh u e Positive Going Traition v e Negative Going Traition e A Positive Pulse e A Negative Pulse T F 6386 Order Number DMS23M or DMS23N See NS Package Number M6A or N6E C995 National Semiconductor Corporation T F 6386 RRD-B30M05 Printed in U S A