Connection Diagram DECODIFICADORES. 74LS42 Decodificador BCD a decimal. Grado en Ingeniería Informática FUNDAMENTOS DE TECNOLIGÍA DE COMPUTADORES
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1 Grado en Ingeniería Informática DEPARTAMENTO DE AUTOMÁTICA ARQUITECTURA Y TECNOLOGÍA DE COMPUTADORES FUNDAMENTOS DE TECNOLIGÍA DE COMPUTADORES Circuitos combinacionales MSI DECODIFICADORES 74LS42 Decodificador BCD a decimal Connection Diagram Dual-In-Line Package
2 Function Table No. BCD Inputs Decimal Outputs D C B A L L L L L H H H H H H H H H 1 L L L H H L H H H H H H H H 2 L L H L H H L H H H H H H H 3 L L H H H H H L H H H H H H 4 L H L L H H H H L H H H H H 5 L H L H H H H H H L H H H H 6 L H H L H H H H H H L H H H 7 L H H H H H H H H H H L H H 8 H L L L H H H H H H H H L H 9 H L L H H H H H H H H H H L I H L H L H H H H H H H H H H N H L H H H H H H H H H H H H V H H L L H H H H H H H H H H A H H L H H H H H H H H H H H L H H H L H H H H H H H H H H I H H H H H H H H H H H H H H D H e High Level L e Low Level Logic Diagram e
3 74LS138 Decodificador 3 a 8 Connection Diagrams DM74LS138 Function Tables DM74LS138 Inputs Enable Select Outputs G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H L H H H H H H H L L H L H H L H H H H H H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L Note 1: G2 = G2A + G2B
4 Logic Diagrams DM74LS138 74LS154 Decodificador 4 a 16 Connection and Logic Diagrams Dual-In-Line Package
5
6 Function Table Inputs Outputs G1 G2 D C B A L L L L L L L H H H H H H H H H H H H H H H L L L L L H H L H H H H H H H H H H H H H H L L L L H L H H L H H H H H H H H H H H H H L L L L H H H H H L H H H H H H H H H H H H L L L H L L H H H H L H H H H H H H H H H H L L L H L H H H H H H L H H H H H H H H H H L L L H H L H H H H H H L H H H H H H H H H L L L H H H H H H H H H H L H H H H H H H H L L H L L L H H H H H H H H L H H H H H H H L L H L L H H H H H H H H H H L H H H H H H L L H L H L H H H H H H H H H H L H H H H H L L H L H H H H H H H H H H H H H L H H H H L L H H L L H H H H H H H H H H H H L H H H L L H H L H H H H H H H H H H H H H H L H H L L H H H L H H H H H H H H H H H H H H L H L L H H H H H H H H H H H H H H H H H H H L L H X X X X H H H H H H H H H H H H H H H H H L X X X X H H H H H H H H H H H H H H H H H H X X X X H H H H H H H H H H H H H H H H H e High Level, L e Low Level, X e Don t Care 74LS47 Decodificador BCD a 7 segmentos Logic Symbol Connection Diagram V CC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names Description A0 A3 BCD Inputs RBI Ripple Blanking Input (Active LOW) LT Lamp Test Input (Active LOW) BI/RBO Blanking Input (Active LOW) or Ripple Blanking Output (Active LOW) a g Segment Outputs (Active LOW) (Note 1) Note 1: OC Open Collector
7 Truth Table Decimal Inputs Outputs or Note Function LT RBI A3 A2 A1 A0 BI/RBO a b c d e f g 0 H H L L L L H L L L L L L H (Note 2) 1 H X L L L H H H L L H H H H (Note 2) 2 H X L L H L H L L H L L H L 3 H X L L H H H L L L L H H L 4 H X L H L L H H L L H H L L 5 H X L H L H H L H L L H L L 6 H X L H H L H H H L L L L L 7 H X L H H H H L L L H H H H 8 H X H L L L H L L L L L L L 9 H X H L L H H L L L H H L L 10 H X H L H L H H H H L L H L 11 H X H L H H H H H L L H H L 12 H X H H L L H H L H H H L L 13 H X H H L H H L H H L H L L 14 H X H H H L H H H H L L L L 15 H X H H H H H H H H H H H H BI X X X X X X L H H H H H H H (Note 3) RBI H L L L L L L H H H H H H H (Note 4) LT L X X X X X H L L L L L L L (Note 5) Note 2: BI/RBO is wire-and logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not desired. X = input may be HIGH or LOW. Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input condition. Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment outputs go to a LOW level. Functional Description The DM74LS47 decodes the input data in the pattern indicated in the Truth Table and the segment identification illustration. If the input data is decimal zero, a LOW signal applied to the RBI blanks the display and causes a multidigit display. For example, by grounding the RBI of the highest order decoder and connecting its BI/RBO to RBI of the next lowest order decoder, etc., leading zeros will be suppressed. Similarly, by grounding RBI of the lowest order decoder and connecting its BI/RBO to RBI of the next highest order decoder, etc., trailing zeros will be suppressed. Leading and trailing zeros can be suppressed simultaneously by using external gates, i.e.: by driving RBI of a intermediate decoder from an OR gate whose inputs are BI/RBO of the next highest and lowest order decoders. BI/ RBO also serves as an unconditional blanking input. The internal NAND gate that generates the RBO signal has a resistive pull-up, as opposed to a totem pole, and thus BI/ RBO can be forced LOW by external means, using wiredcollector logic. A LOW signal thus applied to BI/RBO turns off all segment outputs. This blanking feature can be used to control display intensity by varying the duty cycle of the blanking signal. A LOW signal applied to LT turns on all segment outputs, provided that BI/RBO is not forced LOW.
8 Logic Diagram Numerical Designations Resultant Displays
9 CODIFICADORES 74LS147 Codificador con prioridad decimal BCD SN54/ 74LS147 (TOP VIEW) SN54/ 74LS147 FUNCTION TABLE INPUTS OUTPUTS D C B A H H H H H H H H H H H H H X X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L X L H H H H H H H H H L H L H H H H H H H H H H H L H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant
10 SN54/ 74LS147
11 74LS148 Codificador con prioridad 8 a 3 SN54/ 74LS148 SN54/ 74LS748 (TOP VIEW) INPUTS SN54/ 74LS148 SN54/ 74LS748 FUNCTION TABLE OUTPUTS EI A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H
12 SN54/ 74LS148
13 MULTIPLEXORES 74LS157 Cuádruple multiplexor de dos entradas LOGIC SYMBOL E I0a I1a I0b I1b I0c I1c I0d I1d 1 S Za Zb Zc Zd VCC = PIN 16 GND = PIN 8 CONNECTION DIAGRAM DIP (TOP VIEW) VCC E I0c I1c Zc I0d I1d Zd NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package S I0a I1d Za I0b I1b Zb GND
14 LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d E S Za Zb Zc Zd VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TRUTH TABLE ENABLE SELECT INPUT INPUTS OUTPUT E S I0 I1 Z H X X X L L H X L L L H X H H L L L X L L L H X H H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care
15 74LS151 Multiplexor 1 entre 8 Connection Diagram Truth Table Select Inputs Strobe C B A S H = HIGH Level L = LOW Level X = Don't Care D0, D1...D7 = the level of the respective D input Y Outputs X X X H L H L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 W
16 Logic Diagrams See Address Buffers Address Buffers
17 COMPARADOR 74LS85 Comparador binario de 4 bits Connection Diagram Function Table Comparing Cascading Outputs Inputs Inputs A3, B3 A2, B2 A1, B1 A0, B0 A > B A < B A = B A > B A < B A = B A3 > B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 > B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A3 = B3 A2 = B2 A1 > B1 X X X X H L L A3 = B3 A2 = B2 A1 < B1 X X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H H L H = HIGH Level, L = LOW Level, X = Don t Care
18 Logic Diagram
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