Photologic Sensor OPL530, OPL531, OPL535, OPL536, OPL550, OPL551, OPL560, OPL561, OPL562, OPL563
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- Kelley Charles
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1 Photologic Seor Features: Choice of four output optio in lowcost sidelooking package Choice of two seitivity optio (OPL60/61/62/63) High noise immunity Direct TTL/LSTTL CMOS interface Data rates to 20 kbaud for all except OPL60 series (200 kbaud) Low power coumption Product Photo Here Description: All components in this series include a photodiode, amplifier, voltage regulator, Schmitt trigger and NPN output traistor on a single silicon chip. OPL60 chips also include a voltage regulator on the chip. All devices in the series have a Photologic chip that is encapsulated in a molded plastic sidelooking package with an integral le (recessed integral le for OPL3 and OPL36). This packaging provides enhanced optical coupling, combined with mechanical protection. The hysteresis characteristics of the Schmitt trigger on each device offers high immunity to noise on input and CC. OPL30, OPL31, OPL3 and OPL36 include a 10 K Ω pullup resistor (R L ) from output to CC. These components exhibit very stable performance over supply voltages ranging from 4. to 16 and a wide range of irradiance levels. OPL0 and OPL1 devices feature TTL/LSTTL compatible logic level output which can drive up to 8 TTL loads without additional circuitry and mediumspeed data rates to 20 kbaud, with typical rise and fall times of 2 nanoseconds. OPL60, OPL61, OPL62 and OPL63 devices feature TTL/LSTTL compatible logic level output which can drive up to 10 TTL loads over supply voltages ranging from 4. to 16. OPL30, OPL31, OPL0, OPL1, OPL60, OPL61, OPL62 and OPL63 are mechanically and spectrally matched to OP140 and OP240 LEDs. OPL3 and OPL36 are mechanically and spectrally matched to OP14 and OP24 series LEDs. Applicatio: Noncontact reflective object seor Assembly line automation Machine automation Machine safety End of travel seor Door seor Base Part Number Package Output Type with Light OPL30 OPL31 OPL3 OPL36 Internal 10K High Internal 10K Low Input Power Range ( ) [Min/Max] A B 0.08/ /.2 OPL0 Recessed Totem Pole High 0.2/ /1.4 OPL1 Le Totem Pole Low 0.2/2. 0.2/1. OPL60 OPL61 OPL62 OPL63 Internal 10K High Internal 10K Low Totem Pole High Totem Pole Low Totem Pole High Totem Pole Low 0.09/. 0.09/ / / /0.40 OC = Open Collector Output RoHS Phone: (972) or (800) FAX: (972) seors@optekinc.com Page 1 of 8
2 Photologic Seor OPL30, OPL0, OPL60 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC OPL3, OPL36 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC Page 2 of 8 Phone: (972) or (800) FAX: (972) seors@optekinc.com
3 Photologic Seor (OC, OCA, OCB) OPL0, OPL0A, OPL1, OPL1A, OPL60, OPL60A, OPL61, OPL61A, OPL62, OPL62A, OPL63, OPL63A OPL0/0A/60/60A/62/62A TotemPole OPL30/3/0/60/62 (OC, OCA, OCB) OpenCollector CC CC OPL 1/1A/61/61A/63/63A/ Inverted TotemPole OPL 31/36/1/61/63 (OC, OCA, OCB) Inverted OpenCollector CC CC OPL30, OPL30A, OPL30B, OPL31, OPL31A, OPL31B OPL3, OPL3A, OPL3B, OPL36, OPL36A, OPL36B OPL30/30A/30B, OPL3/3A/3B 10K PullUp OPL31/31A/31B, OPL36/36A/36B Inverted 10K PullUp CC CC CC CC Phone: (972) or (800) FAX: (972) Page 3 of 8
4 Photologic Seor Absolute Maximum Ratings (T A =2 C unless otherwise noted) Input Diode Supply oltage ( CC ) OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36, OPL36OC, OPL0, OPL1 Operating Temperature Range Storage Temperature Range C to + 8 C 40 C to + C Lead Soldering Temperature [1/16 inch (1.6mm) from the case for sec. with soldering iron] 260 C Sourcing Current Power Dissipation OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36, OPL36OC OPL0, OPL1, Sinking Current OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36, OPL36OC OPL0, OPL1 oltage at Output Lead (4) OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36, OPL36OC OPL0OC, OPL1OC OPL60OC, OPL61OC, OPL62OC, OPL63OC Duration of Output Short to CC or Ground OP0, OP1 Duration of Output Short to CC OPL0OC, OPL1OC, OPL60OC, OPL61OC, OPL62OC, OPL63OC Low Level Output Current High Level Output Current Irradiance OPL60, OPL60OC, OPL61, OPL61OC OPL62, OPL62OC, OPL63, OPL63OC mw 200 mw (2) second 1 second 1 second mw/cm 3 (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC, a maximum of 20 grams force may be applied to leads (2) Derate linearly 2.67 mw/ C above C for OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC. Derate linearly 2. mw/ C above 2 C for all devices in the OPL0, OPL1, OPL60, OPL61, OPL62 and (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ. Page 4 of 8 Phone: (972) or (800) FAX: (972) seors@optekinc.com
5 Photologic Seor Electrical Characteristics (T A = 2 C unless otherwise noted) SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS Operating Supply oltage OPL30, OPL30OC, OPL31, OPL31OC OPL3, OPL3OC, OPL36, OPL36OC, OPL60, OPL61 Series CC PeaktoPeak CC Ripple Necessary to Cause False Triggering of Output OPL30, OPL30OC, OPL31, OPL31OC OPL3, OPL3OC, OPL36, OPL36OC OPL60, OPL61 Series 2 f = DC to 0 MHz 2 CC = DC, f = DC to 0 MHz Supply Current (4) OPL30, OPL30OC, OPL31, OPL31OC OPL3, OPL3OC, OPL36, OPL36OC 2.7 E E = 0 or 1 I CC 8 1 E E = 0 or 3, CC =. OPL60, OPL61 Series 8 12 E E = 0 or 1 PositiveGoing Threshold Irradiance (3) OPL30, OPL30OC, OPL31, OPL31OC OPL3, OPL3OC, OPL36, OPL36OC T A = 2 C E et(+) OPL30A, OPL30OCA, OPL31A, OPL31OCA OPL3A, OPL3OCA, OPL36A, OPL36OCA T A = 2 C OPL30B, OPL30OCB, OPL31B, OPL31OCB OPL3B, OPL3OCB, OPL36B, OPL36OCB T A = 2 C OPL0, OPL0OC, OPL1, OPL1OC OPL0A, OPL0OCA, OPL1, OPL1OCA CC =, T A = 2 C CC =, T A = 2 C Hysteresis Ratio OP30, OP31 Series E et(+)/ E et() OP3, OP36 Series OPL60, OPL61 Series E et (+) ( T) Temperature Coefficient OPL30, OPL30OC, OPL31, OPL31OC OPL3, OPL3OC, OPL36, OPL36OC %/ C %/ C >0 C <0 C (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC, a maximum of 20 grams force may be applied to leads (2) Derate linearly 2.67 mw/ C above C for OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC. Derate linearly 2. mw/ C above 2 C for all devices in the OPL0, OPL1, OPL60, OPL61, OPL62 and (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ. Phone: (972) or (800) FAX: (972) seors@optekinc.com Page of 8
6 Photologic Seor Electrical Characteristics (T A = 2 C unless otherwise noted) SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS OH Operating Supply oltage OPL0 OPL1 OPL CC CC = 4., I OH = 800 µa, E E = 3 CC = 4., I OH = 800 µa, E E = 0 I OH = 1, E E = 1 OPL61 CC 2.1 I OH = 1, E E = 0 Low Level Output oltage OPL30, OPL30OC, OPL3, OPL3OC I OL = 16, E E = 0 OPL31, OPL31OC, OPL36, OPL36OC I OL = 16, E E = 1 OL OPL0 OPL1 OPL60, OPL60OC CC = 4., I OL = 12.8, E E = 0 CC = 4., I OL = 12.8, E E = 3 I OL = 16, E E = 0 OPL61, OPL61OC.4 I OL = 16, E E = 1 I OS Short Circuit Output Current OPL0 OPL CC =., Output =, E E = 3 CC =., Output =, E E = 0 High Level Output Current (4) OPL31, OPL31OC, OPL36, OPL36OC OH = 30, E E = 0 OPL3, OPL3OC, OPL30, OPL30OC OH = 30, E E = 1 I OH OPL0OC OPL1OC OPL60OC 1 1 CC = 4., OH = 30, E E = 3 CC = 4., OH = 30, E E = 0 OH = 30, E E = 1 OPL61OC OH = 30, E E = 0 (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC, a maximum of 20 grams force may be applied to leads (2) Derate linearly 2.67 mw/ C above C for OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC. Derate linearly 2. mw/ C above 2 C for all devices in the OPL0, OPL1, OPL60, OPL61, OPL62 and (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ. Page 6 of 8 Phone: (972) or (800) FAX: (972) seors@optekinc.com
7 Photologic Seor Electrical Characteristics (T A = 2 C unless otherwise noted) SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS Output Rise Time OPL30, OPL31, OPL3, OPL36 1. E E = 0 or 1, C L = 0 pf t r OPL30OC, OPL31OC, OPL3OC, OPL36OC OPL0, OPL1 OPL0OC, OPL1OC OPL60, OPL61 OPL60OC, OPL61OC 0 2 2, C L = 0 Pf CC =, T A = 2 C, E E = 0 or 3, f = 10 khz, DC = 0% RL = 8 TTL loads CC =, T A = 2 C, E E = 0 or 3, f = 10 khz, DC = 0%, R L = 360 Ω T A = 2 C, E E = 0 or 1, f = 10 khz, DC = 0%, R L = 360 Ω t r Output Rise Time OPL30, OPL31, OPL3, OPL36 OPL30OC, OPL31OC, OPL3OC, OPL36OC OPL0OC, OPL1OC OPL60OC, OPL61OC OPL60, OPL61 OPL60OC, OPL61OC 2 E E = 0 or 1, C L = 0 pf, C L = 0 pf CC =, T A = 2 C, E E = 0 or 3, R L = 8 TTL loads, f = 10 khz, DC = 0% CC =, T A = 2 C, E E = 0 or 3, R L = 8 TTL loads, f = 10 khz, DC = 0% T A = 2 C, E E = 0 or 1, f = 10 khz T A = 2 C, E E = 0 or 1, f = 10 khz Output Fall Time OPL30, OPL31, OPL3, OPL36 20 E E = 0 or 1, C L = 0 Pf t f OPL30OC, OPL31OC, OPL3OC, OPL36OC OPL0OC, OPL1OC OPL60, OPL61 OPL60OC, OPL61OC 20 2, C L = 0 pf CC =, T A = 2 C, E E = 0 or 3, R L = 360 Ω, f = 10 khz, DC = 0% T A = 2 C, E E = 0 or 1, f = 10 khz T A = 2 C, E E = 0 or 1, f = 10 khz (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC, a maximum of 20 grams force may be applied to leads (2) Derate linearly 2.67 mw/ C above C for OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC. Derate linearly 2. mw/ C above 2 C for all devices in the OPL0, OPL1, OPL60, OPL61, OPL62 and (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ. Phone: (972) or (800) FAX: (972) seors@optekinc.com Page 7 of 8
8 Photologic Seor Electrical Characteristics (T A = 2 C unless otherwise noted) SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONS tpe et (+) Propagation Delay OPL30, OPL31, OPL3, OPL36 OPL30OC, OPL31OC, OPL3OC, OPL36OC OPL0OC, OPL1OC , C L = 0 pf, C L = 0 pf CC =, T A = 2 C, E E = 0 or 3, R L = 8 TTL loads, f = 10 khz, DC = 0% tpe et () Propagation Delay OPL30, OPL31, OPL3, OPL36, OPL30OC, OPL31OC, OPL3OC, OPL36OC OPL0OC, OPL1OC , C L = 0 pf CC =, T A = 2 C, E E = 0 or 3, R L = 360 Ω, f = 10 khz, DC = 0% t PLH, T PHL Propagation Delay (LowHigh/HighLow) OPL60, OPL61 DC = 0%, R L = 10 TTL Loads OP60OC, OPL61OC DC = 0%, R L = 300 Ω (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC, a maximum of 20 grams force may be applied to leads (2) Derate linearly 2.67 mw/ C above C for OPL30, OPL30OC, OPL31, OPL31OC, OPL3, OPL3OC, OPL36 and OPL36OC. Derate linearly 2. mw/ C above 2 C for all devices in the OPL0, OPL1, OPL60, OPL61, OPL62 and (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ. Page 8 of 8 Phone: (972) or (800) FAX: (972) seors@optekinc.com
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8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
Presettable Counters High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup
MM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent
Hi-Reliability Optically Coupled Isolator
HiReliability Optically Coupled Isolator Features: TO78 hermetically sealed package High current transfer ratio 1 k electrical isolation Base contact provided for conventional transistor biasing TX and
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
Dual 4-Input Data Selector/Multiplexer High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C153A Dual 4-Input Data Selector/Multiplexer igh-performance Silicon-ate CMOS The IN74C153A is identical in pinout to the LS/ALS153. The device inputs are compatible with standard CMOS
Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
Hex 3-State Noninverting Buffer with Common Enables High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C365A ex 3-State Noninverting Buffer with Common Enables igh-performance Silicon-ate CMOS The IN74C365A is identical in pinout to the LS/ALS365. The device inputs are compatible with
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
74VHC139 Dual 2-to-4 Decoder/Demultiplexer
74HC139 Dual 2-to-4 Decoder/Demultiplexer General Description Ordering Code: November 1992 Revised April 1999 The HC139 is an advanced high speed CMOS Dual 2-to- 4 Decoder/Demultiplexer fabricated with
HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
DESCRIPTION The / optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
MM54HC148 MM74HC Line Priority Encoder
MM54HC148 MM74HC148 8-3 Line Priority Encoder General Description This priority encoder utilizes advanced silicon-gate CMOS technology It has the high noise immunity and low power consumption typical of
8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C251A 8-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C251A is identical in pinout to the LS/ALS251. The device inputs are compatible with
CD4028BC BCD-to-Decimal Decoder
CD4028BC BCD-to-Decimal Decoder General Description The CD4028BC is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
MM74C221 Dual Monostable Multivibrator
MM74C221 Dual Monostable Multivibrator General Description The MM74C221 dual monostable multivibrator is a monolithic complementary MOS integrated circuit. Each multivibrator features a negative-traition-triggered
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
Octal 3-State Inverting Transparent Latch High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C33A Octal 3-State Inverting Traparent Latch igh-performance Silicon-ate CMOS The IN74C33A is identical in pinout to the LS/ALS33. The device inputs are compatible with standard CMOS
74VHC138 3-to-8 Decoder/Demultiplexer
74HC138 3-to-8 Decoder/Demultiplexer General Description The HC138 is an advanced high speed CMOS 3-to-8 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation
CD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CD4093BC Quad 2-Input NAND Schmitt Trigger
CD4093BC Quad 2-Input NAND Schmitt Trigger General Description The CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a 2-input NAND gate with Schmitttrigger action on both inputs.
74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed
Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC193A Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The IN74HC193A is identical in pinout to the LS/ALS193. The device inputs are compatible with standard
MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter
4-Bit Decade Counter 4-Bit Binary Counter General Description The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
HIGH SPEED TRANSISTOR OPTOCOUPLERS
SINGLECHANNEL: PACKAGE SCHEMATIC N/C V CC + V CC V F + V F 7 V B _ 7 V 0 _ V O _ V 0 V F N/C 4 5 GND + 4 5 GND,,, Pin 7 is not connected in Part Number / DESCRIPTION The /, / and / optocouplers consist
Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00
TECHNICAL DATA IW027B Dual JK Flip-Flop The IW027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and traferred
MM54C14 MM74C14 Hex Schmitt Trigger
MM54C14 MM74C14 Hex Schmitt Trigger General Description The MM54C14 MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement
74VHC393 Dual 4-Bit Binary Counter
Dual 4-Bit Binary Counter General Description March 1993 Revised March 1999 The HC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C244A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver igh-performance Silicon-ate CMOS The IN74C244A is identical in pinout to the LS/ALS244. The device inputs are compatible
74VHC74 Dual D-Type Flip-Flop with Preset and Clear
74HC74 Dual D-Type Flip-Flop with Preset and Clear General Description Ordering Code: October 1992 Revised March 1999 The HC74 is an advanced high speed CMOS Dual D- Type Flip-Flop fabricated with silicon
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear
MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear General Description These J-K Flip-Flops utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power dissipation of
Dual J-K Flip-Flop with Set and Reset
TECNICAL DATA IN74C109A Dual J-K Flip-Flop with Set and Reset igh-performance Silicon-ate CMOS The IN74C109A is identical in pinout to the LS/ALS109. The device inputs are compatible with standard CMOS
74LS240 / 74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
74LS240 / 74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board deity of 3-STATE buffers/ drivers