Base Part Number Package Output Type - with Light. Internal 10K - High Internal 10K - Low Internal 10K - High Internal 10K - Low.
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- Noreen Joseph
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1 Choice of four output optio in lowcost sidelooking package Choice of two seitivity optio (OPL560/561/562/563) High noise immunity Direct TTL/LSTTL CMOS interface Data rates to 250 kbaud for all except OPL560 series (200 kbaud) Low power coumption All components in this series include a photodiode, amplifier, voltage regulator, Schmitt trigger and NPN output traistor on a single silicon chip. OPL560 chips also include a voltage regulator on the chip. All devices in the series have a Photologic chip that is encapsulated in a molded plastic sidelooking package with an integral le (recessed integral le for OPL535 and OPL536). This packaging provides enhanced optical coupling, combined with mechanical protection. The hysteresis characteristics of the Schmitt trigger on each device offers high immunity to noise on input and CC. OPL530, OPL531, OPL535 and OPL536 include a 10 K Ω pullup resistor (R L ) from output to CC. These components exhibit very stable performance over supply voltages ranging from 4.5 to 16 and a wide range of irradiance levels. OPL550 and OPL551 devices feature TTL/LSTTL compatible logic level output which can drive up to 8 TTL loads without additional circuitry and mediumspeed data rates to 250 kbaud, with typical rise and fall times of 25 nanoseconds. OPL560, OPL561, OPL562 and OPL563 devices feature TTL/LSTTL compatible logic level output which can drive up to 10 TTL loads over supply voltages ranging from 4.5 to 16. OPL530, OPL531, OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 are mechanically and spectrally matched to OP140 and OP240 LEDs. OPL535 and OPL536 are mechanically and spectrally matched to OP145 and OP245 series LEDs. Noncontact reflective object seor Assembly line automation Machine automation Machine safety End of travel seor Door seor Base Part Number Package Output Type with Light OPL530 OPL531 OPL535 OPL536 OPL550 External Le Recessed Le External Le Internal 10K High Internal 10K Low Internal 10K High Internal 10K Low Input Power Range (mw/cm 2 ) [Min/Max] A B 0.08/ / /0.40 Totem Pole High 0.25/ /1.4 OPL551 Totem Pole Low 0.25/ /1.5 OPL560 OPL561 OPL562 OPL563 Totem Pole High Totem Pole Low Totem Pole High Totem Pole Low OC = Open Collector Output N/A 0.09/ / / / / /0.23 RoHS
![OPL530, OPL550, OPL560 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC Pin # Seor 1 Ground 2 Output](/docs-images/78/77605667/images/2-10.jpg "3 cc OPL535, OPL536 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC Pin # Seor 1 Ground 2 Output 3")
2 OPL530, OPL550, OPL560 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC Pin # Seor 1 Ground 2 Output 3 cc OPL535, OPL536 Series DIMENSIONS ARE IN: [ MILLIMETERS] INCHES Pin # Seor 1 Ground 2 Output 3 CC Pin # Seor 1 Ground 2 Output 3 cc
3 OPL530, OPL531, OPL535, OPL536, OPL550, OPL551, OPL560, OPL561, OPL562, OPL563 (OC, OCA, OCB) OPL550, OPL550A, OPL551, OPL551A, OPL560, OPL560A, OPL561, OPL561A, OPL562, OPL562A, OPL563, OPL563A OPL550/550A/560/560A/562/562A TotemPole OPL530/535/550/560/562 (OC, OCA, OCB) OpenCollector CC CC OPL 551/551A/561/561A/563/563A/ Inverted TotemPole OPL 531/536/551/561/563 (OC, OCA, OCB) Inverted OpenCollector CC CC
4 OPL530, OPL530A, OPL530B, OPL531, OPL531A, OPL531B OPL535, OPL535A, OPL535B, OPL536, OPL536A, OPL536B OPL530/530A/530B, OPL535/535A/535B 10K PullUp OPL531/531A/531B, OPL536/536A/536B Inverted 10K PullUp CC CC CC CC
5 Supply oltage ( CC ) OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536, OPL536OC, OPL550, OPL551 OPL560, OPL561, OPL562, OPL563 Operating Temperature Range Storage Temperature Range C to + 85 C 40 C to + C Lead Soldering Temperature [1/16 inch (1.6mm) from the case for 5 sec. with soldering iron] 260 C Sourcing Current OPL560, OPL561, OPL562, OPL563 Power Dissipation OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536, OPL536OC OPL550, OPL551, OPL560, OPL561, OPL562, OPL563 Sinking Current OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536, OPL536OC OPL550, OPL551 OPL560, OPL561, OPL562, OPL563 oltage at Output Lead (4) OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536, OPL536OC OPL550OC, OPL551OC OPL560OC, OPL561OC, OPL562OC, OPL563OC Duration of Output Short to CC or Ground OP550, OP551 Duration of Output Short to CC OPL550OC, OPL551OC OPL560, OPL561, OPL562, OPL563, OPL560OC, OPL561OC, OPL562OC, OPL563OC Low Level Output Current High Level Output Current Irradiance OPL560, OPL560OC, OPL561, OPL561OC OPL562, OPL562OC, OPL563, OPL563OC 10 ma 90 mw 200 mw (2) 50 ma 50 ma second 1 second 1 second 16 ma 1 ma 10 mw/cm 2 9 mw/cm 3 mw/cm 2 Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC, a maximum of 20 grams force may be applied to leads while at soldering temperatures. (2) Derate linearly 2.67 mw/ C above C for OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC. Derate linearly 2.5 mw/ C above 25 C for all devices in the OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 series. (3) Irradiance measurements are made with λi = 935 nm. (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ.
6 Operating Supply oltage OPL530, OPL530OC, OPL531, OPL531OC OPL535, OPL535OC, OPL536, OPL536OC, OPL560, OPL561 Series CC PeaktoPeak CC Ripple Necessary to Cause False Triggering of Output OPL530, OPL530OC, OPL531, OPL531OC OPL535, OPL535OC, OPL536, OPL536OC OPL560, OPL561 Series 2 f = DC to 50 MHz 2 CC = 5 DC, f = DC to 50 MHz Supply Current (4) OPL530, OPL530OC, OPL531, OPL531OC OPL535, OPL535OC, OPL536, OPL536OC ma E E = 0 or 1 mw/cm 2 I CC 8 15 ma E E = 0 or 3 mw/cm 2, CC = 5.5 OPL560, OPL561 Series 8 12 ma E E = 0 or 1 mw/cm 2 PositiveGoing Threshold Irradiance (3) OPL530, OPL530OC, OPL531, OPL531OC OPL535, OPL535OC, OPL536, OPL536OC mw/cm 2 T A = 25 C E et(+) OPL530A, OPL530OCA, OPL531A, OPL531OCA OPL535A, OPL535OCA, OPL536A, OPL536OCA mw/cm 2 T A = 25 C OPL530B, OPL530OCB, OPL531B, OPL531OCB OPL535B, OPL535OCB, OPL536B, OPL536OCB mw/cm 2 T A = 25 C OPL550, OPL550OC, OPL551, OPL551OC OPL550A, OPL550OCA, OPL551, OPL551OCA mw/cm 2 mw/cm 2 CC = 5, T A = 25 C CC = 5, T A = 25 C
7 Hysteresis Ratio OP530, OP531 Series E et(+)/ E et() OP535, OP536 Series E et (+)( T) OPL560, OPL561 Series Temperature Coefficient OPL530, OPL530OC, OPL531, OPL531OC OPL535, OPL535OC, OPL536, OPL536OC 1.20 Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC, a maximum of 20 grams force may be applied to leads while at soldering temperatures. (2) Derate linearly 2.67 mw/ C above C for OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC. Derate linearly 2.5 mw/ C above 25 C for all devices in the OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 series. (3) Irradiance measurements are made with λi = 935 nm. (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ %/ C %/ C >0 C <0 C
8 OH Operating Supply oltage OPL550 OPL551 OPL CC CC = 4.5, I OH = 800 µa, E E = 3 mw/cm 2 CC = 4.5, I OH = 800 µa, E E = 0 I OH = 1, E E = 1 mw/cm 2 OPL561 CC 2.1 I OH = 1, E E = 0 Low Level Output oltage OPL530, OPL530OC, OPL535, OPL535OC I OL = 16 ma, E E = 0 OPL531, OPL531OC, OPL536, OPL536OC I OL = 16 ma, E E = 1 mw/cm 2 OL OPL550 OPL551 OPL560, OPL560OC CC = 4.5, I OL = 12.8 ma, E E = 0 CC = 4.5, I OL = 12.8 ma, E E = 3 mw/cm 2 I OL = 16 ma, E E = 0 OPL561, OPL561OC.4 I OL = 16 ma, E E = 1 mw/cm 2 I OS Short Circuit Output Current OPL550 OPL ma ma CC = 5.5, Output =, E E = 3 mw/cm 2 CC = 5.5, Output =, E E = 0 High Level Output Current (4) OPL531, OPL531OC, OPL536, OPL536OC OH = 30, E E = 0 OPL535, OPL535OC, OPL530, OPL530OC OH = 30, E E = 1 mw/cm 2 I OH OPL550OC OPL551OC OPL560OC 1 1 CC = 4.5, OH = 30, E E = 3 mw/cm 2 CC = 4.5, OH = 30, E E = 0 OH = 30, E E = 1 mw/cm 2 OPL561OC OH = 30, E E = 0 Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC, a maximum of 20 grams force may be applied to leads while at soldering temperatures. (2) Derate linearly 2.67 mw/ C above C for OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC. Derate linearly 2.5 mw/ C above 25 C for all devices in the OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 series. (3) Irradiance measurements are made with λi = 935 nm. (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ.
9 Output Rise Time OPL530, OPL531, OPL535, OPL E E = 0 or 1 mw/cm 2, C L = 50 pf t r OPL530OC, OPL531OC, OPL535OC, OPL536OC OPL550, OPL551 OPL550OC, OPL551OC OPL560, OPL561 OPL560OC, OPL561OC E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 Pf CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, f = 10 khz, DC = 50% RL = 8 TTL loads CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, f = 10 khz, DC = 50%, R L = 360 Ω T A = 25 C, E E = 0 or 1 mw/cm 2, f = 10 khz, DC = 50%, R L = 360 Ω Output Rise Time OPL530, OPL531, OPL535, OPL536 E E = 0 or 1 mw/cm 2, C L = 50 pf OPL530OC, OPL531OC, OPL535OC, OPL536OC E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 pf t r OPL550OC, OPL551OC OPL560OC, OPL561OC OPL560, OPL561 OPL560OC, OPL561OC 25 CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, R L = 8 TTL loads, f = 10 khz, DC = 50% CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, R L = 8 TTL loads, f = 10 khz, DC = 50% T A = 25 C, E E = 0 or 1 mw/cm 2, f = 10 khz T A = 25 C, E E = 0 or 1 mw/cm 2, f = 10 khz Output Fall Time OPL530, OPL531, OPL535, OPL E E = 0 or 1 mw/cm 2, C L = 50 Pf OPL530OC, OPL531OC, OPL535OC, OPL536OC 20 E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 pf t f OPL550OC, OPL551OC OPL560, OPL561 OPL560OC, OPL561OC 25 CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, R L = 360 Ω, f = 10 khz, DC = 50% T A = 25 C, E E = 0 or 1 mw/cm 2, f = 10 khz T A = 25 C, E E = 0 or 1 mw/cm 2, f = 10 khz Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC, a maximum of 20 grams force may be applied to leads while at soldering temperatures. (2) Derate linearly 2.67 mw/ C above C for OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC. Derate linearly 2.5 mw/ C above 25 C for all devices in the OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 series. (3) Irradiance measurements are made with λi = 935 nm. (4) This applies to OC versio only. For I CC on pullup versio, add CC/10 KΩ.
10 tpe et (+) Propagation Delay OPL530, OPL531, OPL535, OPL536 OPL530OC, OPL531OC, OPL535OC, OPL536OC OPL550OC, OPL551OC E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 pf E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 pf CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, R L = 8 TTL loads, f = 10 khz, DC = 50% tpe et () Propagation Delay OPL530, OPL531, OPL535, OPL536, OPL530OC, OPL531OC, OPL535OC, OPL536OC 3.0 E E = 0 or 1 mw/cm 2, RL = 300 Ω to 5, C L = 50 pf OPL550OC, OPL551OC CC = 5, T A = 25 C, E E = 0 or 3 mw/cm 2, R L = 360 Ω, f = 10 khz, DC = 50% t PLH, T PHL Propagation Delay (LowHigh/HighLow) OPL560, OPL561 5 DC = 50%, R L = 10 TTL Loads OP560OC, OPL561OC 5 DC = 50%, R L = 300 Ω Notes: (1) RMA flux is recommended. Duration can be extended to 10 sec. max. when flow soldering. For OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC, a maximum of 20 grams force may be applied to leads while at soldering temperatures. (2) Derate linearly 2.67 mw/ C above C for OPL530, OPL530OC, OPL531, OPL531OC, OPL535, OPL535OC, OPL536 and OPL536OC. Derate linearly 2.5 mw/ C above 25 C for all devices in the OPL550, OPL551, OPL560, OPL561, OPL562 and OPL563 series. (3) Irradiance measurements are made with λi = 935 nm. (4) This applies to OC versio only. For I CC on pullup versio, add CC /10 KΩ.
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Quad 2-Input AND Gate General Description The MM74HC08 AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
Dual 4-Input Data Selector/Multiplexer High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C153A Dual 4-Input Data Selector/Multiplexer igh-performance Silicon-ate CMOS The IN74C153A is identical in pinout to the LS/ALS153. The device inputs are compatible with standard CMOS
MM74HC32 Quad 2-Input OR Gate
Quad 2-Input OR Gate General Description The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
Hex 3-State Noninverting Buffer with Common Enables High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C365A ex 3-State Noninverting Buffer with Common Enables igh-performance Silicon-ate CMOS The IN74C365A is identical in pinout to the LS/ALS365. The device inputs are compatible with
Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00
TECHNICAL DATA IW027B Dual JK Flip-Flop The IW027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and traferred
8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C251A 8-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C251A is identical in pinout to the LS/ALS251. The device inputs are compatible with
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. CD4020BC CD4040BC CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed
Octal 3-State Inverting Transparent Latch High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C33A Octal 3-State Inverting Traparent Latch igh-performance Silicon-ate CMOS The IN74C33A is identical in pinout to the LS/ALS33. The device inputs are compatible with standard CMOS
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC193A Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The IN74HC193A is identical in pinout to the LS/ALS193. The device inputs are compatible with standard
MM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent
NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
HIGH SPEED TRANSISTOR OPTOCOUPLERS
SINGLECHANNEL: PACKAGE SCHEMATIC N/C V CC + V CC V F + V F 7 V B _ 7 V 0 _ V O _ V 0 V F N/C 4 5 GND + 4 5 GND,,, Pin 7 is not connected in Part Number / DESCRIPTION The /, / and / optocouplers consist
MM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CD4093BC Quad 2-Input NAND Schmitt Trigger
CD4093BC Quad 2-Input NAND Schmitt Trigger General Description The CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a 2-input NAND gate with Schmitttrigger action on both inputs.
CD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter
MM74HC4020 MM74HC4040 14-Stage Binary Counter 12-Stage Binary Counter General Description The MM54HC4020/MM74HC4020, MM54HC4040/ MM74HC4040, are high speed binary ripple carry counters. These counters
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed
MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter
4-Bit Decade Counter 4-Bit Binary Counter General Description The MM74C90 decade counter and the MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel
CD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C244A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver igh-performance Silicon-ate CMOS The IN74C244A is identical in pinout to the LS/ALS244. The device inputs are compatible
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard
Dual J-K Flip-Flop with Set and Reset
TECNICAL DATA IN74C109A Dual J-K Flip-Flop with Set and Reset igh-performance Silicon-ate CMOS The IN74C109A is identical in pinout to the LS/ALS109. The device inputs are compatible with standard CMOS
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or
HIGH SPEED TRANSISTOR OPTOCOUPLERS
DESCRIPTION The HCPL05XX, and HCPL04XX optocouplers consist of an AlGaAs LED optically coupled to a high speed photodetector transistor housed in a compact pin small outline package. A separate connection
Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL Compatible Inputs The is a single gate CMOS Schmitt trigger inverter fabricated with silicon gate CMOS technology. It achieves high speed operation
74LS240 / 74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
74LS240 / 74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board deity of 3-STATE buffers/ drivers
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
74VHC393 Dual 4-Bit Binary Counter
Dual 4-Bit Binary Counter General Description March 1993 Revised March 1999 The HC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
Dual D Flip-Flop with Set and Reset
TECNICAL DATA IN74C74A Dual D Flip-Flop with Set and Reset The IN74C74A is identical in pinout to the LS/ALS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
DESCRIPTION The / optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline
74VHC74 Dual D-Type Flip-Flop with Preset and Clear
74HC74 Dual D-Type Flip-Flop with Preset and Clear General Description Ordering Code: October 1992 Revised March 1999 The HC74 is an advanced high speed CMOS Dual D- Type Flip-Flop fabricated with silicon
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
74VHC138 3-to-8 Decoder/Demultiplexer
74HC138 3-to-8 Decoder/Demultiplexer General Description The HC138 is an advanced high speed CMOS 3-to-8 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
CD4028BC BCD-to-Decimal Decoder
CD4028BC BCD-to-Decimal Decoder General Description The CD4028BC is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to
MM74C221 Dual Monostable Multivibrator
MM74C221 Dual Monostable Multivibrator General Description The MM74C221 dual monostable multivibrator is a monolithic complementary MOS integrated circuit. Each multivibrator features a negative-traition-triggered
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP