Interconnect Power and Delay Optimization by Dynamic Programming in Gridded Design Rules

Transcription

1 Interconnect Power and Delay Optimization by Dynamic Programming in Gridded Design Rules Konstantin Moiseev, Avinoam Kolodny EE Dept. Technion, Israel Institute of Technology Shmuel Wimer Eng. School, Bar-Ilan University March 2010 ISPD

2 Agenda What is the problem? Results for 32nm design It is NP complete Optimal solution by dynamic programming How it works in practice Further research problems March 2010 ISPD

3 Interconnect Power and Delay line-to-line coupling line-to-line coupling signal's activity, 0<= AF <=1 Line-to-line coupling is dynamic power killer Using Elmore delay model, simple, inaccurate but with high fidelity March 2010 ISPD

4 Interconnect Bus Model S i W i S i+1 L A March 2010 ISPD

5 Delay and Dynamic Power Minimization Delay: (,, ) i i D i si 1 wi si αi βiwi δi w i w i s µ µ i 1 si α, β, γ, δ, ε - technology parameters, driver's i i i i i γ ε 1 1 = resistance, capacitive load and bus length L. Dynamic power: 1 1 P ( s, w, s ) = κ w + η + i i 1 i i i i i µ µ si 1 si i i L κ, η - technology parameters, signal's activity, and bus length. March 2010 ISPD

6 Minimize delay: Minimize power: Formulation of the Problem (,, ) o r max max (,, ) D sum n = D s w s D D s w s i 1 i i 1 i i = = i i 1 i i 1 i n n i (,, ) P= = P s w s 1 i i 1 i i Subject to Constrained area: In 32nm and 22nm: n n w + s = A i= 1 i i= 0 i { } { } 1,...,, 1,..., s S S w W W i p i q Discrete optimization: problem is NP-complete Dynamic programming works March 2010 ISPD

7 Power-Delay Shape Function March 2010 ISPD

8 Results Obtained for 32nm Implemented in C++ / OpenAccess Ran on 32nm control blocks of Intel mobile processor Routed by Synopsys tool Width and space re-allocated in metal 2, 3 and 4 Used effective drivers and loads from netlist Typical block size was 250u X 250u Both dynamic power and delays are reduced 10%-15% dynamic power reduction Per optimized layer 2% - 5% delay reduction March 2010 ISPD

9 MIN_DLYPWR Problem Question : Is there a setting of widths and spaces such that delay reduction from base is δ D at least, while power increase from base is δ P at most? MIN_DLYPWR is NPC by polynomial reduction of PARTITION, which attemps to answer whether for a ( ) + given set B whose elements have size s b, b B, ( ) = s( b) there's a subset satisfying s b. b B b B B March 2010 ISPD

10 MIN_MAX_DLYPWR Problem Question : Is there a setting of widths and spaces such that power decrease from base power is at least δ P while maximal delay is increasing by δ D at most? MIN_MAX_PWRDLY is NPC by polynomial reduction of SUBSET_SUM which answers whether for ( ) ( ) whose + + elements have size s b, and diven a number N, there is B B satisfying s b = N. b B B March 2010 ISPD

11 Dynamic Programming Solution ( n) Delay is additive: D 1, ( 1, ) ( 1, ) D( j) D( j+ n) D j + D j+ n = max 1,, 1, { } ( ) = ( ) + ( + ) Power is additive P 1, n P 1, j P j 1, n ( ) ( j j = ) i= 0 i + i= 0 i Area is additive A jn, A w s Minimization of power and delay from j+1 to n is independent of power and delay from 1 to j. This suggests dynamic programming. Algorithm generates only essential (P,D) pairs in progression from wire to wire. March 2010 ISPD

12 Power-Delay Solution Space D D=D 0 P min P max P Dynamic Programming finds the red curve progressively. Optimal solution is derived from solution space of last wire. March 2010 ISPD

13 State Definition for Dynamic Programming area left for n-(j+1) wires accumulated delay A( j+ 1, n), s, ( ( 1, ), ), ( ( 1, ), ) j D A j+ n sj P A j+ n s j rightmost allocated space accumulated power March 2010 ISPD

14 State Dominancy and Redundancy Allocation ( w s w s ) ω :,,...,, 0 0 j j is dominating allocation ( w s w s ) ω :,,...,, 0 0 j j if A ( ) ( ) j j j j s + w A s + = 0 i= 0 i i= 0 i i= i i w 0 i s j s j and ( ω ) (. ω ) ( ω ) ( ω ) D D P P March 2010 ISPD

15 Stage Progression and State Augmentation stage wire j Λ j stage Λ j+1 wire j+1 Width and space allocations of next wire March 2010 ISPD

16 Theorem (optimality): Stage Λ n of the DP algorithm contains all the feasible non-redundant, and hence optimal, power-delay pairs that can be obtained by any width and space allocation to n wires Theorem: Any power-delay function f ( PD, ) monotonically increasing in and achieves minimum on the boundary of the P D power-delay feasible region. March 2010 ISPD

17 Modeling Real Layout u 0 u n+1 Use transitive reduction of wire visibility graph Design rules are transitively closed Process wires from left to right in topological order with appropriate enhancement to power-delay calculations March 2010 ISPD

18 Time and Storage ( α+ β 3 log ε ) O pq n n Time complexity: α and β are max in-degree and out-degree, respectively, of wire adjacency graph vertex Storage complexity: ( β 3 ε ) O q n Time and storage in practice are manageable due to power grid which decomposes the problem into many independent smaller problems. March 2010 ISPD

19 Further Research Directions Filling aware optimization Dynamic programming can generate filling patterns! Line-to-line capacitance can be measured on the spot Current algorithm works on P&R style only Enhancement for full-custom design style Cross-hierarchy dynamic programming Is bang-bang sizing possible? Using two values only is tremendous for litho! Simultaneous cell and interconnect resizing Use cell families with same footprint March 2010 ISPD

20 Thank You! March 2010 ISPD

21 Backup March 2010 ISPD

22 NP Completeness Proof of Delay Sum It is NP since any substitution of valid guess into delay and power equations can be checked for YES or NO answer. Reduction of PARTITION into MIN_DLYPWR: 1. A wire is allocated for every element of PARTITION. 2. Resistance of drivers and wires are set to 0 and 1, resp., hence wire resistance is not affecting delays. March 2010 ISPD

23 Coeficients in delay and power equations are set to zero or one, except load and activity, yielding: D = C w and P = Fw. b b b b b b 3. Only one spacing is allowed, hence not affecting the problem. 4. Only two width values are allowed W, W. 5. Bus area is set sufficiently large, hence not affecting the problem. { } 1 2 March 2010 ISPD

24 ( ) ( ) 6. Activity factors are set to s b W W. 2 1 ( ) ( ) Capacitive loads are set s b WW W W ( ) ( ) sum Delay turns into: D = 1 w s( b) WW W W, b B ( ) Power turns into: P= wsb ( ) W W. b B b b Bounds of power increase and delay reduction are set to δ P= δ D= s( b) 2. b B Transformation consumes polynomial time. March 2010 ISPD

25 Let the answer to f ( I) of MIN_DLYPWR be YES. ( ) Instance f I is set such that P increases and D decreases in w. There's single P and D where: b B b b B b b B ( ) δd = δp = s b ( ) ( s b ) We obtained 2 b B 1 1 WW s b = W W W W ( ) s( b) b B b B ( B B B ) = δ D = b B implying that, solves PARTITION. b, March 2010 ISPD

26 Conversely, let B B be a YES answer to PARTITION. Set width of w, b B, to W, and rest wires stay W. b 2 1 δ b = b( 1 2) = ( ) ( ) ( ) D reduction is D C 1 W 1 W s b, and P increase is δ P = F W W = s b b b 2 1 the MIN_DLYPWR problem. Q.E.D, thus yielding a YES answer to March 2010 ISPD

27 NP Completeness Proof of Max Delay Base delay and power are obtained by setting widths to W, resulting maximum power and minimum delay for each signal. Settings 1 to 5 of MIN _ MAX _ DLYPWR instance are similar to those of MIN _ DLYPWR proof. Base delays are increasing upon wire narrowing. Setting 6 in MIN_DLYPWR proof is modified such that load is set to b ( ) C = NWW W W, yielding: ( ) ( ) ( ) { } b max D = max N 1 w WW W W. b B March 2010 ISPD

28 For any b B, wire narrowing from W to W reduces ( ) 2 1 power by s b. Delay grows by δ D = N, so maximum b delay increase by N always. Setting 7 in MIN_DLYPWR proof turns to δp= δd= N. { } Consequently, δ P= δ D= N iff δ P = b max δ D = N b. b B b B This holds iff the answer to SUBSET _ SUM is YES. Q.E.D March 2010 ISPD