Announcements. EE141-Spring 2007 Digital Integrated Circuits. CMOS SRAM Analysis (Read/Write) Class Material. Layout. Read Static Noise Margin

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1 Vo l ta ge ri s e [ V] EE-Spring 7 Digital Integrated ircuits Lecture SRM Project Launch nnouncements No new labs next week and week after Use labs to work on project Homework #6 due Fr. pm Project updated by tomorrow Proj. Phase due Tu March by pm Proj. Phase due Tu pril by pm Homework #7 posted this weekend Due Fr March 3 by pm! lass Material Last lecture MOS Logic Optimization Memory, SRM Today s lecture SRM Decoders Reading (hapters, 6) MOS SRM nalysis (Read/Write) Voltage Rise (V) ell Ratio (R). 3 ( W / L) PR = ( W / L) 6 3 Read Static Noise Margin 6T-SRM Layout BL BLB Obtained by breaking the feedback between the inverters SNM GND WL ompact cell Bitlines: M Wordline: bootstrapped in M3 6

2 N wo rd s D e c od er 6nm SRM ST/Philips/Motorola ccess Transistor Pull down Pull up 7 8 rray-structured Memory rchitecture Decoders 9 Memory rchitecture: Decoders M bits M bits Row Decoders S S S Word Word Word Storage cell S Word Word Word Storage cell ollection of M complex logic gates Organized in regular and dense fashion (N)ND Decoder S N- S N- Word N- Word N- Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K- K = log N Word N- Word N- Input-Output (M bits) Decoder reduces the number of select signals K = log N WL = WL 7 3 = NOR Decoder WL =!( ) WL7 =! ( )

3 Hierarchical Decoders Multi-stage implementation improves performance WL WL NND decoder using -input pre-decoders x3 SRM Memory PROJET 6 Phase : 6T MOS SRM ell Design BL M WL M Q M Q M 6 M M 3 BL Objectives Minimize one (select and state) Power ccess time (R/W) onstraints (apply to all) SNM > mv ell area < 6µm. V max (no minimum). micron MOS 7 8

4 WL63 Phase : Row and olumn Decoder Project Phase WL WL SRM rray a a a3 a a a3 a a a See Fig. - 9 Project Goals and onstraints The importance of the project report hoose between two different goals Minimize delay (6µm max cell area) Minimize average energy (t a nsec max delay) Freedom in implementation choices Static logic Some constraints. V max (no minimum). micron MOS Limit of 3 pages to convince us that your project should get a Nobel prize (or at least a major award) Be concise and to the point Demonstrate clearly that your claims are true Express your motivations and your reasoning. Make sure to make it quantitative Be honest we will check your spice files and run them! 3

5 Recommended Reading Other recommendations hapter 6 and Do not start with optimization by simulation Think through the problem first and build a first-order analytical model to start DO NOT FORGET WIRING 6 Sizing Logic Paths for Speed Logical Effort Frequently, input capacitance of a logic path is constrained Logic has to drive some capacitance Example: LU load in an Intel s microprocessor is.pf How do we size the LU datapath to achieve maximum speed? We have already solved this for the inverter chain can we generalize it for any type of logic? 7 8 Buffer Example In Out N N L = N+ Delay = N ( + f i ) i = (in units of τ inv ) Delay = k R = τ ( p + g f ) unit unit L + γ in p intrinsic delay (3kR unit unit γ) - gate parameter f(w) g logical effort (kr unit unit ) gate parameter f(w) f electrical effort (effective fanout) For given N: i+ / i = i / i- To find N: i+ / i ~ How to generalize this to any logic path? f i = i+ / i 9 Normalize everything to an inverter: g inv =, p inv = Divide everything by τ inv (everything is measured in unit delays τ inv ) ssume γ =. 3

6 Delay in a Logic Gate gf Delay = k τ p + γ p parasitic delay - gate parameter f(w) g logical effort gate parameter f(w) f electrical effort (effective fanout) Gate delay: d = h + p effort delay intrinsic delay Effort delay: Normalize everything to an inverter: g inv =, p inv = Everything is measured in unit delays τ logical effort h = g f effective fanout = out / in 3 Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size 3 Inverter has the smallest logical effort and intrinsic delay of all static MOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity Logical effort is the ratio of input capacitance of a gate (input) to the input capacitance of an inverter with the same output current B F B F B B F 33 Inverter -input NND -input NOR g = g = /3 g = /3 3 of Gates of Gates Normalized delay (d) g= p= d= t pnnd tpinv g= p= d= Normalized delay (d) t pnnd g=/3 p= d=(/3)h+ tpinv g= p= d=h+ F(Fan-in) F(Fan-in) Fan-out (f) Fan-out (f) 3 36

7 of Gates dd Branching Effort Normalized Delay 3 Inverter: g = ; p = -input NND: g = /3; p = Effort Delay Intrinsic Delay Branching effort: b = on-path on path + on path off path 3 Fanout f 37 off-path 38 Multistage Networks Optimum Effort per Stage Delay = N ( pi + gi fi ) i = When each stage bears the same effort: h N = H Stage effort: h i = g i f i h = N H Path electrical effort: F = out / in Stage efforts: g f = g f = = g N f N Path logical effort: G = g g g N Effective fanout of each stage: f i = h g i Branching effort: B = b b b N Path effort: H = GFB Path delay D = Σd i = Σp i + Σh i Minimum path delay Dˆ = i / N ( g f + p ) = NH P i i + 39 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing D / N = NH i + p Remember: we can always add inverters to the end of the chain The best stage effort h = H / Nˆ is around (3.6 with γ=) From Sutherland, Sproull

8 Example: Optimize Path Example: Optimize Path a b c a b c g = f = a g = /3 f = b/a g = /3 f = c/b g = f = /c g = f = a g = /3 f = b/a g = /3 f = c/b g = f = /c Effective fanout, F = G = H = h = a = b = 3 Effective fanout, F = G = /9 H = /9 = 3.9 h =.93 a =.93 b = ha/g =.3 c = hb/g 3 = g /f =.9 Example 8-Input ND Next Lecture Wrap-up Ratioed Logic Pass-Transistor Logic 6