Am186CC/CH/CU Customer Development Platform Schematics. Main Board

Transcription

1 Table of ontents Page : over Sheet (OVR.SH) Page : m/h/h (M.SH) Page : onfiguration (ONFIGURTION.SH) Page : Memory : RM/ FLSH (MMORY.SH) Page : Memory : SRM/ROM (MMORY.SH) Page : HL Interface (Page ) (HL.SH) Page : HL Interface (Page ) (HL.SH) Page : HL Interface (Page ) (HL.SH) Page : URT (URT.SH) Page 0: US (US.SH) Page : ebug onnectors (UG/Q.SH) Page : xp., and TIP onnectors (XP/TI.SH) Page : aughter ard onnectors (UGHTR.SH) Page : Power Supply (POWR.SH) Page : Miscellaneous (MIS.SH) m/h/u ustomer evelopment Platform Schematics Rev.0: Rev.: Rev.0: Original design TMROUT0[PIO] changed to SRY[PIO]. Nets on ST s changed. Pull-ups and pull-downs added to MH. Pinouts corrected on diode and MOSFT on US page. RX[PIO] changed from TMRIN0[PIO]. V power changed to a switching regulator. Fuse changed to. Pinouts corrected on diode and flyback transformer on power page. Sheet : dd series terminators in 00 package. Removed TP, TP and TP. Sheet : Removed,,,, R0 and removed P TH- drawing. hanged R to. Updated tables and noted. Removed R-R. Sheet : hanged JP to x removing FLSHS#. Removed R0, R, R, R. Sheet : hanged JP & JP to JP & JP, respectively. Sheet : hanged HL L s circuit. hanged L part drawing. hanged label for. Sheet : hanged HL L s circuit. hanged L part drawing. hanged label for. Sheet : Modified tables. dded series terminators. Sheet : hanged URT L s circuit. dded series resistance to URT. hanged capacitors to 000pf. hanged label for. Sheet 0: Replaced U with TN000T dded 00K Pull-down to US detect circuit. hanged US L to PIO (RY). Removed and. dded unpopulated 0 Ohm resistors to US lines from transceiver. Modified L part drawing. Sheet : orrected picture to reflect analyzer configuration. Sheet : Removed R & R. Removed P and fixed illustration. Main oard Rev.0: Rev.: Sheet : dded net to V at P, pin for SL. hanged TIPSL to NTN on P. hanged SWIRQ to SHIRQ on P. Removed RYP on P. Removed TIP IRQ Jumpers and replace with 0 Ohm resistors. Sheet : hanged fuse part specification. Moved and and changed to 0.0uF. hanged U to a different part. hanged and to 0uF, YV, 0, V. hanged to two 0uF, -S, 0V caps. hanged 0 to three 0uF, -S, 0V caps. Sheet : dded 0K resistor to Sw, pin for Multidrop Mode. Removed RXHU from SW. Rearranged connections to SW. Sheet : dded USX# pinstrap control Sheet : hanged RS URT transceivers circuitry to support full flow control Sheet 0: hanged US attach/detach circuit Sheet : hanged TIP ethernet chip select dded RY to TIP connector () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) x. OVR.SH. ate: Tuesday, March 0, Sheet of

2 V V V V (,,,,) M[0..] These are series terminators used between the m and the Flash, SOJ SRM, RM, xpansion Interface, and TIP Interface. (,,,,) These are series terminators used between the m address bus and the SRM/ROM-I sockets to provide isolation from the other local data address routing. These are series terminators used between the m and the Flash, SOJ SRM, RM, xpansion Interface, and TIP Interface. These are series terminators used between the m data bus and the SRM/ROM-I sockets to provide isolation from the other local data bus routing. M0 M M M M M M M M M M0 M M M M M M M M M R0 R R R R R R R R R R0 R R R R R 0 Rev..0 R 0 R0 R R R00 R R0 R R R R 0 R R0 R R R R R R R R[0..] R0 R R R R R R R R R R0 R R R R R 0 R R R0 R R R 0 R R R R R R R R R R0 R R0 R R R R R R M[0..] M0 M M M M M M M M M M0 M M M R R R0 R R R R R R R R R R R 0 0 M R R[0..] M R R R R0 R R0 R R R R R R R R R R R m () () (,,) (,) () () (0,,,,) (,,,) (,,,) (,,,) (,,) (,,) (,,) (,,) PUX PUX LKOUT ULK USX USX TP INT[0..] NMI RQ0 RQ RY SRY HL HOL TMROUT0 TMRIN0 TMROUT TMRIN Rev..0 R INT0 INT INT INT INT INT INT INT INT 000pF 0 0.0uF 0.uF U X RLKOUT X 0 LKOUT ULK [USSOF] [USSI] [PIO] USX USX INT0 0 INT 0 INT INT INT INT 0 INT [PIO] INT [PIO] INT [PW] [PIO] NMI RQ0 [PIO] RQ RY [PIO] SRY [PIO] HL {LKSL} HOL TMROUT0 [PIO] TMRIN0 [PIO] TMROUT [PIO] TMRIN [PIO0] + F MURT LMP00SP 0uF V -S 0 V V V V V m US V V V V V V V V V VUS V 000pF V V 0.0uF RS# RSOUT RUSR# US# {ON#} RLSR# LS# [RS0#] RMS0# MS0# {USX#} [PIO] RMS# MS# [S#] RMS# MS# [S0#] RMS# MS# [RS#] [PIO] PS0# {USSL} [PIO] PS# {USSL} [PIO] PS# PS# PS# {LKSL} [PIO] PS# {TSTMO#} [PIO] 0 PS# [PIO] PS# [PIO] RR# R# RWR# WR# {PROTST#} [PIO] RWL# WL# RWH# WH# L [PIO] T/R# [PIO] N# [S#] [PIO0] H# {N#} [PIO] 0 S0# {USXVR#} S# S# S SIZ# QS0 QS SN [PIO0] SLK [PIO] ST [PIO] RX [] [RX] TX [U] [TX] RLK [L] [LK] TLK [FS] [FS] TS# [TS#] [PIO] RTR# [PIO] RX [RX] [PIO] TX [TX] [PIO] RLK [LK] [PIO0] TLK [FS] [PIO] TS# [TS#] [PIO] RTR# [PIO] RX [RX] [PIO] TX [TX] [PIO] RLK [LK] [PIO] 0 TLK [FS] [PIO] TS# [TS#] [PIO] RTR# [PIO] RXU [RX] [RX] [PIO] TXU [TX] [TX] [PIO0] TSU# [TLK] [FS] [PIO] RTRU# [RLK] [LK] [PIO] RXHU [PIO] TXHU TSHU# [TS#] [TS#] PIO] RTRHU# [RTR#] [PIO] US- [UMNS] US+ [UPLS] RSRV [UXVRV] RSRV [UXVN#] RSRV [UTXMNS] RSRV [UTXPLS] pf 0.uF Rev..0 R R R R R R R R R R0 R R Rev..0 RUS- RUS+ R0 US- R US+ 0 pf + F.uF MURT LMP00SP V -S RS# RSOUT USR# US# LS# MS0# MS# MS# MS# PS0# PS# PS# PS# PS# PS# PS# PS# RR# R# WR# WL# WH# L T/R# N# H# S0# S# S# S SIZ# QS0 QS RX TX RLK TLK TS# RTR# RX TX RLK TLK TS# RTR# RX TX RLK TLK TS# RTR# RXU TXU TSU# RTRU# RXHU TXHU TSHU# RTRHU# SN SLK ST RSRV RSRV RSRV RSRV [UMNS] [UPLS] [UXVRV] [UXVN#] [UTXMNS] [UTXPLS] Rev.0 (,) (,0,,,) (,,,,) (,,,,) (,,,,) (,,,,,) (,,,) (,,,) (,,,) (,,,,) (,,,,) (,,,) (,,,) (,,) (,,) (,,) (,,,,) (,,,) (,,) (,,) (,) () () () Rev.0 (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,,,,) (,,,,,) (,,,,,) (,,,,,) (,) (,) (,,,,) (,,,) (,) (,) (,) (0) (0) (0) (0) Rev.0 (0) (0) PS[0..] (,,,) 0 0 Rev.0 () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - m x. M.SH. ate: Friday, February 0, Sheet of

3 Pinstrap onfiguration PH PH PH PH0 Rev..0: Removed 0 Ohm resistors. SW SW IP- ON Rev..0: Removed 0 Ohm resistors. Rev..0: Removed 0 Ohm resistors. HL [PULKS] PS # [PULKS] PS0 # [USLKS] PS # [USLKS] PULKS (,,,) (,,) (,,,) (,,,) NOT: Pinstraps default high. Set switch to ON position to enable alternate pinstrap function. PU PLL LK MOS 0 0 PULKS 0 X PLL 0 PU PLL MO X PLL (FULT) X PLL PLL YPSS V PU LK Y O V GN OUT *OSp cliptek 00HS-XX X RYSTL TH- cliptek M-L0 PUX Rev..0 pf PUX Rev..0 pf () () V URT LK Y O V GN OUT *OSp cliptek 00HS-XX.mm ULK (,) R K R0 K R K R K R0 K V R 0K R 0 R 0K R K PH PH PH R 0K R 0K V R 0K 0.uF R 0K SW SW IP- V ON R R0 0K R 0K 0K [N#] [USX#] [USXVR#] V USX# U Rev..: dded tristate circuit to allow x oot width and MS0# to work correctly. R 0K R 0K R 0K Reset onfiguration R 0K R0 0K R 0K R 0K PH R 0K PH PH PH PH PH PH0 PH PH PH PH PH PH PH PH PH H# MS0# S0# RSOUT SW SW IP- SW 0 USLKS US PLL LK MOS USLKS NOT: Used to define daughter board options. 0 (,,,,) (,,,,,) (,,,) () 0 US PLL MO 0 X PLL Rev..0: Removed PLL ypass R0 R R R R R R R R R R0 R R R R R R[0..] US PU LK, US PLL ISL (FULT) X PLL (,,,,,) V Y US LK O V GN OUT *OSp cliptek 00HS-XX X RYSTL TH- cliptek -.000M-L0 NOT: If PU lock is used as US lock, should be populated with a K resistor. PU and US locking Options lock PU lock US lock Shared PU / US lock High Speed / Low Speed URT lock V USX Rev..0 pf 0 pf Rev..0 x Rev..0-0MHz X X X USX x -MHz MHz MHz X () () x Reset ircuit -.MHz MHz MHz X OS PLL ypass 0-MHz X X X.mm RYSTL NOT: Populate oscillator or crystal. apacitors populated only when the crystal is used. Oscillator 0-MHz X X 0-0MHz NOT: To disable all HL and URT transceivers set all switches to ON. R 0K V R 0K HL / URT SHUTOWN PH PH SW SW IP- ON 0 SW IP- ON R 0K R0 0K R 00K R0 0K R0 00K V R 0K HLN HLN HLN HLN HURTN# LURTN# (,,) (,,) (,,) (,,) (,) (,) (,) R 00K SW RST RRS# + V PH.0uF V -S V U SNS V RST RSIN RST# T GN RF TLI 0.uF V PH0 RS# 0 0.uF (,) () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - onfiguration x. ONFIGURTION.SH. ate: Friday, February 0, Sheet of

4 (,,,,) M[0..] Kx RM evices K x SRM evice (,,,,,) M[0..] SRM NOT: Populate R0 and depopulate R if using SRM rather than RM as main system memory. (,,,) (,,,,) (,,,) (,,,) (,,,,) () MS# LS# MS# MS# R# WRP# U M RM0 R 0 Q0 M RM R Q M RM R Q M RM R Rev.0 Q M RM R Q M RM R Q M RM R Q M RM R VMM Q 0 M RM R Q RM R Q RM0 R0 Q0 0 RM R R0 N Q RM R N Q RM R *0K N Q RM R N Q RM R Q RS0# MS# [S0#] RS# 0 MS# [S#] LS# V US# V R# O# V VMM WRP# WR# 0 [RS#] [RS0#] [S0#] [S#] R 0 RM X SOJ M0 M M M M M M M M M M0 M M M M M M M M M M M M M M MS# [RS#] MS# [S0#] MS# [S#] R# WRP# U 0 0 N N N N RS# LS# US# O# WR# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q V V V *RM X SOJ M0 M M M M M M M M M M0 M M M M M VMM H# (,,,,) M M M M M M M M M M0 M M M M M M M M M0 Rev..: Removed SRM device and added SRM device. U L 0 H O W Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Vcc Vcc Vss Vss *SRM Kx SOJ 0 0 M0 M M M M M M M M M M0 M M M M M VMM SOJ- RM 0 (,,,,,) (,,,,) M[0..] M[0..] Kx / Mx FLSH evice efault JP: - Rev..: TMROUT0[PIO] changed to SRY[PIO]. SRY [PIO] (,,,) (,,,,) (,,,,,) Rev..0: Removed FLSHS#. (,,,,) (,,,,) (,) US# MS0# WR# R# RS# VMM R 0K R 0K NOT: Populate R and depopulate R if using PIO to bank into the lower K of Flash. Rev..0: Removed 0 Ohm resistors. SW PH PH M M0 JP HR X SW PT W/Y# efault SW0: x M/M0 M Rev.0 R 0 R *0 VMM R 0K Grayhill S0 R 0K VMM R 0K x FLSH WITH x RM M M M M M M M M M M0 M M M M M M M M M FS# WR# R# RS# PH W/Y# U # W# O# RST# RY/Y# YT# MF00 TSOP Q0 Q Q Q Q Q 0 Q Q Q Q Q0 Q Q Q Q RM 0 Q/- V N N 0 N N M0 M M M M M M M M M M0 M M M M M/M0 VMM FLSH FLSH SRM TSOP- F *MURT LMP00SP 0 Rev..: Removed unpopulated caps for SRM device and dded caps for SRM device. NOT: Populate one resistor or the other to provide V or V to RM and FLSH. V VMM V 0 SOJ-0 F MURT LMP00SP 0 Rev..0: Removed 0 Ohm resistors. NOT: Switch FLSH between x and x VMM + 0uF V -S 0.uF 00 0.uF 0.uF 0 0.uF 0 0.uF 0 0.uF 0.uF 0.uF 0.uF () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Memory : RM/FLSH x. MMORY.SH. ate: Wednesday, June 0, Sheet of

5 x / x SRM evice, ROM I (,,,,,) R[0..] (,,,,) R[0..] Rev..0: Rev..0: R R R R R R R R R R0 R R R R R PSL PSL P0SL PSL U SRM Q0 Q Q Q Q Q Q Q 0 O# S# W# V GN RR0 RR RR RR RR RR RR RR R R R R R R R R RR# SRMS# PL V R0 R R R R R R R R R R R R R R R R R0 R R R R R PSL R P0SL PSL U SRM RR R Q0 RR R Q RR0 R Q RR R0 Q RR R Q RR R Q 0 RR R Q RR R Q O# S# W# V GN RR# SRMS# PH V R R R0 R R R R R (,,,,) RR# V (,,,,) (,,,,) (,,,,,) LS# USR# MS0# JP0 HR X R 00K V (,,,) (,,,) R R R R0 WL# R R WH# R S R 0K R JP 0 HR X JP 0 HR X PSL PSL PL PH P0SL PSL SRM Kx Kx Kx Kx ROM Kx Kx Rev..0: JP JP PSL PSL PL PH P0SL PSL N N N N N N V + 0uF V -S SRM SRM 0.uF 0.uF () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Memory : SRM/ROM x. MMORY.SH. ate: Friday, February, Sheet of

6 (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,) RX TX RLK TLK TS# RTR# HLN V HLTX RS- TRNSIVRS U TX IN OUTM RLK IN OUTP TLK IN OUTM RTR# IN OUTP OUTM HLN ON OUTP 0 ON OUTM OUTP ST SOP V GN TXM TXP RLKM RLKP TLKM TLKP RTRM RTRP V (LKM) (LKP) (FSM)(LKM) (FSP)(LKP) TO RS-0 PORT () () () () RS-0 PORT P RTRP TLKM (LKM) HLKP HLKM GN TLKM (FSM) 0 RLKM (LKM) TLKP (FSP) 0 GN TSP HLKP HLKM RTRM RLKP (LKP) TSM TXP TXM TLKP (LKP) RXM RXP GN TSP R0 00 TSM HLKP R0 00 HLKM HLKP R0 00 HLKM RXM R0 00 RXP (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,) Rev.0 RX TX RLK TLK TS# RTR# HLN U T V U T V R 00K HLRX R 00K PH PH R 0 R 0 R GRN TH R L SOT- Rev.0 RX RX TS# TS# U OUT OUT OUT OUT HLN N HLN N ST SOP U TX IN OUTM RLK IN OUTP TLK IN OUTM RTR# IN OUTP OUTM HLN ON OUTP 0 ON OUTM OUTP V GN ST SOP Rev..: Nets RXM and RXP switched with TSM and TSP. INM INP INM INP INM INP INM INP V GN 0 RXM RXP RXM RXP TSM TSP TSM TSP V TXM TXP RLKM RLKP TLKM TLKP RTRM RTRP V TO RS-0 PORT & TO RS-0 PORT (LKM) (LKP) (FSM)(LKM) (FSP)(LKP) TO RS-0 PORT () () () () RTRP TLKM HLKP HLKM GN TLKM RLKM TLKP GN TSP HLKP HLKM RTRM RLKP TSM TXP TXM TLKP RXM RXP GN RS-0 PORT (LKM) (FSM) (LKM) (FSP) (LKP) (LKP) P 0 0 ONNTOR TSP R0 00 TSM HLKP R0 00 HLKM HLKP R0 00 HLKM RXM R0 00 RXP 0 HLTX ONNTOR U T V R 00K R 0 R PH GRN TH PH R L SOT- R0 0 Rev.0 SOT- Top View V + 0uF V -S Rev.0 ST ST ST T 0.uF 0.uF 0.uF 0.uF HLRX U T R 00K Rev.0 () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - HL Transceivers (Page ) x. HL.SH. ate: Friday, February 0, Sheet of

7 (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,) (,,,,,) (,,,,,) (,,,,,) (,,,,,) (,,,,) (,,,) (,,) RX TX RLK TLK TS# RTR# HLN RXU TXU RTRU# TSU# TSHU# RTRHU# HLN Rev.0 [RX] [TX] [RLK] [TLK] [TS#] [RTR#] V U T V U T V 0 HLTX R 00K HLRX R 00K HLTX R 0 R PH GRN TH PH R L SOT- R Rev.0 0 RS- TRNSIVRS U TX IN OUTM RLK IN OUTP TLK IN OUTM RTR# IN OUTP OUTM HLN ON OUTP 0 ON OUTM OUTP V GN ST SOP RX RXU TS# TSHU# U OUT OUT OUT OUT HLN N HLN N ST SOP U0 TXU IN OUTM RTRU# IN OUTP TSU# IN OUTM RTRHU# IN OUTP OUTM HLN ON OUTP 0 ON OUTM OUTP V GN ST SOP TXM TXP RLKM RLKP TLKM TLKP RTRM RTRP V (LKM) (LKP) (FSM)(LKM) (FSP)(LKP) Rev..: Nets RXM and RXP switched with TSM and TSP. INM INP INM INP INM INP INM INP V GN 0 RXM RXP RXM RXP TSM TSP TSM TSP V TO RS-0 PORT & TO RS-0 PORT TXM TXP RLKM (LKM) RLKP (LKP) TLKM (FSM)(LKM) TLKP (FSP)(LKP) RTRM RTRP V TO RS-0 PORT TO RS-0 PORT () () () () () () () () HLKP HLKM RTRP TLKM GN TLKM RLKM TLKP GN TSP HLKP HLKM RTRM RLKP TSM TXP TXM TLKP RXM RXP GN HLKP HLKM RTRP TLKM GN TLKM RLKM TLKP GN TSP HLKP HLKM RTRM RLKP TSM TXP TXM TLKP RXM RXP GN RS-0 PORT (LKM) (FSM) (LKM) (FSP) (LKP) (LKP) RS-0 PORT (LKM) (FSM) (LKM) (FSP) (LKP) (LKP) P 0 0 P 0 0 ONNTOR TSP R 00 TSM HLKP R 00 HLKM TSP R 00 TSM HLKP R 00 HLKM HLKP R 00 HLKM RXM R 00 RXP HLKP R 00 HLKM RXM R 00 RXP U T V U T R 00K HLRX R 00K R 0 R PH GRN TH PH R L SOT- R Rev.0 0 SOT- Top View V + 0uF V -S Rev.0 ST ST ST T 0 0.uF 0.uF 0.uF 0.uF ONNTOR Rev.0 () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - HL Transceivers (Page ) x. HL.SH. ate: Friday, February 0, Sheet of

8 V Y O V GN OUT OSp cliptek M V V Y O V GN OUT OSp cliptek -.M MO[0..] FRM[0..] FRQ[0..] () () () + 0uF V -S 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF V SW SW IP- SW0 SW IP- SW SW IP- R 0K R0 0K MOX0 MOX MOX MOX FRMX0 FRMX FRMX FRQX0 FRQX FRQX R0 0K R 0K R 0K R 0K R 0K R 0K R 0K R 0K R K R0 K R0 K R K R K R0 K R K R0 K R K R K /PM LOK SOUR LK SOUR JPx TLK/FS RLK/LK TLK RLK P P - - P RMOT - - RMOT P - - RMOT RMOT uF 0.uF0 0.uF0 0.uF0 0.uF 0.uF 0.uF 0.uF 0 (,0,,,) 0.uF 0.uF RSOUT () () () () () () () () U LK0 I/LK LK I0/LK0 MO0 I/O MO I/O0 MO I/O MO I/O FRM0 I/O FRM I/O FRM I/O FRQ0 I/O FRQ I/O FRQ I/O0 I/O HLN I/O HLN I/O HLN 00 I/O HLN I/O HLKM HLKP HLKM HLKP HLKM HLKP HLKM HLKP V I/O I/O I/O I/O I/O I/O I/O I/O0 I/O I/O I/O I/O I/O I/O I/O I/O0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M-/-Y 0 U INM INP INM INP INM INP INM INP V GN OUT OUT OUT OUT N N I/O I/O I/O I/O I/O0 I/O I/O I/O0 I I/LK I/LK I TRST NL TK TMS TI TO V V V V V V V V I/O I/O I/O I/O I/O 0 I/O 0 I/O0 I/O I/O I/O I/O I/O I/O I/O HLK HLK HLK HLK RLKT R0 RLKR R RLKT R RLKR R RLKT R0 RLKR R RLKT R RLKR R Rev.0 TRST R NL R TK TMS TI TO LKT LKR LKT LKR LKT LKR LKT LKR Rev..: Pull-up and pull-down added to signals TRST and NL. V 0K K V LKT LKR LKT LKR LKT LKR P 0 HR X MP - JP HR X JP HR X JP HR X LOW R0 V K TLK RLK TLK RLK TLK RLK (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) Rev.0: hange made to table. (,,) (,,) () () () () () () () () (,,) (,,) HLN HLN HLKM HLKP HLKM HLKP HLKM HLKP HLKM HLKP V HLN HLN 0 ST SOP U INM INP INM INP INM INP INM INP V GN ST SOP OUT OUT OUT OUT N N HLK HLK HLK HLK LKT LKR JP HR X TSU# RTRU# [TLK] [RLK] () dvanced Micro evices, Inc. (00) - (,,,,,) (,,,,,) 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - HL Transceivers (Page ) x. HL.SH. ate: Friday, February 0, Sheet of

9 TS# (PIO) and RTR# (PIO) can be used to provide HSURT hardware flow control in case TSHU# is needed as its TS# alternate function. Rev. JP RTRHU# (,,,) RTR# (PIO) (,,,) TSHU# (,,,,) TS# (PIO) (,,,,) HR X RXHU (,) (,) TXHU Rev.: hanged Part HSPIO HSPIO JRTRHU# RXHU JTSHU# TXHU HSPIO HSPIO0 High Speed URT U TIN TOUT ROUT RIN TIN TOUT ROUT RIN ROUT RIN TIN TOUT 0 TIN TOUT TIN TOUT PIOHS PIOHS RRTRHS# RRXHS RTSHS# RTXHS PIOHS PIO0HS Rev.0 R R R R R R R R Rev. RIHS# TRHS# RTRHS# RXHS TSHS# TXHS SRHS# HS# P ONNTOR (,) HURTN# 0.uF PH0 N# S + PH - V- + - V+ PH PH 0.uF PH PH0 0.uF V 0.uF 0pF 0pF 0pF 0pF 0pF 0pF 0pF 0pF Rev.0 Rev. (,,) (,,) (,,) (,,) NOT: PIO s may be used as additional hardware flow control signals for the high or low speed RS port if needed. These are defined as: PIO0 - PIO - TR PIO - RI PIO - SR TMRIN [PIO0] TMROUT [PIO] TMRIN0 [PIO] TMROUT0 [PIO] JP HR X Rev. SP0H Sipex SP0HT Rev.0 V V T0 U V GN U 0 T0 UL UL Rev.0 R R 0PH GRN R 0 PH TH R L SOT- NOT: SIPX XVR S HV 00K PULLUPS ON RIVR INPUTS N K PULLOWNS ON RIVR INPUTS (,,) (,,) (,,) (,,) TMRIN TMROUT TMRIN0 TMROUT0 [PIO0] [PIO] [PIO] [PIO] JP HR X V V U T0 U 0 UL UL R 0PH R 0PH Rev.0 R GRN TH R L SOT- SOT- Top View T0 Low Speed URT (,,,,,) (,,,,,) (,,,,,) (,,,,,) RTRU# RXU TSU# TXU Rev.: hanged Part U LSPIO TIN TOUT LSPIO ROUT RIN RTRU# TIN TOUT RXU ROUT RIN TSU# ROUT RIN TXU TIN TOUT LSPIO 0 TIN TOUT LSPIO0 TIN TOUT PIOLS PIOLS RRTRLS# RRXLS RTSLS# RTXLS PIOLS PIO0LS Rev.0 R R R R R R0 R R Rev. RILS# TRLS# RTRLS# RXLS TSLS# TXLS SRLS# LS# P ONNTOR (,) LURTN# 0.uF PH PH N# S + - V- + - V+ PH0 PH 0.uF PH PH 0.uF V 0.uF 0pF 0pF Rev.0 0pF 0pF 0pF 0pF 0 0pF 0pF Rev. SP0 Sipex SP0T V GN 0 V SPH SP T0 Rev.0 + 0uF V -S 0.uF 0.uF 0.uF () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - High Speed URT x. URT.SH. ate: Thursday, February, Sheet of

10 m US ttach/etach ttach: ) m polls RXP [PIO] for high edge to determine when Vusb becomes active. ) m drives TXP [PIO] for LO enable high after Vusb presence detected. etach: ) Vusb goes away: m polls RXP [PIO] for low edge. ) m tristates US+/-. ) m V goes away: Q isolates Vusb from RXP [PIO]. G S () TXP [PIO] SOT- Top View TN000T Rev..0 Rev..: TX[PIO] changed from L[PIO]. Rev..0 Q TN000T SOT- Rev..0 Rev.. V SOT- Top View R00 PH Rev..: Pinout corrected for this part. Pins and were swapped. Rev..0 V+ NOT: N TO SWITH PIO OFF WHN PIO TSTING [UPLS] [UMNS] [UXVRV] [UXVN#] [PIO] Rev..: RX[PIO] changed from TMRIN0[PIO]. PH V VP VM Rev..: Pinout corrected for this part. Pin changed to pin. U0 VMO VPO VP VM RV O# SUSPN SP *US XVR - + N N V GN 0 Rev..0 PH PH 0 pf G V S G S Q () () () () P VUS US- US+ GN PH US ON MP 0- F MURT LMSP US+ US- RSRV RSRV () () () RXP RSRV [UTXMNS] RSRV [UTXPLS] Rev..0 R *0 R *0 IO ROHM R00 TN000T SOT- R *0 R *0 0 pf PH PHX PHX R 00K R.K TP F MURT LMSP PH Rev..0 TP US Type Front View oard dge R K R 0K P Footprint PH V R0 0 R 0 R 00 PH0 Rev..: Resistor changed from 0K to 00. US T Rev..0 R Rev..0 GRN RYP [PIO] TH R L SOT- (,,,,) US Transceiver Population Option Internal xternal V R R R R R R US XVR 0.uF () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - US Transeiver x. US.SH. ate: Thursday, February, Sheet 0 of

11 Rev..0 PO 0 PO HP onn. PO PO m PO PO 0 PO PO 0 Top View P RLK [L] [FS] TLK RX [] TX [U] 0 HR X MP - GI onn. GI onn. 0 Top View (,,,) PS[0..] PS# PS# PS# PS0# (,) SLK Rev..: Signals S# and S0# switched. S# (,,) S0# (,,,) H# (,,,,) N# (,,) SRY (,,,) QS0 () QS () P +V LK LK GN 0 HP ONN P +V LK LK GN 0 HP ONN PS# PS# PS# PS# (,) ST (,) SN (,,0,,) RSOUT (,,) S# (,) S (,,) L (,,) T/R# (,0,,,) RY () SIZ# (,,,,) (,,,) R# (,,,,) LS# (,,,,) MS# (,,,) MS0# (,,,,,) WL# (,,,) WH# (,,,) R R R[0..] INT[0..] INT INT INT INT NMI (,,,) TMROUT (,,) TMROUT0 (,,) HL (,,,) P +V LK (,,,,) LK (,,,) (,,,) 0 (,,,,) 0 (,,,,) R R 0 GN 0 HP ONN P +V LK INT LK INT INT 0 INT 0 INT0 (,,) (,,) (,,,) 0 GN 0 HP ONN US# MS# MS# R# WR# TMRIN TMRIN0 HOL P Q- (,,,,,) (PIO0) TXU (PIO) (,,,,,) RXU (PIO) TSU# (PIO) (,,,,,) RTRU# 0 0 (,,,,,) (PIO0) (,) SN (PIO) (,) SLK (PIO) (,) ST (,,,) PS0# (PIO) 0 (PIO) (,,,) PS# (,,) PS# 0 (,,) PS# (,,) PS# (PIO) (PIO) (,,) PS# (,,) PS# (PIO) (PIO) (,) PS# 0 (PIO) (,0,,,) RY (,,,) (PIO) SRY (PIO) (,,,,) WR# (,,) (PIO) T/R# 0 (PIO0) (,,) N# (,,) (PIO) L (PIO) (,,,,) H# 0 MO (PIO) (,) ULK MO (PIO) (,,,) RTRHU# MO (PIO) (,,,,) TSHU# MO0 0 (PIO) (,) RXHU 0 (,) HURTN# (,) LURTN# HLN (,,) (,,) HLN HLN (,,) 0 (,,) HLN +V GN 0 Q ONN MP --0 MO[0..] () Q onn. (,,) LKOUT JP HR X (,,,,,) R[0..] (,,,,) WR# PH R R R0 R R R R R0 R R R0 R R R R R0 P +V LK LK GN 0 HP ONN P0 +V LK LK GN 0 HP ONN R R R R R R R R R R R R R R R R TX (,,,) RLK (,,,) TS# (,,,) TX (,,,) RLK (,,,) TS# (,,,) RQ0 (,,) ULK (,) TXU (,,,,,) TSU# (,,,,,) TXHU (,) TSHU# (,,,,) TX (,,,) RLK (,,,) TS# (,,,) P +V LK LK (,,,) RX (,,,) TLK 0 (,,) RTR# 0 (,,,) RX (,,,) TLK (,,) RTR# (,,) RQ 0 GN 0 HP ONN P0 +V LK LK (,,,,,) RXU (,,,,,) RTRU# 0 0 (,) RXHU (,,,) RTRHU# (,,,) RX (,,,) TLK (,,) RTR# 0 GN 0 HP ONN INT0 (,,,) INT (,,,) INT (,,,) INT (,,) INT (,,) TMROUT0 (,,) TMRIN0 (,,) (PIO) (PIO) (PIO) (PIO) RQ0 (,,) (PIO) TS# (,,,) (PIO) TX (,,,) (PIO) TS# (,,,) (PIO) RLK (,,,) (PIO0) TX (,,,) (PIO) TS# (,,,) (PIO) RLK (,,,) (PIO) FRQ FRQ0 FRM FRM0 P Q V GN 0 Q ONN MP --0 (PIO) FRM (,,,) INT (,,,) INT (,,) INT (,,) INT (,,,) NMI (PIO) (PIO0) (,,) (,,) TMROUT TMRIN (PIO) (,,,,,) MS0# (PIO) (,,,) MS# (PIO) (PIO) (PIO) (PIO) (PIO) (PIO) (PIO) (,,) (,,,) (,,) (,,,) (,,,) (,,) (,,,) RTR# RX RTR# TLK RX RTR# TLK FRQ FRM[0..] FRQ[0..] () () Top View 0 (,,,,) R[0..] () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - UG/Q x. UG/Q.SH. ate: Friday, February 0, Sheet of

12 Local us Interface (,,,,,) M[0..] RY (,0,,,) SRY (,,,) (,,,,) M[0..] M M M M M M M M0 RY SRY M M M M M M M M M M0 M M M M M M M M M M0 P HR X V (,,0,,) (,,) (,,) (,,) (,,) (,,,,) (,,,,) (,,,,) (,,,,) (,,,) (,,,) (,,,) (,,,,,) (,,,,,) (,,,,,) (,,,,,) (,,,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,,) RSOUT TMROUT0 TMRIN0 TMRIN TMROUT US# LS# WR# R# MS# MS# MS# MS0# RTRU# TXU RXU TSU# NMI INT INT HL WL# L WH# (,,,) H# (,,,,) PS[0..] PS# PS# PS# PS# PS# PS0# M M M0 M M M M M P V Rev..0 (,,,) (,) (,,,) (,,,) (,,,) (,,) (,,) (,,) (,,) (,,) (,,,) (,,) (,,) HOL S INT INT INT0 RQ RQ0 LKOUT S# S# S0# T/R# N# HR 0X 0 Rev..: Part changed flipping the pin names ( names moved to right side and name moved to left side). Top View Rev..0 () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Local us Interface x. XP.SH. ate: Friday, February 0, Sheet of

13 Module onnectors Tip onn. (,,,,,) (,,,,) M[0..] M[0..] NOT: M high during reset indicates TIP is present. Rev..0 0 V WH# (,,,) WL# (,,,) H# (,,,,) RY (,0,,,) SRY (,,,) US# (,,,,) M0 M M M M M0 M M M M M0 M M M M M0 M M V V P # 0 PS0 PS# PS# PS# PS# PS# PS# PS# 0 ON0 MP 0- M M M M M M M M M M M M M M M M M M V V WR# R# (,,,,) (,,,,) (,,,) (,,,) (,,0,,) (,,,,) V WR# R# HOL HL RSOUT LS# V + 0uF V -S M0 M M M M M0 M M M M M0 M M M Rev..0 NTN R# WL# S# Rev..0 SHIRQ RRS# (,) RSOUT R# WL# US# Rev..0 P ON0 MP 00- M M M M M Rev..0 M M M M M M M M M (,,,,,) NTIRQ PRIRQ SRIRQ SRIRQ0 Rev.. () RYP SL M V 0 Top View + 0uF V -S (,,,) PS[0..] M0V (,,,) MV Rev..: apacitors 0 and removed. INT[0..] T/R# (,,) N# (,,) MS0# (,,,,,) MS# (,,,) S0# (,,,) S# (,,) S# (,,) RX (,,,) TX (,,,) RLK (,,,) TLK (,,,) TS# (,,,) RTR# (,,) RX (,,,) TX (,,,) RLK (,,,) TLK (,,,) TS# (,,,) RTR# (,,) ST (,) INT0 INT INT INT INT P ON0 MP 0- [RX] [TX] [RLK] [TLK] [TS#] [RTR#] INT INT INT INT (,,) (,,) (,,,) (,,,) (,,) (,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,) (,,,,,) (,,,,,) (,,,,,) (,,,,,) (,,,,) (,,,) (,) (,) LKOUT L MS# MS# RQ0 RQ NMI RX TX RLK TLK TS# RTR# RXU TXU RTRU# TSU# TSHU# RTRHU# SN SLK V + 0uF V -S + MV 0uF V -S Rev..0 INT0 INT INT INT NOT: ROUTS TIP IRQ S TO m/h/u R *0 R 0 R 0 R 0 R 0 PS# R 0 SHIRQ NTIRQ PRIRQ SRIRQ SRIRQ0 NTN Rev.. NOT: () SHIRQ is all IRQ s logically OR ed on TIP and configured as level triggered high. () M is TIP present indicator in RSON register. () PS# is the TIP ethernet chip select. () S# is the MM/IO cycle detect to TIP. () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Module and TIP onnectors x. MOUL/TIP.SH. ate: Wednesday, June 0, Sheet of

14 P NTR SHUNT SLV RRL ON KYON KL-00- VX Rev uf V -S VX TPSM0R uF Rev..0. F V Rev.0 0uF U VIN SHN GROUN SW F MV RGULTOR Micrel MI-.0U RG_SW L 0uH oiltronics TX0-- IO ROHM R0L-0 MVO Rev.0 + 0uF 0V -S + 0uF 0V -S VX TPSM00# 00 MV R0 0 KO RMZ, %, W arrel onnector Top View TO-- MI-.0U MIU R0L-0 O- SOT- Top View GN Rev.0 0 0uF Rev.0 U VIN SHN GROUN MI SW F V L SHOTTKY RTIFIR uh + 0uF 0V -S + 0uF 0V -S + 0uF 0V -S V 0.uF U IN OUT GN LO-. Micrel MI0-.S Rev.0 Rev. + 0uF V -S V 0.uF Rev..: Power changed to a switching regulator. Rev.0 MV M0V V + uf V -S VX TPSM0R00 0 VX TPSM0R uf V -S 00pF 0 0V VX 00MTM SOT- Top View RHOM RSZ OMPR Rev..: Pinout corrected for this part. Pin changed to pin. V U IN SW OMP OMP GN F SLI RGULTOR Micrel MIU R.K 0 IO ZNR ROHM RSZ 0 0.uF 0 VX 0MTM F VX R 0K IO ZNR General Semi SMZJ IO General Semi S VSW R V OP MP Micrel MIM U V 0.0uF 0 Rev..: Pinout corrected for this part. T T: T: T: T: Flyback Transformer eckman HM00-0pF 0 0V VX 00MTM M0V TRTP MV General Semi S General Semi S General Semi S + + MVP KO RMZ, %, W uf V -S VX TPSM0R00 0 uf V -S VX TPSM0R SOT-- MIM MVR R00 0 M0VR uf V -S VX TPSM0R00 0 M0VF M0RR R 0 KO RMZ, %, W R.K 0 R.K 0 R L SMT R L SMT R0 L SMT R L SMT R L SMT LM0V R.K KO RM, %, W LMV LMV LV LV M0V P MV P R.K KO RM, %, W R 0 R R 0 MV anana Jack anana Jack P V P V P anana Jack anana Jack anana Jack P anana Jack () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Power Supply x. POWR.SH. ate: Friday, February 0, Sheet of

15 V SP V V Rev..0 V R 0K SWX MULTIROP SWITH NOT: ST SWITH ON WHN USING MULTIROP MO (TH RS TRNSIVRS WILL RMOV IN THIS MO) SW ON SW ON GRYHILL G0 IP- SW ON GRYHILL G0 IP- (,,,,,) (,,,,,) GRYHILL G0 IP- SW ON (,,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) (,,,) [RX] RXU [TX] TXU [TS#] TSHU# RX TX TS# RX TX TS# RX TX TS# efault SW: OFF SW: OFF SW: OFF SW: OFF General Function PIO s US PIO s WR# (,,,,) [PIO] INT (,,) INT (,,) INT (,,) TX (,,,) RX (,,,) [PIO] [PIO] PIO ISOLTION SWITH NOT: TURN SWITH TO OFF POSITION IF PIO ISOLTION IS SIR. efault SW: ON SW ON VMM R 0K INTP INTP INTP RY (,0,,,) [PIO] 0 Rev..0 Rev..0 GRYHILL H0 IP- R 0K R0 00K R 0K V R 0K () Rev..: L[PIO] and TMRIN0[PIO] changed to TX[PIO] and RX[PIO]. (0) (0) WRP# TXP RXP RYP Rev.. GN *SPR Y Y Y Y 0 Y 0 Y 0 SP Y Y Y Y Y Y Y Y Y 0 GP GN *SPR0 V 0 0.uF GP V 0.uF GRYHILL G0 IP- GP GP GP GP Rev..: hanged Part UG R 0 V R0 0 UG U INT0 (,,,) INT (,,,) R0 0K V R 0 R 0 UG V 0 UG INT (,,,) INT (,,,) INT (,,,) INT (,,) R R R R 0K 0K 0K 0K NMI (,,,) R HOL (,,,) R 00K 00K U R 0K R 0 R 0 UG V UG U () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ustomer ev. Platform (Main oard) - Miscellaneous x. MIS.SH. ate: Friday, February 0, Sheet of

16 Table of ontents Page : over Sheet (OVR.SH) Page : Main oard onnectors (ONNTOR.SH) Page : thernet Page (THRNT.SH) Page : thernet Page (THRNT.SH) Page : ISN S Interface (ISN_S.SH) Page : ISN U Interface (ISN_U.SH) Page : RSLI Page (POTS_RSLI.SH) Page : RSLI Page (POTS_RSLI.SH) Page : SL (POTS_SL.SH) Page 0: Miscellaneous (MIS.SH) m/h/u ustomer evelopment Platform Schematics Router/ISN evelopment Rev.0: Rev.0: Original design Sheet : hange buffer control Sheet : hange Packet SRM to Kx hange PL routing for thernet and uffer control dd thernet L0 and delete L Sheet : orrect S/T interface RJ pinout dd S/T protection circuitry hange S/T transceiver to -bit addressing Remove ISN diagnostic L Sheet : dd S/T interface names to U transceiver Sheet : dd Time Slot ontrol buffering Module Rev.: Sheet : hange data buffer control dded RING_IN PIO s thru buffer Sheet : hange PL for TMF and ata uffer control hanged Packet SRM select circuitry Sheet : hange S/T Interrupt to INT Sheet 0: dded SL clocking jumper select Swapped TMF data bit order () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - over Page x. OVR.SH. ate: Friday, June 0, Sheet of

17 ddress us us :0 :0 uffers uffered ddress us uffered us thernet ontroller m L s Transformer RJ ontrol us ontrol us uffered ontrol us PL uffer trl thernet trl PROM ISN trl Packet SRM 0ase-T thernet Main oard Interface onnectors SSI trl POTS trl S/T Transceiver m ISN S/T Interface Transformer RJ SSI HL TX STS# Tristate uffer TX U Transceiver Lucent T RX Transformer RJ HL TX TS# Tristate uffer TX ISN U Interface L s HL LK, FS odec m0 RSLI mr ircuit Protection RJ STS# RSLI mr ircuit Protection RJ TMF Receiver Teltone M-0-0 POTS Interface TMF Receiver Teltone M-0-0 () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - lock iagram x. LOK IGRM. ate: Monday, May, Sheet of

18 V Rev..0: Removed WL# and WH# Rev..0: Removed RY 0uF 00V + + 0uF 0V M0 M M M M M0 M M M M 0 0 V V H# () PS# PS# PS# P ON0 P M M M M M M M M M M V V WR# R# NTL0 PS# PS# V Rev.0: dded LS#. INT INT INT INT V INT 0 Rev.0: dded () LKOUT R R MS0# () 0K 0K 0 V TX PM RX PM TX R *0 R R PM0 LK 0 RLK PM FS TLK 0K *0K [PIO] TS# () () TS# [PIO] RTR# () () RTR# 0 RX R *0 TX TX R0 *0 TX LK () LK R *0 LK FS () FS R *0 FS TS# R *0 TS# 0 Rev.0: dded HL. M0V MV ST (,) () SN V MV (,) SLK ON0 0 0 () () (,,) () [0..] HOL HL RSOUT LS# PS[0..] (,,,) (,,) PM[0..] (,,,) INT[0..] 0uF V uF V ONN ONN " HL hannel is used if the m is required to communicate directly across the PM bus with the SL. The HL hannel TX is connected to the hannel RX and vice-versa, the lock and Frame Sync is derived from hannel source WRNING: If HL hannel is used, the Low speed URT is unavailable Rev..0: hanged connections here. R Rev..0: hanged connections here. V U MSTR# R 0K ON IR IR R 0K M M M M Rev..0: hanged connections here. WR# R# Rev..: uffer Ring_In to make (PIO0) RLK MOS level for RSLI. (PIO) TLK R 0K ON R 0K ON R 0K ON R 0K ON R 0K ON0 R 0K ON R 0K ON R 0K ON Rev..0: hanged connections here. Rev..: dded Gate control. MSTR# (,) K UFG# UFIR# () UFG# () M0 M M M M M M M M M M0 M M M M M UFG# ON 0 0 U IR IR G# G# GN GN GN GN T T V V V V GN GN GN GN G# G# GN GN GN GN U V V V V GN GN GN GN IR IR G# G# GN GN GN GN V V V V GN GN GN GN V V V 0 0 NTL[0..] (,,) WR# NTL R# NTL RINGIN_ RINGIN_ (,,,) Rev..: uffer Ring_In to make (,,,) MOS level for RSLI. 0 0 [0..] (,,) [0..] (,,,) T V 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF + 0uF V -S () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - Main oard onnectors x. ONNTOR.SH. ate: Monday, May, Sheet of

19 cliptek M-ITR X V V Isolate from V plane. onnect at single point with 0 mil trace. 00 m NTL[0..] (,,) RSOUT NTL0 PS #(,) SH# (,,) R# NTL WR# NTL R# NTL WR# (,,) RF# Rev.0: hanged MMW# to WR#. SLP# HL# () [0..] (,,) [0..] (,,,) K# pf R 0.000MHz K# 0K V pf U NTX XTL NTX XTL RST N L SH# IOR# IOW# MMR# MMW# RF# SLP# K# K# K# K# S0 S S S S S S S S S S0 S S S S S S S S S L L L L0 L L L S0 S S S S S S S S S S0 S S S S S V V V V V V V m 0 0 V V V V IRQ# IRQ# IRQ# IRQ# IRQ0# IRQ# IRQ# IRQ/PS# IOS# IOHRY MSTR# RQ RQ RQ RQ XVR PS# L0 L L L I+ I- I+ I- O+ O- TX- TX+ TXP- TXP+ RX- RX+ SHFUSY S O I SK PR PR PR PR PR TO TMS TI TK IOS# IOHRY (,) NOT: onnect between (Pin 00) and V (Pin ) Rev.0 orrected thernet L connection ISHT ISHT NT INT R 0K TXM TXP TXPM TXPP RXM RXP 0.uF NTL NTL NTL V R 0K MSTR# () V V HOL R 0K + uf V -S R R K Rev..0: hanged resistor to K from 0K. SHFUSY S O I SK R R TH GRN L SOT- R R TH GRN L SOT- R R TH GRN L SOT- Isolate from V plane. onnect at single point with 0 mil trace. NTLX NTLX NTLX U S O I SK V N N R 0 V SRIL PROM IP R 0 V R 0 Front View SOT- Top View L Layout Note: Keepout rea, No Power or GN planes Signal Trace = 0 mils, route all traces on top signal layer U TX- TX+ TXP- TXP+ RX- RX+ LN TRNSFORMR T+ T- R+ R- RJ onnector Rev..0: isconnected pin. omponent Side View Mounting Hole Layout 0 TP TM RP RM P PINS: - NP MOUNTING HOLS:, 0 SHIL MOUNTING HOLS:, oard dge GN GN RJ SH# R 0K RF# R 0K SLP# INT () SHFUSY R# NTL WR# HOL R R R0 R R R 0K 0K 0K 0K 0K 00K V 0.uF 0.uF 0.uF 0.uF + uf V -S V V () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - thernet Page x. THRNT.SH. ate: Monday, May, Sheet of

20 PNetIS SRM - Packet uffer K x SRM [0..] (,,,) [0..] (,,) 0 U Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q Q Q Q 0 V 0 0 TSOP- PLV0 NTL[0..] (,,) R# WR# MS0# 0 H# NTL NTL L 0 H O W Kx SRM Vcc Vcc Vss Vss PL- Rev..0: hanged two Kx parts to one Kx part. PL SRIPTION Rev..0: hanged 0 to RSOUT. Rev..: dded PS# for TMF. Rev..: dded PS# for TMF. LKOUT () MSTR# (,) RSOUT (,,) Rev..0: Removed I I/O WH#. PS # (,) I I/O () UFG# R# NTL I I/O SRMS# HL () I I/O HL# () PS # (,) I I/O () H# WR# NTL 0 I I/O 0 SRSL# TS# [PIO] () I I/O SLK () SLK (,) I I/O () SH# PS # (,) I0 I/O0 () UFIR# GN I PS # (,) GN PLV0 PL- Rev..0: dded off-page connector, PS#. Rev..0: Removed H#. U LK/I0 I V V I/O 0.uF 0.uF V RST# () Rev..: dded control for data buffer. Rev..0: dded UFIR# and PS# and changed direction of SH#. 0.uF Rev..0: hanged UFO# to H#. Rev..: hanged SRM select circuit. SW SW PT V R0 00K () MS0# () LS# V Grayhill S0 LS# Packet SRM MS0# HL# = HL + MSTR; SH# = H + H; (NL_Y /MSTR#) UFG = [PS + PS + PS + PS] + [MSTR * SRMS * MIN] + [/MSTR * SRMS * /MIN] UFIR# = MSTR * WR + /MSTR * R SLK = SLK; (NL_Y PIO) SRMS# = (NL_Y /MSTR#) H# (NL_Y MSTR#) RST# = RSOUT HL# is an inverted HL and must remain active while MSTR is asserted (If RM is used as main system memory, the will deassert HL when requesting a refresh). SH# is an output which is delayed to extend after the rising edge of the command when has bus, and is an input which drives H# when PNTIS has the bus. It is clocked by LKOUT. UFG enables the gate of the tristate data buffer only when data is being transferred between the P main and module. UFIR# points the data buffer towards the on reads from PNTIS and when the has the bus and during PNTIS writes when PNTIS has the bus. SLK is the SLK which is controlled by PIO to tristate SLK when the T is not being accessed. SRMS# is TIV when PNTIS has bus. H# is a gated SH# output from PNTIS. RST# is an inverted RSOUT. () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - thernet Page x. THRNT.SH. ate: Monday, May, Sheet of

21 Layout Note: is a single substrate device. Separate Vcc plance for this area, connected to System Vcc through single point. See ypass ap below for bulk capacitance. LIN (,) LIN (,) LOUT () LOUT () M - ISN S Interface Layout Note: Keepout rea, No Power or GN planes Signal Trace = 0 mils, route all traces on top signal layer SINTX X SINTX RV.0: dded (,,) NTL[0..] (,,) [0..] RSOUT R# WR# RV.: hanged from INT [0..] (,,,) PM[0..] (,,) 0 pf.mhz U XTL XTL NTL0 PS # (,) RST LIN NTL S# LIN NTL R# LOUT INT () WR# LOUT INT# HSW 0 0 MLK RSRV RV.0: dded RSRV 0 RSRV 0 RSRV RSRV RSRV RSRV RSRV RSRV 0 RSRV LK PM0 V 0 0 FS PM SLK V TX PM SFS RX PM SIN LK SOUT L/ST M PL LIN LIN LOUT LOUT MLK pf VS R K 0 R K 0 R R.. T 0 0 +/- %, /W +/- %, /W U0 T T R0. T 0 +/- %, /W U R.K T T 0 T T L0- L0- R.K 0 R. 0 +/- %, /W TPRTXFRX U STXFR 0 TNRTXFRX RPRTXFRX STXFR RNRTXFRX Pulse P- STXFR 0pF STXFR 0pF STXFRL STXFRL STXFRL STXFRL R0 00 R 00 U P 000pF 000pF Rev.0: dded caps and corrected pinout 000pF LRJ LRJ LRJ LRJ 000pF P GN GN RJ V VS m -PIN PL LK MLK LK_ () MLK_ () MLK_ drives MLK_SL when ISN S Interface is functional. lternate source for MLK_SL is T/U Interface. Note - MLK_ is controlled by the PLV0 Front View RJ onnector omponent Side View Mounting Hole Layout 0 PINS: - NP MOUNTING HOLS:, 0 SHIL MOUNTING HOLS:, oard dge VS ulk apacitance, place at single point connection for Vcc plane(isn S Interface) () Ls onnected to PIOs R RTR# [PIO] GRN TH R ISN L SOT- SLX R V 0.uF 0.uF + 0uF V -S () RTR# [PIO] ISN R GRN TH R L SOT- SLX R o not use separate supplies for V and V due to single substrate () PS# [PIO] ISN R GRN TH R L SOT- SLX R () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - ISN S Interface Rev.0: Removed ISN IG L x. ISN_S.SH. ate: Monday, May, Sheet of

22 U Interface T -PIN PL V.0uF T R.K R 0K R RSRR V R GRN TH R L SOT- R 0 STLX RST# () STL VU OPTVR VR R.M VR U GN VO V Vcc N N athode node N R UPNO UOMTH U T RS P OM LH PR+ T R PR- PRP PRM R0.K LHRR R.K 0.0uF 0.0uF V PM[0..] (,,) FS PM RFS VU R *0 Rev.0: dded U 0 ILOSS# V FS STL OPTOIN GN HIGHZ# RST# V GN GN 0.0uF 00pF V ST (,) 0.0uF R 0K SLK () V V TX RX LK INT () 0.0uF PM PM PM0 SLK - From PLv0. PIO is used to tri-state (with pull-up) SLK when T is not accessed by. 0 TMI TM0 TMLK GN INT# SI V SO SK GN KOUT UINTX X UINTX.0MHz Saronix SRX VU T PL GNO VO X X V TNR TPR GN RNR RPR VRM 0 V SINP SINN HP LON GN V LOP HN VRN VRP VRM 0.uF 0 SINP SINN HP LON LP HN VRN VRP 0.uF 0 0.0uF 0pF VU 0.uF R. R. 00pF U SMTV U Pulse T00 TTXFR R 0 UTXFRR UTXFRR.0uF Layout Note: Keepout rea, No Power or GN planes Signal Trace = 0 mils, route all traces on top signal layer UTXFRR U P00S F FUS Width of Tip and Ring traces should be 0 mils TIP RING P GN GN RJ LK_U drives MLK_SL when ISN U Interface is functional. lternate source for MLK_SL is the /U Interface. Note - MLK_ is controlled by the PLv0. LIN LIN LOUT LOUT *0.0uF *0.0uF Rev.0: dded S/T to U connection LIN LIN R *0 R * R * LOUT R *0K *0.0uF R *0 LOUT R0 *0K *0.0uF TNR TPR RNR RPR 0.0uF NOT: VU is isolated from V plane. onnect at single point. VU V Front View RJ onnector omponent Side View Mounting Hole Layout 0 PINS: - NP MOUNTING HOLS:, 0 SHIL MOUNTING HOLS:, oard dge () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ISN Terminal dapter (Reference esign) - ISN U Interface x. ISN_U.SH. ate: Monday, May, Sheet of

23 RJ onnector Front View omponent Side View Mounting Hole Layout 0 PINS: - NP MOUNTING HOLS:, SHIL MOUNTING HOLS:, 0 oard dge RT.0uF RSLRTRIP RRT_.K U RTRIP R 0 RSLRRR R.K P RJ GN GN 0 FR RJFR FUS RSISTOR FR 0.uF RJFR TISPTIP TISPRING Protection ircuit TISP0 U TIP G N TISP0 K GN GN RING K X 00pF X 00pF RRT_ K RSLRTRIP RSLTIP RSLHP HP 0.0uF RSLHP RTRIP (TIP) HP HP RSGH RSGL VTX RSN R RSGH RSLRSGH.K RSGL_ RSLRSGL *0 RT RSLRR K RSLRSN R_ RSLRG.K R_ RSLR.K T 00pF RT K _ 0.uF RRX_ 00K RR_ 0.0K VIN RSLI0 VOUT RSLI RSLI[0..] () FUS RSISTOR M0V [VT] -0 Volts MV [VT] - Volts V0 RSLRING 0.uF IO V0 IO V0 0.uF RSLVT RSLVT (RING) mr N RYOUT RYOUT RY N 0 VT VT GN/GN GN RR T# RINGIN V VNG 0 RR_ RSLRR RSLRNGIN 0.0K VP 0.uF RSLRRX MV 0.uF RSLW 0K SLW 0.uF IO ZNR ROHM RSZ R_ 0.0uF RSLI_ RSLI RSLI_ RSLI RSLI_ RSLI RSLI_ RSLI RSLI_ RINGIN_ () RSLI VP V NOT: P and P 0 mil traces connected to GN plane at single point. No V or GN plane in this area. M0V is a 0 mil trace. MV is a 0 mil trace. MV is a 0 mil trace. VP is a 0 mil trace connected to V at a single point. () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ISN Terminal dapter (Reference esign) - RSLI Page x. POTS_RSLI.SH. ate: Monday, May, Sheet of

24 RJ onnector Front View omponent Side View Mounting Hole Layout 0 PINS: - NP MOUNTING HOLS:, SHIL MOUNTING HOLS:, 0 oard dge RT.0uF RSLRTRIP RRT_.K U RTRIP R 0 RSLRRR R.K P RJ GN GN 0 FR RJFR FUS RSISTOR 0.uF FR RJFR TISPTIP TISPRING Protection ircuit TISP0 U TIP G N TISP0 K GN GN RING K X 00pF X 00pF RRT_ K RSLRTRIP RSLTIP RSLHP HP 0.0uF RSLHP RTRIP (TIP) HP HP RSGH RSGL VTX RSN R RSGH RSLRSGH.K RSGL_ RSLRSGL *0 RT RSLRR K RSLRSN R_ RSLRG.K R_ RSLR.K T 00pF RT K _ 0.uF RRX_ 00K RR_ 0.0K VIN VOUT RSLI0 RSLI RSLI[0..] () FUS RSISTOR M0V [VT] -0 Volts MV [VT] - Volts V0 RSLRING IO V0 0.uF IO V0 RSLVT (RING) RYOUT RSLVT VT RYOUT RY N 0 VT GN/GN GN RR N T# RINGIN V VNG 0 RR_ RSLRR 0.0K RSLRNGIN VP MV RSLRRX SLW 0.uF R_ 0.0uF RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RINGIN_ () RSLW 0K RSLI RSLI RSLI RSLI RSLI 0.uF mr 0.uF 0 0.uF IO ZNR ROHM RSZ VP V NOT: P and P 0 mil traces connected to GN plane at single point. No V or GN plane in this area. M0V is a 0 mil trace. MV is a 0 mil trace. MV is a 0 mil trace. VP is a 0 mil trace connected to V at a single point. () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ISN Terminal dapter (Reference esign) - RSLI Page x. POTS_RSLI.SH. ate: Monday, May, Sheet of

25 MLK_SL V V RSLI[0..] () PIO functions as separate chip select for individual programming of POTs channels PM[0..] (,,) 0.uF 0.uF 0.uF 0.uF 0 0.uF RSLI[0..] () VIN VOUT RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ RSLI_ VOUT VIN U RSLI0 VIN RSLI VOUT RSLI RSLI RSLI RSLI RSLI HLK RSLI RSLI RSLI RSLI RSLI RSLI VOUT RSLI0 VIN m0 MLK X R PLK FS TS# S# S# LK IO RSV V GN V V GN V PLK_SL FS_SL STS# R *0 Rev..: Removed resistor pop options. [PIO] 0.uF 0.uF 0.uF 0.uF TX RX PM PM TS# () PIO RSN V MV MV V VP R0 0K R 0 V R 0K SN () SLK (,) ST (,) 0 0 M-0-0 PLV0 PL- 0 0 R 00K INVRF VIN TMFR TMFINM IN+ St/Gt TMFST () TMFGS IN- St () INT GS [0..] 0.uF R 00K VRF St (,,,) I Q Rev..: orrected I Q TMF bit ordering. TMFX Q 0 OS Q TMFX 0 TMFO OS O V X V Vss VIN ().MHz cliptek -.M-ITR 0 R 00K TMFR TMFINM 0.uF R 00K 0pF TMFX U U INVRF IN+ TMFGS IN- GS VRF I I OS OS TMF M-0-0 St/Gt St St Q Q Q Q O TMF M V Vss TMFSTGT TMFSTGT TMFST 0 V TMFO R 00K 0.uF R 00K () INT [0..] (,,,) Rev..: orrected TMF bit ordering. V () () () () () () STS# TX TS# PS # PS # TX 0 U LK/I0 I I I I I I I I I I0 GN V I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O0 I 0 V TMFO TMFO () RX PTX () TX R 0 U PL SRIPTION TMFO = PS; TMFO = PS; TX = TX; NL_Y STS RX = TX; NL_Y TS TMFO is an inverted PS#/PIO used for TMF O. TMFO is an inverted PS#/PIO used for TMF O. TX is the m TX output when the SL is NOT transmitting on the PM bus. This is needed in case the HL TS s are configured in muxed mode and a POTS line is needed. The m TX output will be tristated when the POTS interface is transmitting. RX is the m TX output when PM channel is transmitting. This is used if the m is required to transmit data to the SL. () () () () MLK_ LK_ RSOUT LK Rev..: dded data clock. 0 U0 LK/I0 I I I I I I I I I I0 GN V I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O0 I 0 V SL locking Options Mode PLK_S FS_S MLK_S S/T SP S/T SP with LK Sync S/T IOM- with GI/PM onv S/T IOM S/T IOM- with LK Sync U PM Rev..: dded to SL clocking options. JP PLK_PL LK_ () LK () LK () FS () FS 0 MLK_ MMLK_ LK HR X JP HR X PLK_SL FS_SL MLK_SL GN PLV0 PL- GN PLV0 PL- U0 is used to define the clocking used for the SL device. The SL is a PM device only and may require clocking modifications for PLK, FS, and MLK, if PLK is asynchronous to MLK. locking options provided allow synchronous and asynchronous clocking based on clock masters running in PM and GI mode. Options include : ) GI master - Use LK, FS, and MLK outputs from master device. ) GI master - Use PL to derive correct timing from GI master for MLK and PLK. FS is a direct connection from GI master. ) GI/PM conversion - PLK and FS are generated from the LK and FS outputs from the m device. x. ) PM master - PLK ans FS are a direct connection from the PM master device. ate: () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name m ISN Terminal dapter (Reference esign) - SL POTS_SL.SH. Monday, May, Sheet 0 of

26 V V 0.uF SP GN V Y Y Y Y 0 Y 0 Y 0 *SPR LN onnection P MLK_SL SLK ST INT TX SN RX FS LK STS# 0 0 ONNTOR GP If using the external LN board to interface to a SL device, all connections on JP and JP must be removed. PIO RSOUR SSIGNMNTS PIO SIGNL FUNTIONLITY HIP SLT SSIGNMNTS HIP SLTS VI INTRF INTRRUPT SSIGNMNTS INTRRUPT VI POLRITY PIO PIO PIO PIO PIO PIO0 PIO RTR RTR_# PS# TS# TS_ RLK_ TLK_ L ISN L ISN L ISN FOR SL T SLK NTL POTS LIN RINGING SIGNL POTS LIN RINGING SIGNL MS0# PS# PS# PS# PS# SRM PNetIS II TMF O TMF O IT IT IT IT IT INT INT INT T PNetIS II TIV LOW G TIV HIGH G TIV LOW G () dvanced Micro evices, Inc. (00) - 0. en White lvd. ustin, TX M Proprietary/ll Rights Reserved esign Name Router/ISN evelopment Module - Miscellaneous x. MIS.SH. ate: Monday, May, Sheet of