Scalable Cryogenic Control Systems for Quantum Computers

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Electronics and Analytics ZEA-2: Electronic Systems 2017-11-23 Carsten Degenhardt,

1 SCIENCE Electronic ZEA-2 Systems Engineering Needs and Challenges in Scalable Cryogenic Control Systems for Quantum Computers Central Institute of Engineering, Electronics and Analytics ZEA-2: Electronic Systems Carsten Degenhardt, Andre Kruth, Lotte Geck, Patrick Vliex, Dennis Nielinger, Christian Grewing, Stefan van Waasen

2 Outline Forschungszentrum Jülich Scalable Control Electronics for Qubits Top-Down System Design Bottom-Up Implementation First Results Next Steps 2

3 Campus location ZEA-2: Electronic Systems 3

4 Forschungszentrum Jülich GmbH Founded: Employees: > 5700 approx scientists approx. 540 PhD students approx. 900 guest scientists approx. 360 apprentices and trainees Budget: 525 m. incl. 190 m. third-party funding 1.8 bn. project executing org. 4

5 ZEA-2 System House for Science Application Areas Detector Systems Measurement Systems Nano- and Microelectronic Systems R & D Competences Mixed-Signal Hardware Systems Digital Hardware Systems Integrated Systems Software Systems Modelling and Algorithmics 5

Nano- and Microelectronic Systems Today Development, testing and verification of highly integrated mixed-signal ICs (65nm node, in

effort, material) Develop scalable and flexible implementations to share development costs between multiple applications) Tomorrow

) intelligence into the chip Low power, area efficiency, 3D packaging Include optical technologies Central Under-water Unit (CUU)

6 Nano- and Microelectronic Systems Today Development, testing and verification of highly integrated mixed-signal ICs (65nm node, in future: 40nm, 28nm) System Engineering (V-Model, Top-Down, Bottom-Up) Platform creation (Chip development is expensive (time, effort, material) Develop scalable and flexible implementations to share development costs between multiple applications) Tomorrow Embed more and more configurable (digital!) intelligence into the chip Low power, area efficiency, 3D packaging Include optical technologies Central Under-water Unit (CUU) HVVDD HVGND RXGND RXVDD PMTCLK PMTCTRL PMTSIG n n n n HVCTRL HVSTAT n RXCTRL 4.7mm RESETN ipmt (JUNO) HV (Mars) RX (Vulcan) IOCLK 32 SIGNAL HVOUT HVGND Prototype chip in TSMC 65nm RXINL RXINM RXINH MEMCLK PMT RAM n MEMCTRL uc 6

7 Highly Integrated Systems-on-Chip (SoC) Solutions for ever Increasing Demands in Science and Research 7

8 Control Electronics for Quantum Computers Goal Design, implement and test scalable control electronics for quantum computers Challenges Scalability (area, power consumption, interface; operate thousands and millions of qubits in parallel) Cryogenic environment with very limited cooling power (few Milliwatts in total at < 100mK) Area restrictions for 1:1 coupling of electronics with qubits Interface to room temperature electronics Take advantage of custom build integrated circuits Dilution refrigerator oxford-instruments.com 8

Control Electronics for Quantum Computers Current

50-100 qubits Further scaling very difficult

9 Control Electronics for Quantum Computers Current Approaches Brute force scaling to operate up to qubits Further scaling very difficult Homulle et al., IEEE Trans. Circuits & Systems 63 (2016), pp Lamb et al., Rev. Sci. Inst. 87 (2016), pp. 1-7 Mohseni et al., Nature 543 (2017), pp

10 Vision of a scalable QC Fully integrated QC chip with simple interface Control chip 3D interconnect Qubit chip 10

11 Electronics Design Approaches Top Down Design Bottom Up Implementation Start from high level system design Specify system and interfaces Elaborate model Start from basic component Design and test component Assemble subsystem with several components Combine results from both approaches for functional system with detailed component characteristics 11

12 High Level System Design: Functionality Quantum Algorithm Operation Error Correction, Operation Execution Control, Readout Qubits Qubit gate Main functional components: Bias Generation: DC voltages to tune qubit into operating point RF: Pulses for operational control of Qubit (gate sequences) Memory: Storage of voltage levels and pulse forms Control: I/F to outside and sequencing 12

13 High Level System Design: Internal Structure Qubit bias Qubit gate 13

14 Bias Voltage Generation Qubit gate Capacitor based Digital to Analog Converter (DAC) Multiplex and hold 14

15 System Design and Modeling Elaborate model Matlab Simulink/ SystemVerilog Schematic Advantages: Adaptability towards parameter changes Unaffected by inaccuracy of device models Early estimations of critical circuit properties (area, power, interface) and identification of dominant contributors Schematic with extracted parasitics 15

16 System Model and Area Estimation 16

17 CMOS Chip Demonstrator Goal: Show proof-of-principle for operating GaAs spin qubits at T < 100mK by custom IC Use of 65nm bulk CMOS process No cryogenic device models available Working with extrapolated models and data Design focus: Qubit Chip Wire Bonds CMOS Chip Ultra low power (1mW cooling power) Scalability High-Fidelity Qubit Gates 17

18 DC Biasing Voltages For GaAs qubits, 8-10 DC bias voltages are needed per qubit Design of Digital-to-Analog Converter (DAC) Generate extremely stable (order of µv) biasing voltages to form potential well Multiplexing to reduce area and power consumption: sharing one DAC with multiple bias electrodes C E B E B E B E C Readout C B B B C Readout RF RF RF RF Qubit 1 Qubit 2 18

19 DC DAC Conceptual Overview Logic & Control Charge-Redistribution Digital-to-Analog Converter Multiplexed Output Channel 10 Output Channel Counter LSB MSB Charge-Redistribution DAC topology DAC_Input_Sw Change_MSBs Logic 13x5Bit Trans_Gate_Sw (20+1)x13bit Channel level cache DAC_Discharge EN_Chan<9:0> Component Fine tuning Coarse tuning 1V 875mV 750mV 625mV 500mV 375mV 250mV 125mV GND 3Bit 10Bit 125mV Trans_Gate_Sw EN_Chan<0> Transmission gate with dummy MOS Power consumption per V DD =1.2V VOUT Simulated noise at 100 mk (with RT models): V RMS 1.3 µv Voltage ripple < 10µV DAC 1 µw Transmission Gates 7 µw Control & Memory 12 µw Total 20 µw Promising first result; ten to twenty qubits could be operated with 1 mw cooling budget 19

20 RF DAC Pulse shapes for performing qubit gates The pulses for the Qubit control are obtained by an optimization algorithm for optimum fidelity Various parameters influence pulse shape Number of segments Rise time Sampling time Noise 20

21 RF DAC Quantization After optimizing the pulse shape, quantization is applied and the fidelity is evaluated Beyond a certain number of bits, quantization is no longer the limiting factor for fidelity Large scale integration for QC is not about rebuilding room-temperature electronics but opens up completely new approaches/possibilities. This needs intense and open-minded discussions between all involved parties (qubit experts, theoreticians, engineers, ) to tap the full potential of large scale integration for quantum computing. 21

22 Next Steps Top-down Include model representation of qubits Factor in error correction properties Define interface between control system and surroundings Define figures of merit Bottom-up Implement and characterize AC/DC DACs Model, implement and characterize readout circuits Setting up test environment (4K cryostat, test-stand) Device and circuit characterization 22

23 The Team Dr. Carsten Degenhardt 13 years experience in semiconductor industry and academia Dr. Andre Kruth 14 years IC design experience in industry and academia Lotte Geck PhD student, Master in EE Christian Grewing 20 years IC design experience in industry and academia? NN, PhD student (cryogenic test environment and device characterization) Dennis Nielinger PhD student, Master in EE Patrick Vliex PhD student, Master in EE? NN, PhD student (integrated qubit readout) 23

ZEA-2 Facts & Figures Approx. 100 employees approx. 65 scientists, engineers und technicians approx. 12 doctoral researchers (PhD students) approx.

24 ZEA-2 Facts & Figures Approx. 100 employees approx. 65 scientists, engineers und technicians approx. 12 doctoral researchers (PhD students) approx. 10 students (Bachelor/Master) 4 administrative staff members approx. 15 apprentices (SW Eng., electronics, IT, administration) Thank You! Funding 70% PoF-Funding (cooperation with 12 institutes) 20% interne Leistungsverrechnung (contracts) 10% Third-Party funding

Design Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor

Design Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor Hendrik Bluhm Andre Kruth Lotte Geck Carsten Degenhardt 1 0 Ψ 1 Quantum Computing