STK25CA8 128K x 8 AutoStore nvsram QuantumTrap CMOS Nonvolatile Static RAM Module

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Dorothy Randall
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1 128K x 8 AutoStore nvsram QuantumTrap CMOS Nonvolatile Static RAM Module FATURS Nonvolatile Storage without Battery Problems Directly Replaces 128K x 8 Static RAM, Battery- Backed RAM or PROM 35ns and 45ns Access Times STOR to Nonvolatile lements Initiated by AutoStore on Power Down RCALL to SRAM on Power Restore 22mA I CC at 200ns Cycle Time Unlimited RAD, RIT and RCALL Cycles 1,000,000 STOR Cycles to Nonvolatile lements 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) 32-Pin 600 mil Dual In-Line Module DSCRIPTION Preliminary The Simtek STK25CA8 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the Nonvolatile lements. Data transfers from the SRAM to the Nonvolatile lements (the STOR operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Nonvolatile lements to the SRAM (the RCALL operation) take place automatically on restoration of power. BLOCK DIAGRAM PIN CONFIGURATIONS A 15 A 16 A 5 A 6 A 7 A 8 A 9 A 11 A 12 A 13 A 14 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 RO DCODR INPUT BUFFRS MODUL DCODR STATIC RAM ARRAY 512 x 512 COLUMN I/O COLUMN DC QUANTUM TRAP 512 x 512 A 0 A 1 A 2 A 3 A 4 A 10 STOR RCALL STOR/ RCALL CONTROL V CC POR CONTROL G NC A 16 A 14 A 12 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 DQ 0 DQ 1 DQ 2 V SS PIN NAMS V CC A 15 NC A 13 A 8 A 9 A 11 G A 10 DQ 7 DQ 6 DQ 5 DQ 4 DQ mil Dual In-Line Module A 0 - A 16 Address Inputs rite nable DQ 0 - DQ 7 Data In/Out Chip nable G Output nable V CC Power (+ 5V) V SS Ground January Document Control # ML0021 rev 0.0

2 ABSOLUT MAXIMUM RATINGS a Voltage on Input Relative to V SS V to (V CC + 0.5V) Voltage on DQ V to (V CC + 0.5V) Temperature under Bias C to 125 C Storage Temperature C to 150 C Power Dissipation DC Output Current (1 output at a time, 1s duration) mA Note a: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTRISTICS (V CC = 5.0V ± 10%) SYMBOL PARAMTR Note b: I CC1 and I CC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: I CC2 and I CC4 are the average currents required for the duration of the respective STOR cycles (t STOR ). Note d: V IH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TST CONDITIONS COMMRCIAL b I CC1 Average V CC Current I c CC2 b I CC3 Average V CC Current at t AVAV = 200ns I CC4 c I SB d I ILK INDUSTRIAL MIN MAX MIN MAX UNITS ma ma t AVAV = 35ns t AVAV = 45ns NOTS Average V CC Current During STOR ma All Inputs Don t Care, V CC = max Average V CC Current During AutoStore Cycle V CC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current ma ma 9 9 ma ±2 ±2 µa (V CC 0.2V) All Others Cycling, CMOS Levels All Inputs Don t Care (V CC 0.2V) All Others V IN 0.2V or (V CC 0.2V) V CC = max V IN = V SS to V CC I OLK Off-State Output Leakage Current ±10 ±10 µa V CC = max V IN = V SS to V CC, or G V IH V IH Input Logic 1 Voltage 2.2 V CC V CC +.5 V All Inputs V IL Input Logic 0 Voltage V SS V SS V All Inputs V OH Output Logic 1 Voltage V I OUT = 4mA V OL Output Logic 0 Voltage V I OUT = 8mA T A Operating Temperature C Input Pulse Levels V to 3V Input Rise and Fall Times ns Input and Output Timing Reference Levels V Output Load See Figure 1 5.0V 480 Ohms CAPACITANC e (T A = 25 C, f = 1.0MHz) SYMBOL PARAMTR MAX UNITS CONDITIONS C IN Input Capacitance 20 pf V = 0 to 3V OUTPUT 255 Ohms 30 pf INCLUDING SCOP AND FIXTUR C OUT Output Capacitance 28 pf V = 0 to 3V Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading January Document Control # ML0021 rev 0.0

3 SRAM RAD CYCLS #1 & #2 (V CC = 5.0V ± 10%) SYMBOLS STK25CA8-35 STK25CA8-45 NO. #1, #2 Alt. PARAMTR MIN MAX MIN MAX UNITS 1 t LQV t ACS Chip nable Access Time ns 2 t f AVAV t RC Read Cycle Time ns 3 t g AVQV t AA Address Access Time ns 4 t GLQV t O Output nable to Data Valid ns 5 g t AXQX t OH Output Hold after Address Change 5 5 ns 6 t LQX t LZ Chip nable to Output Active 5 5 ns 7 t h HQZ t HZ Chip Disable to Output Inactive ns 8 t GLQX t OLZ Output nable to Output Active 0 0 ns 9 t h GHQZ t OHZ Output Disable to Output Inactive ns 10 e t LICCH t PA Chip nable to Power Active 0 0 ns 11 t d, e HICCL t PS Chip Disable to Power Standby ns Note f: must be high during SRAM RAD cycles and low during SRAM RIT cycles. Note g: I/O state assumes, G, < V IL and > V IH ; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM RAD CYCL #1: Address Controlled f, g ADDRSS DQ (DATA OUT) 5 t AXQX 2 t AVAV 3 t AVQV DATA VALID SRAM RAD CYCL #2: Controlled f ADDRSS 6 t LQX 2 t AVAV 1 t LQV 1 t HICCL 7 t HQZ G DQ (DATA OUT) I CC STANDBY 8 t GLQX 10 t LICCH 4 t GLQV ACTIV DATA VALID 9 t GHQZ January Document Control # ML0021 rev 0.0

4 SRAM RIT CYCLS #1 & #2 (V CC = 5.0V ± 10%) NO. SYMBOLS STK25CA8-35 STK25CA8-45 PARAMTR #1 #2 Alt. MIN MAX MIN MAX UNITS 12 t AVAV t AVAV t C rite Cycle Time ns 13 t LH t LH t P rite Pulse idth ns 14 t LH t LH t C Chip nable to nd of rite ns 15 t DVH t DVH t D Data Set-up to nd of rite ns 16 t HDX t HDX t DH Data Hold after nd of rite 0 0 ns 17 t AVH t AVH t A Address Set-up to nd of rite ns 18 t AVL t AVL t AS Address Set-up to Start of rite 0 0 ns 19 t HAX t HAX t R Address Hold after nd of rite 0 0 ns 20 h, i t LQZ t Z rite nable to Output Disable ns 21 t HQX t O Output Active after nd of rite 5 5 ns Note i: Note j: If is low when goes low, the outputs remain in the high-impedance state. or must be V IH during address transitions. SRAM RIT CYCL #1: Controlled j ADDRSS 12 t AVAV 14 t LH 19 t HAX 18 t AVL 17 t AVH 13 t LH DATA IN DATA OUT PRVIOUS DATA 20 t LQZ 15 t DVH DATA VALID HIGH IMPDANC 16 t HDX 21 t HQX SRAM RIT CYCL #2: Controlled j ADDRSS 12 t AVAV 18 t AVL 14 t LH 19 t HAX 17 t AVH 13 t LH 15 t DVH 16 t HDX DATA IN DATA VALID DATA OUT HIGH IMPDANC January Document Control # ML0021 rev 0.0

5 AutoStore /POR-UP RCALL (V CC = 5.0V ± 10%) SYMBOLS STK25CA8 NO. PARAMTR UNITS NOTS Standard MIN MAX 22 t RSTOR Power-up RCALL Duration 550 µs k 23 t STOR STOR Cycle Duration 10 ms g 24 t DLAY Time Allowed to Complete SRAM Cycle 1 µs g 25 V SITCH Low Voltage Trigger Level V 26 V RST Low Voltage Reset Level 3.9 V Note k: t RSTOR starts from the time V CC rises above V SITCH. AutoStore /POR-UP RCALL V CC 5V 25 V SITCH 26 V RST AutoStore 23 t STOR POR-UP RCALL 22 t RSTOR 24 t DLAY DQ (DATA OUT) POR-UP RCALL BRON OUT NO STOR DU TO NO SRAM RITS BRON OUT AutoStore BRON OUT AutoStore NO RCALL (V CC DID NOT GO BLO V RST ) NO RCALL (V CC DID NOT GO BLO V RST ) RCALL HN V CC RTURNS ABOV V SITCH January Document Control # ML0021 rev 0.0

6 DVIC OPRATION The STK25CA8 is a versatile memory module that provides two modes of operation. The STK25CA8 can operate as a standard 128K x 8 SRAM. It has a 128K x 8 Nonvolatile lements shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode. NOIS CONSIDRATIONS Note that the STK25CA8 is a high-speed memory and so must have a high frequency bypass capacitor of approximately 0.1µF connected between V CC and V SS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM RAD The STK25CA8 performs a RAD cycle whenever and G are low and is high. The address specified on pins A 0-16 determines which of the 131,072 data bytes will be accessed. hen the RAD is initiated by an address transition, the outputs will be valid after a delay of t AVQV (RAD cycle #1). If the RAD is initiated by or G, the outputs will be valid at t LQV or at t GLQV, whichever is later (RAD cycle #2). The data outputs will repeatedly respond to address changes within the t AVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until or G is brought high. SRAM RIT A RIT cycle is performed whenever and are low. The address inputs must be stable prior to entering the RIT cycle and must remain stable until either or goes high at the end of the cycle. The data on the common I/O pins DQ 0-7 will be written into the memory if it is valid t DVH before the end of a controlled RIT or t DVH before the end of an controlled RIT. It is recommended that G be kept high during the entire RIT cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers t LQZ after goes low. AutoStore OPRATION The STK25CA8 uses the intrinsic system capacitance to perform an automatic store on power down. As long as the system power supply takes at least t STOR to decay from V SITCH down to 3.6V the STK25CA8 will safely and automatically store the SRAM data in Nonvolatile lements on power down. In order to prevent unneeded STOR operations, automatic STORs will be ignored unless at least one RIT operation has taken place since the most recent STOR or RCALL cycle. POR-UP RCALL During power up, or after any low-power condition (V CC < V RST ), an internal RCALL request will be latched. hen V CC once again exceeds the sense voltage of V SITCH, a RCALL cycle will automatically be initiated and will take t RSTOR to complete. If the STK25CA8 is in a RIT state at the end of power-up RCALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between and system V CC or between and system V CC. HARDAR PROTCT The STK25CA8 offers hardware protection against inadvertent STOR operation and SRAM RITs during low-voltage conditions. hen V CAP < V SITCH, all externally initiated STOR operations and SRAM RITs are inhibited. LO AVRAG ACTIV POR The STK25CA8 draws significantly less current when it is cycled at times longer than 50ns. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK25CA8 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of RADs to RITs; 5) the operating temperature; 6) the V CC level; and 7) I/O loading. January Document Control # ML0021 rev 0.0

7 ORDRING INFORMATION STK25CA8 - D 45 I Temperature Range Blank = Commercial (0 to 70 C) I = Industrial ( 40 to 85 C) Access Time 35 = 35ns 45 = 45ns Package D = 32-pin 600 mil Dual In-Line Module January Document Control # ML0021 rev 0.0

8 Document Revision History Revision Date Summary 0.0 January 2003 January Document Control # ML0021 rev 0.0

STK20C x 8 nvsram QuantumTrap CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs

STK20C x 8 nvsram QuantumTrap CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs 512 x 8 nvsram QuantumTrap CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs FATURS 25ns, 35ns and 45ns Access Times STOR to Nonvolatile lements Initiated by Hardware RCALL to SRAM Initiated