A0-A14. January /21

Size: px

Start display at page:

Download "A0-A14. January /21"

Jesse Charles
5 years ago
Views:

1 256 Kbit (32Kb x8) Parallel PROM with Software Data Protection PRLIMINARY DATA FAST ACCSS TIM: 90ns at 5V 120ns at 3V SINL SUPPLY VOLTA: 5V±10% for M V to 3.6V for M28256-xx LO POR CONSUMPTION FAST RIT CYCL: 64 Bytes Page rite Operation Byte or Page rite Cycle NHANCD ND of RIT DTCTION: Data Polling Toggle Bit STATUS RISTR HIH RLIABILITY DOUBL POLYSILICON, CMOS TCHNOLOY: ndurance >100,000 rase/rite Cycles Data Retention >10 Years JDC APPROVD BYTID PIN OUT ADDRSS and DATA LATCHD ON-CHIP SOFTAR DATA PROTCTION 28 1 PDIP28 (BS) 28 1 SO28 (MS) 300 mils Figure 1. Logic Diagram PLCC32 (KA) TSOP28 (NS) 8 x13.4mm VCC DSCRIPTION The M28256 and M28256-are 32K x8 low power Parallel PROM fabricatedwith STMicroelectronics proprietary double polysilicon CMOS technology. A0-A DQ0-DQ7 Table 1. Signal Names M28256 A0-A14 DQ0-DQ7 Address Input Data Input / Output rite nable Chip nable VCC Output nable Supply Voltage VSS AI01885 V SS round January /21 This is preliminaryinformationon a new productnow in developmentor undergoing evaluation. Detail s aresubject to change without notice.

2 Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS M AI01886 VCC A13 A8 A9 A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 A6 A5 A4 A3 A2 A1 A0 NC DQ0 9 A7 A12 A14 DU V CC A13 DQ1 DQ M28256 VSS DU DQ3 DQ4 DQ5 25 A8 A9 A11 NC A10 DQ7 DQ6 AI01887 arning: NC = Not Connected, DU = Don t Use. Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS M VCC A13 A8 24 A9 23 A A10 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3 A11 A9 A8 A13 VCC A14 A12 A7 A6 A5 A4 A M A10 DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 AI01888 AI /21

3 Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit TA Ambient Operating Temperature (2) 40to85 C T ST Storage Temperature Range 65 to 150 C V CC Supply Voltage 0.3 to 6.5 V V IO Input/Output Voltage 0.3 to V CC +0.6 V V I Input Voltage 0.3 to 6.5 V V SD lectrostatic Discharge Voltage (Human Body model) (3) 4000 V Notes: 1. xcept for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. xposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUR Program and other relevant quality documents. 2. Depends on range pF through 1500Ω; MIL-STD-883C, Figure 3. Block Diagram V PP N RST CONTROL LOIC A6-A14 (Page Address) A0-A5 ADDRSS LATCH ADDRSS LATCH X DCOD 256K ARRAY Y DCOD SNS AND DATA LATCH I/O BUFFRS DQ0-DQ7 PA LOAD TIMR STATUS TOL BIT DATA POLLIN AI /21

4 Table 3. Operating Modes (1) Mode DQ0 - DQ7 Read V IL V IL V IH Data Out rite V IL V IH V IL Data In Standby / rite Inhibit V IH X X Hi-Z rite Inhibit X X VIH Data Out or Hi-Z rite Inhibit X V IL X Data Out or Hi-Z Output Disable X VIH X Hi-Z Notes: 1. X = V IH or V IL. DSCRIPTION (Cont d) The devices offer fast access time with low power dissipation and requires a 5V or 3V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Data Polling and Toggle Bit and access to a status register. The devices support a 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JDC algorithm. PIN DSCRIPTION Addresses (A0-A14). The address inputs select an 8-bit memory location during a read or write operation. Chip nable (). The chip enable input must be low to enable all read/write operations. hen Chip nable is high, power consumption is reduced. Output nable (). The Output nable input controls the data output buffers and is used to initiate read operations. Data In/ Out (DQ0- DQ7). Data is written to or read from the memory through the I/O pins. rite nable (). The rite nable input controls the writing of data to the memory. OPRATIONS rite Protection In order to prevent data corruption and inadvertent write operations; an internal VCC comparatorinhibits rite operations if V CC is below VI (see Table 7 andtable 9).Access to the memoryin write mode is allowed after a power-up as specified in Table 7 and Table 9. Read The device is accessed like a static RAM. hen and are low with high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either or is high. rite rite operations are initiated when both and are low and is high.the device supports both and controlled write cycles. The Address is latched by the falling edge of or which ever occurs last and the Data on the rising edge of or which ever occurs first. Once initiated the write operation is internally timed until completion and the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6 is controlled accordingly. Page rite Page write allows up to 64 bytes within the same page to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A14-A6 must be the same for all bytes; if not, the Page rite instruction is not executed. The page write can be initiated by any byte write operation. A page write is composed of successive rite instructions which have to be sequenced with a specific period of time between two consecutive rite instructions, period of time which has to be smaller than the t HH value (see Table 12 and Table 13). If this period of time exceeds the thh value, the internal programmingcycle will start. Once initiated the write operation is internally timed until completion and the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6 is controlled accordingly. 4/21

5 Status Register The devices provide several rite operation status flags that can be used to minimize the application write time. These signals are available on the I/O port bits during programming cycle only. Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. Toggle bit (DQ6). The devices offer another way for determining when the internal write cycle is completed. During the internal rase/rite cycle, DQ6 will toggle from 0 to 1 and 1 to 0 (the first read value is 0 ) on subsequent attempts to read any byte of the memory. hen the internal cycle is completed the toggling will stop and the data read on DQ7-DQ0 is the addressed memory byte. The deviceis now accessiblefor a new Read or rite operation. Page Load TimerStatus bit(dq5). Duringa Page rite instruction, the devices expect to receive the stream of data with a minimum period of time between each data byte. This period of time (thh) is defined by the on-chip Page Load timer which running/overflow status is available on DQ5. DQ5 Low indicates that the timer is running, DQ5 High indicates the time-out after which the internal write cycle will start. Figure 4. Status Bit Assignment DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS X X X X X DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status Software Data Protection The devices offer a software controlled write protection facility that allows the user to inhibit all write modes to the device. This can be useful in protecting the memory from inadvertent write cycles that may occur due to uncontrolledbus conditions. The devices are shipped as standardin the unprotected state meaning that the memory contents can be changedas required by the user. After the Software Data Protection enable algorithm is issued, the device enters the Protect Mode of operation where no further write commands have any effect on the memory contents. The devices remain in this mode until a valid Software Data Protection (SDP) disable sequence is received whereby the device reverts to its unprotected state. The Software Data Protection is fully non-volatile and is not changed by power on/off sequences. To enable the Software Data Protection (SDP) the device requires the user to write (with a Page rite addressing three specific data bytes to three specific memorylocations, each location in a different page) as per Figure 6. Similarly to disable the Software Data Protection the user has to write specific data bytes into six different locations as per Figure 5 (with a Page rite adressing different bytes in different pages). This complexseries ensures that the userwill never enable or disable the Software Data Protection accidentally. To write into the devices when SDP is set, the sequence shown in Figure 6 must be used. This sequence provides an unlock key to enable the write action, and at the same time SDP continues to be set. An extension to this is where SDP is required to be set, and data is to be written. Using the same sequence as above, the data can be written and SDP is set at the same time, giving both these actions in the same rite cycle (tc). 5/21

6 Figure 5. Software Data Protection nable Algorithm and Memory rite SDP Set SDP not Set RIT AAh in Address 5555h RIT AAh in Address 5555h Page rite Instruction RIT 55h in Address 2AAAh RIT A0h in Address 5555h SDP is set Page rite Instruction RIT 55h in Address 2AAAh RIT A0h in Address 5555h RIT Data to be ritten in any Address RIT is enabled SDP NABL ALORITHM rite in Memory rite Data + SDP Set after tc AI01698B Figure 6. Software Data Protection Disable Algorithm RIT AAh in Address 5555h RIT 55h in Address 2AAAh Page rite Instruction RIT 80h in Address 5555h RIT AAh in Address 5555h RIT 55h in Address 2AAAh RIT 20h in Address 5555h Unprotected State after tc (rite Cycle time) AI01699B 6/21

7 Table 4. AC Measurement Conditions Input Rise and Fall Times 20ns Input Pulse Voltages (M28256) 0.4V to 2.4V Input Pulse Voltages (M28256-) 0V to V CC 0.3V Input and Output Timing Ref. Voltages (M28256) 0.8V to 2.0V Input and Output Timing Ref. Voltages (M28256-) 0.5 V CC Figure 7. AC Testing Input Output aveforms Figure 8. AC Testing quivalent Load Circuit 4.5V to 5.5V Operating Voltage 2.4V 2.0V 0.4V 2.7V to 3.6V Operating Voltage 0.8V DVIC UNDR TST I OL OUT V CC 0.3V I OH C L = 100pF 0.5 V CC 0V AI02101B C L includes JI capacitance AI02102B Table 5. Capacitance (1) (TA =25 C, f = 1 MHz ) Note: Symbol Parameter Test Condition Min Max Unit C IN Input Capacitance V IN =0V 6 pf C OUT Output Capacitance V OUT =0V 12 pf 1. Sampled only, not 100% tested. Table 6. Read Mode DC Characteristics for M28256 (TA = 0 to 70 C or 40 to 85 C; VCC = 4.5V to 5.5V) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC 10 µa I LO Output Leakage Current 0V V IN V CC 10 µa ICC (1) Supply Current (TTL inputs) = V IL,=V IL,f=5MHz 30 ma Supply Current (CMOS inputs) = V IL,=V IL,f=5MHz 25 ma I CC1 (1) Supply Current (Standby) TTL = V IH 1 ma ICC2 (1) Supply Current (Standby) CMOS > VCC 0.3V 100 µa V IL Input Low Voltage V V IH Input High Voltage 2 V CC V V OL Output Low Voltage I OL = 2.1 ma 0.4 V V OH Output High Voltage I OH = 400 µa 2.4 Note: 1. All I/O s open circuit. 7/21

8 Table 7. Power Up Timing for M28256 (1) (TA = 0 to 70 C or 40 to 85 C; VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit t PUR Time Delay to Read Operation 1 µs t PU Time Delay to rite Operation (once V CC V I ) 5 ms Note: V I rite Inhibit Threshold V 1. Sampled only, not 100% tested. Table 8. Read Mode DC Characteristics for M (TA = 0 to 70 C or 40 to 85 C; VCC = 2.7V to 3.6V) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC 10 µa I LO Output Leakage Current 0V V IN V CC 10 µa ICC (1) I CC2 (1) Supply Current (CMOS inputs) =V IL,=V IL, f = 5 MHz, V CC = 3.3V 15 ma =V IL,=V IL, f = 5 MHz, V CC = 3.6V 15 ma Supply Current (Standby) CMOS > V CC 0.3V 20 µa VIL Input Low Voltage V V IH Input High Voltage 2 V CC V V OL Output Low Voltage I OL = 2.1 ma 0.2 V CC V V OH Output High Voltage I OH = 400 µa 0.8 V CC V Note: 1. All I/O s open circuit. Table 9. Power Up Timing for M (1) (TA = 0 to 70 C or 40 to 85 C; VCC = 2.7V to 3.6V) Symbol Parameter Min Max Unit t PUR Time Delay to Read Operation 1 µs t PU Time Delay to rite Operation (once V CC V I ) 10 ms Note: V I rite Inhibit Threshold V 1. Sampled only, not 100% tested. 8/21

9 Table 10. Read Mode AC Characteristics (TA = 0 to 70 C or 40 to 85 C; VCC = 4.5V to 5.5V) Symbol Alt Parameter Test Condition M min max min max min max min max Unit t AVQV t ACC Address Valid to Output Valid t LQV t C Chip nable Low to Output Valid t LQV t O Output nable Low to Output Valid =V IL,=V IL ns =V IL ns =V IL ns t HQZ (1) t DF Chip nable High to Output Hi-Z =V IL ns t HQZ (1) t DF Output nable High to Output Hi-Z =V IL ns t AXQX t OH Address Transition to Output Transition =V IL,=V IL ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Table 11. Read Mode AC Characteristics (T A = 0 to 70 C or 40 to 85 C; V CC = 2.7V to 3.6V) Symbol Alt Parameter Test Condition M Unit min max min max min max min max t AVQV t ACC Address Valid to Output Valid t LQV t C Chip nable Low to Output Valid t LQV t O Output nable Low to Output Valid =V IL,=V IL ns =V IL ns =V IL ns t HQZ (1) t DF Chip nable High to Output Hi-Z =V IL ns t HQZ (1) t DF Output nable High to Output Hi-Z =V IL ns t AXQX t OH Address Transition to Output Transition =V IL,=V IL ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. 9/21

10 Table 12. rite Mode AC Characteristics (TA = 0 to 70 C or 40 to 85 C; VCC = 4.5V to 5.5V) Symbol Alt Parameter Test Condition Min M28256 Max Unit t AVL t AS Address Valid to rite nable Low = V IL,=V IH 0 ns t AVL t AS Address Valid to Chip nable Low = V IH,=V IL 0 ns tll tcs Chip nable Low to rite nable Low = VIH 0 ns t HL t OS Output nable High to rite nable Low =V IL 0 ns t HL t OS Output nable High to Chip nable Low = V IL 0 ns t LL t S rite nable Low to Chip nable Low = V IH 0 ns t LAX t AH rite nable Low to Address Transition 50 ns t LAX t AH Chip nable Low to Address Transition 50 ns t LDV t DV rite nable Low to Input Valid = V IL,=V IH 1 µs t LDV t DV Chip nable Low to Input Valid = V IH,=V IL 1 µs tlh tp Chip nable Low to Chip nable High 50 ns t HH t CH rite nable High to Chip nable High 0 ns t HL t OH rite nable High to Output nable Low 0 ns t HL t OH Chip nable High to Output nable Low 0 ns t HH t H Chip nable High to rite nable High 0 ns t HDX t DH rite nable High to Input Transition 0 ns t HDX t DH Chip nable High to Input Transition 0 ns t HL t PH rite nable High to rite nable Low 100 ns t LH t P rite nable Low to rite nable High 50 ns t HH t BLC Byte Load Repeat Cycle Time µs t HRH t C rite Cycle Time 5 ms t L,t L or Input Filter Pulse idth Note 1 10 ns tdvh tds Data Valid before rite nable High 50 ns t DVH t DS Data Valid before Chip nable High 50 ns Note: 1. Characterized only but not tested in production. 10/21

11 Table 13. rite Mode AC Characteristics (TA = 0 to 70 C or 40 to 85 C; VCC = 2.7V to 3.6V) Symbol Alt Parameter Test Condition M Min Max Unit t AVL t AS Address Valid to rite nable Low = V IL,=V IH 0 ns t AVL t AS Address Valid to Chip nable Low = V IH,=V IL 0 ns tll tcs Chip nable Low to rite nable Low = VIH 0 ns t HL t OS Output nable High to rite nable Low =V IL 0 ns t HL t OS Output nable High to Chip nable Low = V IL 0 ns t LL t S rite nable Low to Chip nable Low = V IH 0 ns t LAX t AH rite nable Low to Address Transition 70 ns t LAX t AH Chip nable Low to Address Transition 70 ns t LDV t DV rite nable Low to Input Valid = V IL,=V IH 1 µs t LDV t DV Chip nable Low to Input Valid = V IH,=V IL 1 µs tlh tp Chip nable Low to Chip nable High 100 ns t HH t CH rite nable High to Chip nable High 0 ns t HL t OH rite nable High to Output nable Low 0 ns t HL t OH Chip nable High to Output nable Low 0 ns t HH t H Chip nable High to rite nable High 0 ns t HDX t DH rite nable High to Input Transition 0 ns t HDX t DH Chip nable High to Input Transition 0 ns t HL t PH rite nable High to rite nable Low 100 ns t LH t P rite nable Low to rite nable High 100 ns t HH t BLC Byte Load Repeat Cycle Time µs t HRH t C rite Cycle Time 5 ms t L,t L or Input Filter Pulse idth Note 1 10 ns tdvh tds Data Valid before rite nable High 50 ns t DVH t DS Data Valid before Chip nable High 50 ns Note: 1. Characterized only but not tested in production. 11/21

12 Figure 9. Read Mode AC aveforms A0-A14 VALID tavqv taxqx tlqv thqz DQ0-DQ7 tlqv DATA OUT thqz Hi-Z AI01700 Note: rite nable () = High. Figure 10. rite Mode AC aveforms - rite nable Controlled A0-A14 VALID tavl tlax tll thh thl tlh thl tldv thl DQ0-DQ7 DATA IN tdvh thdx AI /21

13 Figure 11. rite Mode AC aveforms - Chip nable Controlled A0-A14 VALID tavl tlax thl tlh tll thl tldv thh DQ0-DQ7 DATA IN tdvh thdx AI01702 Figure 12. Page rite Mode AC aveforms - rite nable Controlled A0-A14 Addr 0 Addr 1 Addr 2 Addr n thl thrh tlh thh thh DQ0-DQ7 Byte 0 Byte 1 Byte 2 Byte n DQ5 Byte n AI01703B 13/21

14 Figure 13. Software Protected rite Cycle aveforms tlh thl thh tavl tlax A0-A5 Byte Address thdx A6-A h 2AAAh 5555h Page Address tdvh DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63 AI01704 Note: A6 through A14 must specify the same page address during each high to low transition of (or ) after the software code has been entered. must be high only when and are both low. Figure 14. Data Polling aveform Sequence A0-A14 Address of the last byte of the Page rite instruction DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 LAST RIT INTRNAL RIT SQUNC RADY AI /21

15 Figure 15. Toggle Bit aveform Sequence A0-A14 DQ6 (1) DQ6 DQ6 LAST RIT TOL INTRNAL RIT SQUNC RADY AI01706 Note: 1. First Toggle bit is forced to 0. 15/21

16 ORDRIN INFORMATION SCHM xample: M KA 6 T Speed Operating Voltage Package Temperature Range Option 90 (1) 90ns ns blank 4.5V to 5.5V 2.7V to 3.6V BS PDIP28 KA PLCC32 1 (3) 0to70 C 6 40 to 85 C T Tape & Reel Packing ns MS SO mils ns 25 (2) 250ns NS TSOP28 8 x 13.4mm Notes: 1. Not available for operating voltage. 2. Available for operating voltage only. 3. Temperature Range on request only. Devices are shipped from the factory with the memory content set at all 1 s (FFh). For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/21

17 PDIP28-28 pin Plastic DIP, 600 mils width Symb mm inches Typ Min Max Typ Min Max A A A B B C D D e ea eb L S α N A2 A A1 B1 B e1 D2 L α ea eb C S D N 1 1 PDIP Drawing is not to scale. 17/21

18 PLCC32-32 lead Plastic Leaded Chip Carrier, rectangular Symb mm inches Typ Min Max Typ Min Max A A A B B D D D e F R N Nd 7 7 Ne 9 9 D D1 A2 A1 1 N B1 Ne 1 F 0.51 (.020) D2/2 B e 1.14 (.045) Nd A PLCC R CP Drawing is not to scale. 18/21

19 SO28-28 lead Plastic Small Outline, 300 mils body width Symb mm inches Typ Min Max Typ Min Max A A B C D e H L α N CP A2 A C B e CP D N H 1 A1 α L SO-b Drawing is not to scale. 19/21

20 TSOP28-28 lead Plastic Thin Small Outline, 8 x 13.4mm Symb mm inches Typ Min Max Typ Min Max A A A B C D D e L α N CP A e 28 1 B 7 8 D1 D A CP DI C TSOP-c A1 α L Drawing is not to scale. 20/21

21 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved STMicroelectronics ROUP OF COMPANIS Australia - Brazil - Canada - China - France - ermany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 21/21

M28C16A M28C17A. 16 Kbit (2Kb x8) Parallel EEPROM

M28C16A M28C17A. 16 Kbit (2Kb x8) Parallel EEPROM M28C16A M28C17A 16 Kbit (2Kb x8) Parallel PROM FAST ACCSS TIM: 150ns at 5V 250ns at 3V SINL SUPPLY VOLTA: 5V ± 10% for M28C16A and M28C17A 2.7V to 3.6V for M28C16-xx LO POR CONSUMPTION FAST RIT CYCL 32