M28C16A M28C17A. 16 Kbit (2Kb x8) Parallel EEPROM

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1 M28C16A M28C17A 16 Kbit (2Kb x8) Parallel PROM FAST ACCSS TIM: 150ns at 5V 250ns at 3V SINL SUPPLY VOLTA: 5V ± 10% for M28C16A and M28C17A 2.7V to 3.6V for M28C16-xx LO POR CONSUMPTION FAST RIT CYCL 32 Bytes Page rite Operation Byte or Page rite Cycle: 5ms NHAD ND OF RIT DTCTION Ready/Busy Open Drain Output Data Polling Toggle Bit PA LOAD TIMR STATUS BIT HIH RLIABILITY SINL POLYSILICON, CMOS TCHNOLOY ndurance >100,000 rase/rite Cycles Data Retention >40 Years JDC APPROVD BYTID PIN OUT 28 1 PDIP28 (BS) 28 1 SO28 (MS) 300 mils Figure 1. Logic Diagram PLCC32 (KA) TSOP28 (NS) 8 x13.4mm DSCRIPTION The M28C16A and M28C17Aare 2K x8 low power Parallel PROM fabricatedwith STMicroelectronics proprietarysingle polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V or 3V power supply. A0-A10 11 V CC 8 DQ0-DQ7 Table 1. Signal Names A0-A10 Address Input DQ0-DQ7 Data Input / Output rite nable M28C16A M28C17A RB Chip nable RB Output nable Ready / Busy VSS AI02109 V CC Supply Voltage V SS round August /19

2 Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections RB A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS M28C17A VCC DU A8 A9 A10 DQ7 DQ6 DQ5 DQ4 DQ3 A6 A5 A4 A3 A2 A1 A0 DQ0 9 A7 RB or DU VCC DU M28C16A M28C17A 25 A8 A9 A10 DQ7 DQ6 AI02110 DQ1 DQ2 VSS DQ3 DQ4 DQ5 AI02111 arning: = Not Connected, DU = Don t Use. arning: = Not Connected, DU = Don t Use. Note: 1. Pin 2 is either RB for M28C17A or for M28C16A. Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections RB A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 VCC DU 4 25 A A M28C17A 8 21 A DQ DQ DQ DQ DQ3 AI02112 A9 A8 DU VCC RB A7 A6 A5 A4 A M28C16A AI02113 A10 DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 arning: = Not Connected, DU = Don t Use. arning: = Not Connected, DU = Don t Use. 2/19

3 Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit TA Ambient Operating Temperature (2) 40to85 C T ST Storage Temperature Range 65 to 150 C V CC Supply Voltage 0.3 to 6.5 V V IO Input/Output Voltage 0.3 to V CC +0.6 V V I Input Voltage 0.3 to 6.5 V V SD lectrostatic Discharge Voltage (Human Body model) 3000 V Notes: 1. xcept for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. xposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUR Program and other relevant quality documents. 2. Depends on range. Table 3. Operating Modes Mode DQ0 - DQ7 Read VIL VIL VIH Data Out rite V IL V IH V IL Data In Standby / rite Inhibit V IH X X Hi-Z rite Inhibit X X V IH Data Out or Hi-Z rite Inhibit X V IL X Data Out or Hi-Z Output Disable X V IH X Hi-Z Note: X=VIH or VIL DSCRIPTION (cont d) The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C16A/17A supports 32 byte page write operation. PIN DSCRITPION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip nable (). The chip enable input must be low to enable all read/write operations. hen Chip nable is high, power consumption is reduced. Output nable (). The Output nable input controls the data output buffers and is used to initiate read operations. Data In/Out (DQ0 - DQ7). Data is writtento or read from the M28C16A/17A through the I/O pins. rite nable (). The rite nable input controls the writing of data to the M28C16A/17A. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. Ready/Busy is available for the M28C17A in PDIP, PLCC and SO packages, and for the M28C16A in TSOP only. OPRATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset(POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C16A/17Ais accessed like a static RAM. hen and are low with high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either or is high. 3/19

4 Figure 3. Block Diagram V PP N RST CONTROL LOIC A6-A10 (Page Address) A0-A5 ADDRSS LATCH ADDRSS LATCH X DCOD 64K ARRAY Y DCOD SNS AND DATA LATCH I/O BUFFRS DQ0-DQ7 PA LOAD TIMR STATUS TOL BIT DATA POLLIN AI01520 OPRATION (cont d) rite rite operations are initiated when both and are low and is high.the M28C16A/17Asupports both and controlled write cycles. The Address is latched by the falling edge of or which ever occurs last and the Data on the rising edge of or which ever occurs first. Once initiated the write operation is internally timed until completion. Page rite Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a Figure 4. Status Bit Assignment DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status programming cycle. All bytes must be located in a single page address, that is A5 - A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data up to a maximum of thh after the risingedge of or which ever occurs first. If a transition of or is not detected within thh, the internal programming cycle will start. Microcontroller Control Interface The M28C16A/17A provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. 4/19

5 Table 4. AC Measurement Conditions Input Rise and Fall Times 20ns Input Pulse Voltages 0.4V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2.0V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Input Output aveforms Figure 6. AC Testing quivalent Load Circuit 4.5V to 5.5V Operating Voltage V CC 2.4V 2.0V 0.4V 2.7V to 3.6V Operating Voltage V CC 0.3V 0.8V DVIC UNDR TST I OL I OH OUT C L = 30pF 0.5 V CC 0V AI02101B C L includes JI capacitance AI02114 Table 5. Capacitance (TA =25 C, f = 1 MHz ) Symbol Parameter Test Condition Min Max Unit C IN Input Capacitance V IN =0V 6 pf Note: C OUT Output Capacitance V OUT =0V 12 pf 1. Sampled only, not 100% tested. Table 6. Read Mode DC Characteristics for M28C16A and M28C17A (TA = 40 to 85 C, VCC = 4.5V to 5.5V) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC 10 µa I LO Output Leakage Current 0V V IN V CC 10 µa I CC I CC1 I CC2 Supply Current (TTL and CMOS inputs) = V IL,=V IL, f = 5MHz 25 ma Supply Current (Standby) TTL = V IH 1 ma Supply Current (Standby) CMOS > V CC 0.3V 50 µa VIL Input Low Voltage V V IH Input High Voltage 2 V CC V V OL Output Low Voltage I OL = 2.1 ma 0.4 V V OH Output High Voltage I OH = 400 µa 2.4 V Note: 1. All I/O s open circuit. 5/19

6 Table 7. Power Up Timing for M28C16A and M28C17A (TA = 40 to 85 C, VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit t PUR Time Delay to Read Operation 1 µs t PU Time Delay to rite Operation (once V CC V I ) 10 ms Note: V I rite Inhibit Threshold V 1. Sampled only, not 100% tested. Table 8. Read Mode DC Characteristics for M28C16A- (T A = 40 to 85 C, V CC = 2.7V to 3.6V) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC 10 µa I LO Output Leakage Current 0V V IN V CC 10 µa I CC I CC2 Supply Current (TTL and CMOS inputs) = V IL,=V IL,f=5MHz 15 ma Supply Current (Standby) CMOS > V CC 0.3V 20 µa V IL Input Low Voltage V V IH Input High Voltage 2 V CC V V OL Output Low Voltage I OL = 2.1 ma 0.2 V CC V V OH Output High Voltage I OH = 400 µa 0.8 V CC V Note: 1. All I/O s open circuit. Table 9. Power Up Timing for M28C16A- (T A = 40 to 85 C, V CC = 2.7V to 3.6V) Symbol Parameter Min Max Unit t PUR Time Delay to Read Operation 1 µs tpu Time Delay to rite Operation (once VCC VI) 10 ms V I rite Inhibit Threshold V Note: 1. Sampled only, not 100% tested. 6/19

7 Table 10. Read Mode AC Characteristics for M28C16A and M28C17A (T A = 40 to 85 C, V CC = 4.5V to 5.5V) Symbol Alt Parameter Test Condition M28C16A / M28C17A min max min max Unit t AVQV t ACC Address Valid to Output Valid t LQV t C Chip nable Low to Output Valid t LQV t O Output nable Low to Output Valid =V IL,=V IL ns =V IL ns =V IL ns t HQZ t DF Chip nable High to Output Hi-Z =V IL ns t HQZ t DF Output nable High to Output Hi-Z =V IL ns t AXQX t OH Address Transition to Output Transition Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. =V IL,=V IL 0 0 ns Table 11. Read Mode AC Characteristics for M28C16- (TA = 40 to 85 C, VCC = 2.7V to 3.6V) Symbol Alt Parameter Test Condition M28C16A / M28C17A min max min max Unit t AVQV t ACC Address Valid to Output Valid t LQV t C Chip nable Low to Output Valid t LQV t O Output nable Low to Output Valid =V IL,=V IL ns =V IL ns =V IL ns t HQZ t DF Chip nable High to Output Hi-Z =V IL ns t HQZ t DF Output nable High to Output Hi-Z =V IL ns t AXQX t OH Address Transition to Output Transition Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. =V IL,=V IL 0 0 ns 7/19

8 Figure 7. Read Mode AC aveforms A0-A10 VALID tavqv taxqx tlqv thqz DQ0-DQ7 tlqv DATA OUT thqz Hi-Z AI01511B Note: rite nable () = High Toggle bit (DQ6). The M28C16A/17A offers another way for determining when the internal write cycle is completed. During the internal rase/rite cycle, DQ6 will toggle from 0 to 1 and 1 to 0 (the first read value is 0 ) on subsequentattempts to read any address in the memory. hen the internalcycle is completedthe togglingwill stopand the device will be accessible for a new Read or rite operation. Page Load Timer Status bit (DQ5). In the Page rite mode data may be latched by or up to thh after the previous byte. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output nable Low (t PLTS ). DQ5 Low indicates the timer is running, High 8/19

9 Table 12. rite Mode AC Characteristics for M28C16A and M28C17A (TA = 40 to 85 C, VCC = 4.5V to 5.5V) Symbol Alt Parameter Test Condition Min Max Unit tavl tas Address Valid to rite nable Low = VIL, = VIH 0 ns t AVL t AS Address Valid to Chip nable Low = V IH,=V IL 0 ns tll tcs Chip nable Low to rite nable Low = VIH 0 ns t HL t OS Output nable High to rite nable Low =V IL 0 ns t HL t OS Output nable High to Chip nable Low = V IL 0 ns t LL t S rite nable Low to Chip nable Low = V IH 0 ns t LAX t AH rite nable Low to Address Transition 100 ns t LAX t AH Chip nable Low to Address Transition 100 ns t LDV t DV rite nable Low to Input Valid = V IL,=V IH 1 µs t LDV t DV Chip nable Low to Input Valid = V IH,=V IL 1 µs t LH t P Chip nable Low to Chip nable High 100 ns t HH t CH rite nable High to Chip nable High 0 ns thl toh rite nable High to Output nable Low 0 ns thl toh Chip nable High to Output nable Low 0 ns t HH t H Chip nable High to rite nable High 0 ns thdx tdh rite nable High to Input Transition 0 ns t HDX t DH Chip nable High to Input Transition 0 ns t HL t PH rite nable High to rite nable Low 200 ns t LH tp rite nable Low to rite nable High 100 ns t HH t BLC Byte Load Repeat Cycle Time µs t HRH t C rite Cycle Time 5 ms t HRL t DB rite nable High to Ready/Busy Low Note ns t HRL t DB Chip nable High to Ready/Busy Low Note ns t DVH t DS Data Valid before rite nable High 50 ns t DVH t DS Data Valid before Chip nable High 50 ns Note: 1. ith a 3.3 kω external pull-up resistor. 9/19

10 Table 13. rite Mode AC Characteristics for M28C16- (TA = 40 to 85 C, VCC = 2.7V to 3.6V) Symbol Alt Parameter Test Condition Min Max Unit tavl tas Address Valid to rite nable Low = VIL, = VIH 0 ns t AVL t AS Address Valid to Chip nable Low = V IH,=V IL 0 ns tll tcs Chip nable Low to rite nable Low = VIH 0 ns t HL t OS Output nable High to rite nable Low =V IL 0 ns t HL t OS Output nable High to Chip nable Low = V IL 0 ns t LL t S rite nable Low to Chip nable Low = V IH 0 ns t LAX t AH rite nable Low to Address Transition 200 ns t LAX t AH Chip nable Low to Address Transition 200 ns t LDV t DV rite nable Low to Input Valid = V IL,=V IH 1 µs t LDV t DV Chip nable Low to Input Valid = V IH,=V IL 1 µs t LH t P Chip nable Low to Chip nable High 200 ns t HH t CH rite nable High to Chip nable High 0 ns thl toh rite nable High to Output nable Low 0 ns thl toh Chip nable High to Output nable Low 0 ns t HH t H Chip nable High to rite nable High 0 ns thdx tdh rite nable High to Input Transition 0 ns t HDX t DH Chip nable High to Input Transition 0 ns t HL t PH rite nable High to rite nable Low 200 ns t LH tp rite nable Low to rite nable High 200 ns t HH t BLC Byte Load Repeat Cycle Time µs t HRH t C rite Cycle Time 5 ms t HRL t DB rite nable High to Ready/Busy Low Note ns t HRL t DB Chip nable High to Ready/Busy Low Note ns t DVH t DS Data Valid before rite nable High 50 ns t DVH t DS Data Valid before Chip nable High 50 ns Note: 1. ith a 3.3 kω external pull-up resistor. 10/19

11 Figure 8. rite Mode AC aveforms - rite nable Controlled A0-A10 VALID tavl tlax tll thh thl tlh thl tldv thl DQ0-DQ7 DATA IN tdvh thdx RB thrl AI01512 Figure 9. rite Mode AC aveforms - Chip nable Controlled A0-A10 VALID tavl tlax thl tlh tll thl tldv thh DQ0-DQ7 DATA IN tdvh thdx RB thrl AI /19

12 Figure 10. Page rite Mode AC aveforms - rite nable Controlled A0-A10 Addr 0 Addr 1 Addr 2 Addr n tplts thl thrh tlh thh thh DQ0-DQ7 Byte 0 Byte 1 Byte 2 Byte n DQ5 Byte n thrl RB AI01514 Figure 11. Data Polling aveform Sequence A0-A10 Address of the last byte of the Page rite instruction DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 LAST RIT INTRNAL RIT SQU RADY AI /19

13 Figure 12. Toggle Bit aveform Sequence A0-A10 DQ6 LAST RIT TOL INTRNAL RIT SQU RADY AI01517 Note: 1. First Toggle bit is forced to 0 13/19

14 ORDRIN INFORMATION SCHM xample: M28C16 20 NS 6 T Device Identifier C16 RB available only for the TSOP package C17 RB available T Option Tape & Reel Packing Speed Operating Voltage Package Temperature Range ns ns 25 (2) 250ns 30 (2) 300ns blank 4.5V to 5.5V 5ms write 2.7V to 3.6V 5ms write BS MS NS PDIP28 SO mils TSOP28 8 x 13.4mm 6 40 to 85 C KA PLCC32 Notes: 1. Available for M28C16A and M28C17A only. 2. Available for Operating Voltage only. Devices are shipped from the factory with the memory content set at all 1 s (FFh). For a listof availableoptions (Speed, Package,etc... ) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 14/19

15 PDIP28-28 pin Plastic DIP, 600 mils width Symb mm inches Typ Min Max Typ Min Max A A A B B C D D e ea eb L S α N A2 A A1 B1 B e1 D2 L α ea eb C S D N 1 1 PDIP Drawing is not to scale. 15/19

16 PLCC32-32 lead Plastic Leaded Chip Carrier, rectangular Symb mm inches Typ Min Max Typ Min Max A A A B B D D D e F R N Nd 7 7 Ne 9 9 CP D D1 A2 A1 1 N B1 Ne 1 F 0.51 (.020) D2/2 B e 1.14 (.045) Nd A PLCC R CP Drawing is not to scale. 16/19

17 SO28-28 lead Plastic Small Outline, 300 mils body width Symb mm inches Typ Min Max Typ Min Max A A A B C D e H L α N CP A2 A C B e CP D N H 1 A1 α L SO-b Drawing is not to scale. 17/19

18 TSOP28-28 lead Plastic Thin Small Outline, 8 x 13.4mm Symb mm inches Typ Min Max Typ Min Max A A A B C D D e L α N CP A e 28 1 B 7 8 D1 D A CP DI C TSOP-c A1 α L Drawing is not to scale. 18/19

19 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics STMicroelectronics - All Rights Reserved STMicroelectronics ROUP OF COMPANIS Australia - Brazil - Canada - China - France - ermany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 19/19

A0-A14. January /21

A0-A14. January /21 256 Kbit (32Kb x8) Parallel PROM with Software Data Protection PRLIMINARY DATA FAST ACCSS TIM: 90ns at 5V 120ns at 3V SINL SUPPLY VOLTA: 5V±10% for M28256 2.7V to 3.6V for M28256-xx LO POR CONSUMPTION