STD5N20L N-CHANNEL 200V Ω - 5A DPAK STripFET MOSFET
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1 N-CHANNEL 200V Ω - 5A DPAK STripFET MOSFET Table 1: General Features TYPE V DSS R DS(on) I D Pw Figure 1: Package STD5N20L 200 V < 0.7 Ω 5 A 33 W TYPICAL R DS (on) = V CONDUCTION LOSSES REDUCED LOW INPUT CAPACIATNCE LOW THRESHOLD DEVICE DESCRIPTION The STD5N20L utilizes the latest advanced design rules of ST s proprietary STripFET technology. This is suitable for the most demanding DC Motor Control and lighting application. 1 DPAK 3 Figure 2: Internal Schematic Diagram APPLICATIONS UPS AND MOTOR CONTROL LIGHTING Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STD5N20LT4 D5N20L DPAK TAPE & REEL Rev. 3 September 2004 NEW DATASHEET ACCORDING TO PCN DSG-TRA/04/532 1/10
2 Table 3: Absolute Maximum ratings Symbol Parameter Value Unit V DS Drain-source Voltage (V GS = 0) 200 V V DGR Drain-gate Voltage (R GS = 20 kω) 200 V V GS Gate- source Voltage ±20 V I D Drain Current (continuous) at T C = 25 C 5 A I D Drain Current (continuous) at T C = 100 C 3.6 A I DM ( ) Drain Current (pulsed) 20 A P TOT Total Dissipation at T C = 25 C 33 W Derating Factor 0.27 W/ C T stg Storage Temperature T j Operating Junction Temperature ( ) Pulse width limited by safe operating area 55 to 150 C Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max 3.75 C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 C/W T l Maximum Lead Temperature For Soldering Purpose 275 C ELECTRICAL CHARACTERISTICS (T CASE =25 C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol Parameter Test Conditio Min. Typ. Max. Unit V (BR)DSS Drain-source I D = 250 µa, V GS = V Breakdown Voltage I DSS Zero Gate Voltage V DS = Max Rating 1 µa Drain Current (V GS = 0) V DS = Max Rating, T C = 125 C 10 µa I GSS Gate-body Leakage V GS = ±20V ±100 na Current (V DS = 0) V GS(th) Gate Threshold Voltage V DS = V GS, I D = 50µA V R DS(on) Static Drain-source On Resistance V GS = 5 V, I D = 2.5 A Ω 2/10
3 Table 6: Dynamic Symbol Parameter Test Conditio Min. Typ. Max. Unit g fs (2) Forward Traconductance V DS = 15 V, I D = 5 A 6.5 S C iss C oss C rss t d(on) t r t d(off) t f Q g Q gs Q gd Input Capacitance Output Capacitance Reverse Trafer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge V DS = 25V, f = 1 MHz, V GS = V DD = 100 V, I D = 2.5 A R G = 4.7Ω, V GS = 5V (Resistive Load see Figure 14) V DD = 160 V, I D = 5 A, V GS = 5V pf pf pf 6 nc nc nc Table 7: Source Drain Diode Symbol Parameter Test Conditio Min. Typ. Max. Unit I SD Source-drain Current 5 A I SDM (*) Source-drain Current (pulsed) 20 A V SD (1) Forward On Voltage I SD = 5 A, V GS = V t rr Q rr I RRM t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Starting T j =25 C, I d = 5 A, V DD = 50 V (*) Pulse width limited by safe operating area I SD = 5 A, di/dt = 100 A/µs, V DD = 100 V, T j = 25 C (see test circuit, see Figure 15) I SD = 5 A, di/dt = 100 A/µs, V DD = 100 V, T j = 150 C (see test circuit, see Figure 15) nc A nc A 3/10
4 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Trafer Characteristics Figure 5: Traconductance Figure 8: Static Drain-source On Resistance 4/10
5 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variatio Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics 5/10
6 Figure 14: Switching Times Test Circuit For Resistive Load Figure 16: Gate Charge Test Circuit Figure 15: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/10
7 TO-252 (DPAK) MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A A B B C C D E G H L L V2 0 o 8 o 0 o 0 o P032P_B 7/10
8 DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimeio are in millimeters All dimeio are in millimeters TAPE AND REEL SHIPMENT (suffix T4 )* REEL MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. MAX. A B C D G N T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. MAX. A B B D D E F K P P P R W BASE QTY BULK QTY * on sales type 8/10
9 Table 8: Revision History Date Revision Description of Changes 08-June New Stylesheet. Datasheet according to PCN DSG-TRA/04/ Sep Changes on Table 3, and on Figure 3. 9/10
10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10
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3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 16ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
BUK A. N-channel TrenchMOS standard level FET
Rev. 2 31 July 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
PHB108NQ03LT. N-channel TrenchMOS logic level FET
Rev. 4 2 February 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
STPS2030CT/CG/CR LOW DROP POWER SCHOTTKY RECTIFIER MAJOR PRODUCTS CHARACTERISTICS. 2x10A 30 V Tj (max) 150 C
STPS23CT/CG/CR LOW DROP POWER SCHOTTY RECTIFIER MAJOR PRODUCTS CHARACTERISTICS I F(AV) V RRM 2xA 3 V Tj (max) 5 C V F (max).4 V FEATURES AND BENEFITS VERY SMALL CONDUCTION LOSSES NEGLIGIBLE SWITCHING LOSSES
PHP/PHD3055E. TrenchMOS standard level FET. Product availability: PHP3055E in SOT78 (TO-220AB) PHD3055E in SOT428 (D-PAK).
PHP/PHD355E Rev. 6 25 March 22 Product data 1. Description N-channel standard level field-effect power transistor in a plastic package using TrenchMOS 1 technology. Product availability: PHP355E in SOT78
TO-247-3L Inner Circuit Product Summary I C) R DS(on)
Silicon Carbide Power MOSFET N-CHANNEL ENHANCEMENT MODE TO-247-3L Inner Circuit Product Summary V DS I D(@25 C) R DS(on) 1200V 20A 120mΩ Features u Low On-Resistance u Low Capacitance u Avalanche Ruggedness
PSMN4R5-40PS. N-channel 40 V 4.6 mω standard level MOSFET. High efficiency due to low switching and conduction losses
Rev. 2 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in TO22 package qualified to 175 C. This product is designed and qualified for use in a wide
PHD/PHP36N03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 General description. 1.
Rev. 2 8 June 26 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2
BTA/BTB24, BTA25, BTA26 and T25 Series
BTA/BTB24, BT5, BT6 and T25 Series SNUBBERLESS & STANDARD 25A TRIACS MAIN FEATURES: Symbol Value Unit I T(RMS) 25 A V DRM /V RRM 6 and 8 V I T (Q1 ) 35 to 5 ma DESCRIPTION Available either in through-hole
PHD110NQ03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.
M3D3 Rev. 1 16 June 24 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features Logic level threshold
PSMN013-80YS. N-channel LFPAK 80 V 12.9 mω standard level MOSFET
Rev. 1 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
SPECIFICATIONS (T J = 25 C, unless otherwise noted)
N-Channel V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) () I D (A) a, e Q g (Typ.). at V GS = V. at V GS = 4.5 V nc DFN 3x3 EP Top View Bottom View FEATURES APPLICATIONS Top View D 3 4 8 7 6 5 G Pin
Obsolete Product(s) - Obsolete Product(s)
DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT HIGH SPEED: t PD = 16ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
DO-15 DO-201AD STTH3R04Q STTH3R04
STTH3R4 Ultrafast recovery diode Features Negligible switching losses Low forward and reverse recovery times High junction temperature Description The STTH3R4 series uses ST's new 4 V planar Pt doping
2SJ182(L), 2SJ182(S)
Silicon P-Channel MOS FET November 1996 Application High speed power switching Features Low on-resistance High speed switching Low drive current 4 V gate drive device Can be driven from V source Suitable
PSMN2R6-40YS. N-channel LFPAK 40 V 2.8 mω standard level MOSFET
Rev. 1 23 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
Package. TAB Drain. Symbol Parameter Value Unit Test Conditions Note. V GS = 15 V, T C = 25 C Fig. 19 A 22.5 V GS = 15 V, T C = 100 C.
C3M651J Silicon Carbide Power MOSFET C3M TM MOSFET Technology N-Channel Enhancement Mode Features Package V DS I D @ 25 C R DS(on) 1 V 35 A 65 mω C3M TM SiC MOSFET technology Low parasitic inductance with
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 27 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
PSMN8R3-40YS. N-channel LFPAK 40 V 8.6 mω standard level MOSFET
Rev. 1 25 June 29 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 C. This product is designed and qualified for use in a
SIPMOS Power-Transistor
SPP18P6P G SIPMOS Power-Transistor Features P-Channel Enhancement mode Avalanche rated dv /dt rated 175 C operating temperature Product Summary V DS -6 V R DS(on),max.13 Ω I D -18.6 A PG-TO22-3 Type Package
Automotive N- and P-Channel 40 V (D-S) 175 C MOSFET
SQJ54EP Automotive N- and P-Channel 4 V (D-S) 75 C MOSFET 6.5 mm mm PowerPAK SO-8L Dual 5.3 mm D D 4 G 3 S G S FEATURES TrenchFET power MOSFET AEC-Q qualified % R g and UIS tested Material categorization:
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package.
M3D88 Rev. 2 2 November 21 Product data 1. Description in a plastic package using TrenchMOS 1 technology. Product availability: in SOT23. 2. Features TrenchMOS technology Very fast switching Logic level
LNTA4001NT1G S-LNTA4001NT1G. Small Signal MOSFET 20 V, 238 ma, Single, N-Channel, Gate ESD Protection LESHAN RADIO COMPANY, LTD.
Small Signal MOSFET V, 38 ma, Single, N-Channel, Gate ESD Protection Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate Pb-Free Package is Available ESD Protected:V
PSMN K. 1. Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field-effect transistor
Rev. 6 January 2 Product specification. Description SiliconMX products use the latest Philips TrenchMOS 2 technology to achieve the lowest possible on-state resistance in a SOT96- (SO8) package. Product
PSMN002-25P; PSMN002-25B
PSMN2-25P; PSMN2-25B Rev. 1 22 October 21 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS 1 technology. Product availability: PSMN2-25P
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS
LD1117A SERIES LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS LOW DROPOUT VOLTAGE (1.15V TYP. @ I OUT =1A,25 C) VERY LOW QUIESCENT CURRENT (5 ma TYP. @ 25 C) OUTPUT CURRENT UP TO 1A FIXED OUTPUT
AO7401 P-Channel Enhancement Mode Field Effect Transistor
Nov P-Channel Enhancement Mode Field Effect Transistor General Description The uses advanced trench technology to provide excellent R DS(ON), low gate charge, and operation with gate voltages as low as.5v,
PSMN4R3-30PL. N-channel 30 V 4.3 mω logic level MOSFET. High efficiency due to low switching and conduction losses
Rev. 1 16 June 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in TO22 package qualified to 175 C. This product is designed and qualified for use in a wide