9A HIGH-SPEED MOSFET DRIVERS
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1 9A HIGH-SPEED MOSFET DRIVERS 9A HIGH-SPEED MOSFET DRIVERS FEATURES Tough CMOS Construction High Peak Output Current A High Continuous Output Current A Max Fast Rise and Fall Times: 3 ns with,7 pf Load 18 ns with 7, pf Load Short Internal Delays nsec Typ Low Output Impedance Ω Typ APPLICATIONS Line Drivers for Extra-Heavily-Loaded Lines Pulse Generators Driving the Largest MOSFETs and IGBTs Local Power ON/OFF Switch Motor and Solenoid Driver PIN CONFIGURATIONS -Pin TO-22 V DD Tab is Common to V DD 8-Pin Plastic DIP/CerDIP V DD 1 8 V DD NC NOTE: Duplicate pins must both be connected for proper operation. NC = No connection GENERAL DESCRIPTION The /22 are high current buffer/drivers capable of driving large MOSFETs and IGBTs. They are essentially immune to any form of upset except direct overvoltage or over-dissipation they cannot be latched under any conditions within their power and voltage ratings; they are not subject to damage or improper operation when up to V of ground bounce is present on their ground terminals; they can accept, without either damage or logic upset, more than 1A inductive current of either polarity being forced back into their outputs. In addition, all terminals are fully protected against up to kv of electrostatic discharge. The /22 inputs may be driven directly from either TTL or CMOS (3V to 18V). In addition, 3 mv of hysteresis is built into the input, providing noise immunity and allowing the device to be driven from slowly rising or falling waveforms. ORDERING INFORMATION Part No. Package Temperature Range CAT -Pin TO-22 C to +7 C CPA 8-Pin PDIP C to +7 C EPA 8-Pin PDIP C to +8 C MJA 8-Pin CerDIP C to+12 C CAT -Pin TO-22 C to +7 C CPA 8-Pin PDIP C to +7 EPA 8-Pin PDIP C to +8 C MJA 8-Pin CerDIP C to+12 C FUNCTIONAL BLOCK DIAGRAM INVERTING V DD 3 mv NONINVERTING EFFECTIVE C 2 pf.7v / Inverting/Noninverting / /9 TelCom Semiconductor reserves the right ot make changes in the circuitry and specifications of its devices. 1
2 ABSOLUTE MAXIMUM RATINGS* Power Dissipation, T A 7 C PDIP W CerDIP mW -Pin TO W Power Dissipation, T C 2 C -Pin TO-22 (With Heat Sink) W Derating Factors (To Ambient) PDIP mW/ C CerDIP mW/ C -Pin TO mW/ C Thermal Impedance (To Case) -Pin TO-22 R ΘJ-C C/W Storage Temperature C to +1 C Operating Temperature (Chip) C Operating Temperature (Ambient) C Version C to +7 C E Version C to +8 C M Version C to +12 C Lead Temperature (1 sec) C Supply Voltage V Input Voltage (V DD +.3V) to ( - V) Input Current (V IN > V DD ) ma *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS T A = 2 C with.v V DD 18V unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Input V IH Logic 1 Input Voltage V V IL Logic Input Voltage V I IN Input Current V V IN V DD 1 1 µa Output V OH High Output Voltage See Figure 1 V DD.2 V V OL Low Output Voltage See Figure 1.2 V R O Output Resistance, High V DD = 18V, I O = 1 ma 1. Ω R O Output Resistance, Low V DD = 18V, I O = 1 ma Ω I PK Peak Output Current V DD = 18V 9 A I DC Continuous Output Current 1V V DD 18V, T C = 2 2 A (/22 CAT only) I REV Latch-Up Protection Duty Cycle 2% >1 ma Withstand Reverse Current t 3 µs Switching Time (Note 1) t R Rise Time Figure 1, C L = 1, pf 7 nsec t F Fall Time Figure 1, C L = 1, pf 7 nsec t D1 Delay Time Figure 1 3 nsec t D2 Delay Time Figure 1 33 nsec Power Supply I S Power Supply Current V IN = 3V.2 1. ma V IN = V 1 µa V DD Operating Input Voltage. 18 V Input V IH Logic 1 Input Voltage 2. V V IL Logic Input Voltage.8 V I IN Input Current V V IN V DD 1 1 µa 2
3 ELECTRICAL CHARACTERISTICS (Measured over operating temperature range with.v V S 18V unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit Input V IH Logic 1 Input Voltage 2. V V IL Logic Input Voltage.8 V I IN Input Current V V IN V DD 1 1 µa Output V OH High Output Voltage See Figure 1 V DD.2 V V OL Low Output Voltage See Figure 1.2 V R O Output Resistance, High V DD = 18V, I O = 1 ma W R O Output Resistance, Low V DD = 18V, I O = 1 ma W Switching Time (Note 1) t R Rise Time Figure 1, C L = 1, pf 12 nsec t F Fall Time Figure 1, C L = 1, pf 12 nsec t D1 Delay Time Figure 1 8 nsec t D2 Delay Time Figure 1 8 nsec Power Supply I S Power Supply Current V IN = 3V. 3 ma V IN = V..2 ma V DD Operating Input Voltage. 18 V NOTE: 1. Switching times guaranteed by design. V DD = 18V.1 µf 1 8 +V 9%.1 µf.1 µf 2 V +18V 1% t D1 9% t F t D2 t R 9% 7 C = 1, pf L V 1% 1% : khz, square wave, t RISE = t FALL 1nsec Figure 1. Switching Time Test Circuit 3
4 TYPICAL CHARACTERISTICS t RISE (ns) t RISE (ns) Rise Time vs Supply Voltage , pf , pf 8 7 pf pf V DD Rise TIme vs Capacitive Load 1V V 1V t FALL (ns) t FALL (ns) Fall Time vs Supply Voltage , pf , pf 7 pf 2 pf V DD Fall TIme vs Capacitive Load 3 V 2 1V 2 1 1V 1,, C LOAD (pf) 1, C LOAD (pf), Rise and Fall Times vs Temperature Propagation Delay vs Supply Voltage 9 8 C LOAD = 1, pf V DD= 1V C LOAD= pf TIME (ns) 7 t RISE t FALL TIME (ns) 3 3 t D1 t D T A ( C) V DD
5 TYPICAL CHARACTERISTICS (Cont.) I SUPPLY(mA) Supply Current vs Capacitive Load (V DD= 18V) 2 MHz 1.12 MHz 32 khz 2 khz 1, C LOAD(pF), 3.2 khz 2 khz I SUPPLY(mA) Supply Current vs Frequency (V DD= 18V).1 µf 7, pf 1, pf 22, pf 7 pf 7 pf 1 FREQUENCY (khz) I SUPPLY(mA) Supply Current vs Capacitive Load, Supply Current vs Frequency (V = 12) DD (V DD= 12) , pf , pf 7, pf 2 MHz khz MHz.1 µf 7 pf 32 khz 2 khz 2 2 khz 2 7 pf 1,, 1 C LOAD(pF) FREQUENCY (khz) I SUPPLY (ma) I SUPPLY (ma) 9 Supply Current vs Capacitive Load (V DD= V) 2 khz khz 3 2 MHz 32 khz khz 1,, C LOAD(pF) I SUPPLY (ma) Supply Current vs Frequency (V DD= V).1 µf 7 pf 7, pf 22, pf 1, pf 7 pf 1 FREQUENCY (khz)
6 TYPICAL CHARACTERISTICS (Cont.) TIME (ns) Propagation Delay vs Input Amplitude V DD = 1V C LOAD = V t D2 3 t D (V) TIME (ns) Propagation Delay vs Temperature t D2 t D T A( C) Crossover Energy vs Supply Voltage Quiescent Supply Current vs Temperature V DD = 18V A sec 7 1 I QUIESCENT (µa) 1 2 = 1 = V DD NOTE: The values on this graph represent the loss seen by the driver during a complete cycle. For the loss in a single transition, divide the stated value by T J ( C) R DS(ON) ( Ω ) High-State Output Resistance vs Supply Voltage.. T J = 1 C T J = 2 C V DD(V) R DS(ON) ( Ω ) Low-State Output Resistance vs Supply Voltage T J = 1 C T J = 2 C V DD(V)
7 PACKAGE DIMENSIONS 8-Pin Plastic DIP PIN 1.2 (.).2 (.1). (1.1).3 (.7). (1.1).38 (8.8).7 (1.78). (1.1).31 (7.87).29 (7.37).2 (.8).1 (3.).1 (3.81).11 (2.92). (1.2).2 (.1).1 (.38).8 (.2) 3 MIN..11 (2.79).9 (2.29).22 (.).1 (.38). (1.1).31 (7.87) 8-Pin CerDIP.11 (2.79).9 (2.29) PIN 1.3 (7.2).23 (.8). (1.) MAX..2 (.1) MIN.. (1.1).37 (9.).32 (8.13).29 (7.37).2 (.8).1 (.). (1.2).2 (.1).2 (.8).12 (3.18).1 (3.81) MIN..1 (.38).8 (.2) 3 MIN..(1.). (1.1).2 (.1).1 (.1). (1.1).32 (8.13) Dimensions: inches (mm) 7
8 PACKAGE DIMENSIONS (Cont.) -Pin TO (.7).1 (.19).28 (.).23 (.8).113 (2.87).13 (2.2).1 (1.1).39 (9.91).1 (3.9).1 (3.71) DIA.. (1.). (1.1).9 (1.9).9 (1.) 3-7. PLCS.. (1.22).18 (13.1).37 (.9).27 (.9).2 (.1).12 (.3).273 (.93).23 (.8).72 (1.83).2 (1.7).11 (2.92).9 (2.1) Dimensions: inches (mm) Sales Offices TelCom Semiconductor 13 Terra Bella Avenue P.O. Box 727 Mountain View, CA TEL: FAX: TelCom Semiconductor Austin Product Center 911 Burnet Rd. Suite 21 Austin, TX 7878 TEL: FAX: TelCom Semiconductor H.K. Ltd. 1 Sam Chuk Street, Ground Floor San Po Kong, Kowloon Hong Kong TEL: FAX: Printed in the U.S.A.
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MM54C14 MM74C14 Hex Schmitt Trigger
MM54C14 MM74C14 Hex Schmitt Trigger General Description The MM54C14 MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement
MM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
Features. Y Wide supply voltage range 3V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL compatibility Fan out of 2
CD40192BM CD40192BC Synchronous 4-Bit Up Down Decade Counter CD40193BM CD40193BC Synchronous 4-Bit Up Down Binary Counter General Description These up down counters are monolithic complementary MOS (CMOS)
CD54/74HC32, CD54/74HCT32
Data sheet acquired from Harris Semiconductor SCHS7A September 997 - Revised May 000 CD/7HC, CD/7HCT High Speed CMOS Logic Quad -Input OR Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject High Features
74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of 1996 Feb IC24 ata Handbook 1997 Mar 20 FEATURES Wide operating voltage: 1.0 to 5.5 Optimized for Low oltage
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
MM74HC573 3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch General Description The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. September 2001 S7C256 5V/3.3V 32K X 8 CMOS SRM (Common I/O) Features S7C256
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
M74HC147TTR 10 TO 4 LINE PRIORITY ENCODER
10 TO 4 LINE PRIORITY ENCODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
Features. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
Obsolete Product(s) - Obsolete Product(s)
BCD TO DECIMAL DECODER HIGH SPEED : t PD = 14ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch
CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch General Description The CD4723B is a dual 4-bit addressable latch with common control inputs including two address
CD4028BM CD4028BC BCD-to-Decimal Decoder
CD4028BM CD4028BC BCD-to-Decimal Decoder General Description The CD4028BM CD4028BC is a BCD-to-decimal or binaryto-octal decoder consisting of 4 inputs decoding logic gates and 10 output buffers A BCD
UNISONIC TECHNOLOGIES CO., LTD U74HC14
UNISONIC TECHNOLOGIES CO., LTD U74HC14 HIGH-SPEED CMOS LOGIC HEX INVERTING SCHMITT TRIGGER DESCRIPTION The UTC U74HC14 each contain six inverting Schmitt triggers in one package. Each of them perform the
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
Package Type. IXDD614PI 8-Pin DIP Tube 50 OUT 8-Lead Power SOIC with Exposed Metal Back Tube 100
IXD_64 4-Ampere Low-Side Ultrafast MOSFET Drivers Features 4A Peak Source/Sink Drive Current Wide Operating Voltage Range: 4.V to V - C to +2 C Extended Operating Temperature Range Logic Input Withstands
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet
3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky
M74HCT688TTR 8 BIT EQUALITY COMPARATOR
8 BIT EQUALITY COMPARATOR HIGH SPEED: t PD = 21ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
Octal 3-State Noninverting Transparent Latch
TECNICAL DATA IN74CT373A Octal 3-State Noninverting Transparent Latch The IN74CT373A may be used as a level converter for interfacing TTL or NMOS outputs to igh-speed CMOS inputs. The IN74CT373A is identical
CD4028BC BCD-to-Decimal Decoder
CD4028BC BCD-to-Decimal Decoder General Description The CD4028BC is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
74LV393 Dual 4-bit binary ripple counter
INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
SGM48000/1/2 High Speed, Dual Power MOSFET Drivers
SGM000// GENERAL DESCRIPTION The SGM000// ICs are matched dual-drivers. Unique circuit design provides very high speed drivers capable of delivering peak currents of A into highly capacitive loads. Improved
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
CD54/74AC153, CD54/74ACT153
CD4/74AC13, CD4/74ACT13 Data sheet acquired from Harris Semiconductor SCHS237A September 1998 - Revised May 2000 Dual 4-Input Multiplexer Features Description [ /Title (CD74 AC13, CD74 ACT1 3) /Subject