Nanolithography and Design- Technology Co-optimization Beyond 22nm

Transcription

1 Nanolithography and Design- Technology Co-optimization Beyond 22nm David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin 1

2 50+ Years Ago, Still There's Plenty of Room at the Bottom - An Invitation to Enter a New Field of Physics Richard P. Feynman, 1959 The Moore, The Better! 2

3 Outline Introduction Nanolithography for 22nm and Beyond Double Pattern Lithography Emerging Lithography Some Other Design-Technology Co-optimization Issues NBTI/PBTI 3D Integration: TSV, Stress, Reliability Conclusions 3

4 Nanometer Issues -nce Litho CMP Random defects Etch 4

5 Next Generation Lithography 193i w/ DPL EUV mindp Nanoimprint 5

6 Don t Forget Other Objectives Temp ( o C) (source: ITRS) (source: Intel) Interconnect determines the overall performance Power/leakage/thermal issues Other technology related issues: NBTI, HCI, FINFET 6

7 More Moore and More than Moore More Moore: continue pushing the envelope, 22nm, 15nm (14nm), 11nm, 8nm (ITRS) Computational Scaling (pushing 193nm) Double Patterning Emerging Nanolithography More than Moore: New design-technology cooptimization issues Vertically 3D IC integration New device/material: FINFET, optical interconnect, Nano-X 7

8 Outline Introduction Nanolithography for 22nm and Beyond: Double Pattern Lithography Emerging Lithography Some Other Design-Technology Co-optimization Issues NBTI 3D Integration: TSV, Stress, Reliability Conclusions 8

9 Double Patterning Lithography For 22nm and 16nm, the industry most likely will adopt double patterning lithography (DPL) A key problem is overlay control Double exposures, masks, Intelligent CAD solution to compensate unwanted overlay effects or even take advantage of them! [Yang et al, ASPDAC 2010] A new layout decomposition framework Graph-theoretic, multi-objective Stitch mindp 9

10 Issues with DPL Minimum Stitch Insertion Stitch Stitch 1) Yield loss with overlay 2) Area increase due to overlap margin [Lucas SPIE 08] Overlay Compensation 2 nd patterning 2 nd patterning 2 nd patterning 1 st patterning C 1 - C 1 C 2 - C 2 C 1 - C 1 C 2 + C 2 1 st patterning 1 st patterning 1 st patterning 2 nd patterning Without Overlay Compensation With Overlay Compensation 10

11 Comparisons with Previous Works Balanced Density Overlay Compensation Stitch Minimization Complexity [Yao+, ICCAD08] [Yuan+, ISPD09] [Xu+, ICCAD09] Our Framework [ASPDAC10] No No Yes (ILP) No No Yes (ILP) No No Yes (ILP) Yes Yes Yes (Bi-Partitioning) NP-Complete NP-Complete NP-Complete Polynomial Time O(NlogN) 11

12 Benefits of Balanced Density S38584:13% and 87% S38584: 50% and 50% C432:27% and 73% (7 stitches) C432:50% and 50% (17 stitches) 12

13 Overlay Compensation Result ( Weight=0.0 ) ( Weight=0.2 ) ( Weight=0.5 ) ( Weight=1.0 ) 13

14 Spacer-type DPL SADP (self-aligned double patterning) Core mask and trim mask Less overlay cf. LELE (1) target (2) core mask (3) sidewall spacer (4) trim mask 14

15 Challenges in SADP A single width of sidewall spacer Does not allow stitch points SADP currently in production only for 1D patterns NAND Flash memory applications SADP for 2D random logic patterns is challenging [Ban et al., DAC 11] proposes systematic techniques to perform layout decomposition for general 2D patterns 15

16 How to Solve Coloring Conflicts? A B C D E Coloring conflict A A C B D F D Grouping E E A F Merging D E 1 st Mask Sidewall Spacer The space/width of the merged region should be equal or larger than the minimum space/width of the trim mask. Trim mask overlay at the merged region 16 cut (open) Trimming

17 22nm Metal1 Standard Cell (1) Target layout (2) Mandrel & spacer (3) Trim mask (4) Final patterns 17

18 Electronic Beam Lithography Maskless technology, which shoots desired patterns directly into a silicon wafer Low throughput is its major hurdle Variable Shaped Beam (VSB) Total number of 11 shots are needed

19 Character Projection (CP) Technology Print some complex shapes in one electronic beam shot, rather than writing multiple rectangles. Electron Gun 3 shots only Electron Gun Shaping aperture Shaping aperture Stencil Wafer Stencil Electron Gun Electron Gun Wafer Character Shaping aperture Shaping aperture Stencil Stencil Wafer Wafer

20 Blank B Blank A BlankB BlankA Min(BlankA, BlankB) Overlapped Characters The number of characters is limited due to the area constraints of the stencil Layout A Spanned region of electron beam from shaping aperture Layout B H h Character w Character A Character B By overlapping adjacent characters/sharing blank spaces, more characters can be put on the stencil W Layout A Layout B Layout A Layout B Character A Character B Character A Character B

21 Not a Trivial Task [Yuan-Pan, ISPD 11] Character candidates to be considered A B C Stencil Order Matters A B C Out of Stencil C B A

22 Stencil Planning and Optimization #shots (projection time) #characters on stencil D-1 1D-2 1D-3 1D-4 0 1D-1 1D-2 1D-3 1D-4 NON-OVERLAP GREEDY PROPOSED NON-OVERLAP GREEDY PROPOSED #CPU(logscale) D-1 1D-2 1D-3 1D-4 NON-OVERLAP GREEDY PROPOSED 51%, 14% reduction on shot number over previous ILP-based approach without overlapping characters and greedy algorithm. 22

23 Outline Introduction Nanolithography for 22nm and Beyond: Double Pattern Lithography Emerging Lithography Some Other Design-Technology Co-optimization Issues NBTI and Clock Network Design 3D Integration: TSV, Stress, Reliability Conclusion 23

24 What is NBTI? NBTI is a key failure mechanism for PMOS Cause PMOS Vth to drift when driven by GND E.g., V TH = +60mV after 10 years 30% increase in inverter delay NBTI-Induced Skew Management in Gated Clock Trees [Chakraborty+, DATE 2009, ISPD 2010] Main problem: clock gating cause inbalance between different clock buffers/receivers Key idea: try to balance NBTI degradation Both circuit design (run time) and CAD techniques (design time) Similar principle holds for PBTI 24

25 Clock Gating Induced V TH Imbalance SP0=50% SP0=50% CLK SP0=50% SP0 = Prob. that net is at logic 0. SP0=50% GATE: 30% SP0=35% Larger V TH Lower V TH Using NAND gate reduces SP0 at output Using NOR gate increases SP0 at output In both cases, V TH mismatch will exist! Skew? 25

26 MUX [Chakraborty+, DATE 2009] CLK NOR Gated at 0 GATE CLK_OUT CLK NAND Gated at 1 SELECT If { GATE = FALSE } CLK_OUT = CLK Else If { SELECT = 0 } CLK_OUT = 0 Else CLK_OUT = 1 26

27 [Chakraborty and Pan, ISPD 10] Determine clock gating NAND/NOR during design Not runtime (less penalty and no SELECT signals) Symbolic SP0 Propagation SP0 Aware Delay Characterization Main idea: Optimally pick NAND and NOR gates for clock gating Symbolic Arrival Time Computation Skew Minimization Formulation (ILP) 27

28 Delay is Function of CLK Gating Assignment DINV(0.5) + X2 * DNAND(0.5) + X2 * DNOR(0.5) + ( X4 * DNAND( X2 * 0.5 ) + X4 * DNOR( X2 * 0.5 ) ) 28

29 Results CKT Solver Time (s) OUR Skew (ps) All NAND (ps) All NOR (ps) 10 Rand. (ps) A B C D E F G H Avg: X 2.19X 1.33X Age the circuit to 10 years Our > Rand > NAND > NOR solution Significantly tightens the skew budget 29

30 3D IC Integration Better Performance Photonics MEMS RF Memory CMOS Massive Bandwidth Reduced Interconnect Delays Power Reduction (Less IO driver) Higher Functionality/Space Heterogeneous Integration Smaller Size 3D Maximizes Space Utilization Lower Cost Lower Cost vs. Next-gen Device Reuse of Proven SIP 30 [Courtesy of Dr. H.-M., Tong, ASE]

31 3D IC Yield Y 1 = Joint Yield Memory Y 2 = Repassivation/RDL Yield Y 3 = Interface Yield Processor ELK/ULK RDL X X X X X X X X X X Y 4 = TSV Yield Y 5 = Interface Yield Y 6 = Repassivation/RDL Yield Y 7 = Joint Yield Y 8 = Joint Yield Y 9 = Substrate Yield Y 10 = Joint Yield Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Y 10 Overall Yield 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 95.0% 99.5% 99.5% 90.0% 90.0% 90.0% 99.5% 99.5% 99.5% 99.5% 99.5% 70.0% Scrap or Barely Usable Scrap [Courtesy of Dr. H.-M., Tong, ASE]

32 Thermal Stress Impact Near TSV CTE : Coefficient of thermal expansion [Dao+, ICICDT 2009] TSV: 250 C ~400 C process (Higher than operating temperature) Since Cu has larger CTE than Si, tensile stress is in Si near TSV. < Tensile stress > < Fast NFET, slow PFET with tensile stress > Cu TSV Silicon [Selvanayagam+, ECTC 08, TAP 09] 32 [H.S. Yang, IEDM 2004]

33 Stress Aware Design Flow [Yang+, DAC 10] Pre-placed TSV location Stress estimation induced by TSVs Mobility change ( μ/μ) calculation Verilog netlist Cell characterization with mobility (Cell name change in Verilog) Stress aware Verilog netlist Verilog, SPEF merging for 3D STA Liberty file having cell timing with different mobility 3D Timing Analysis with PrimeTime Critical gate selection Optimized layout with TSV stress 33 TSV stress aware layout optimization

34 Stress Effect on Mobility & Current CMOS (Stress: 200MPa, R=r) NMOS: 0.5 μ ( Ids:+1.5%) PMOS: 0.6 μ ( Ids:+1.8%) Cmos NMOS: 0.75 μ ( Ids:+2.25%) PMOS: -0.1 μ( Ids:-0.3%) Cmos TSV NMOS: μ( Ids:+3%) PMOS: - μ( Ids:-3%) Cmos FS corner Cell characterizations based on distance and orientation are needed 34

35 Cell Instantiation Depending on Location TSV2 TSV1 INVX1_P8_N14 ( μ/μ) e = +8% ( μ/μ) h = -14% I3 TSV2 TSV2 I1 KOZ INVX1_P4_P6 ( μ/μ) e = +4% ( μ/μ) h = +6% INVX1_P8_N8 ( μ/μ) e = +8% ( μ/μ) h = -8% I2 I4 INVX1_P2_0 ( μ/μ) e = +2% ( μ/μ) h = 0% KOZ Indentify hole and electron mobility variation according to TSV induced stress Rename cells based on the mobility Cell naming: INVX1_P8_N8 P8: +8% electron mobility variation N8: -8% hole mobility variation 35

36 Falling Delay Variation Rising Delay Variation Inverter Delay Dependence on Stress 30.0% 0.0% -2.0% 20.0% ( μ/μ)e=0% -4.0% ( μ/μ)h=-22% ( μ/μ)h=0% 10.0% ( μ/μ)e=12% ( μ/μ)e=24% -6.0% ( μ/μ)h=10% 0.0% -8.0% 0% 10% 20% 30% Electron Mobility Variation -10.0% -30% -20% -10% 0% 10% 20% Hole Mobility Variation μe : 0%~24% in our test case Dfalling : up to 7.5% μh : -22%~10% in our test case Drising : more than 20% 36

37 Result: Timing Analysis with Stress TSV Specification Width Landing pad KOZ Height Dielectric Resistance Capacitance 4.14um 4.54um 0.4um 20um 0.2um fF Stress effect on critical paths Circuit #Cells Without TSV stress With TSV stress Difference Longest Delay(ns) TNS(ns) 37 Longest Delay(ns) TNS(ns) Longest Delay(ns) TNS(ns) IDCT 14, % -7.7% , % 1.1% , % 5.7% MAC2 29, % 0.3% ETHERNET 77, % 1.3% RISC 88, % 22.9% B18 103, % -12.4% DES_PERT 109, % -8.1% VGA_LCD 126, % -0.9% B19 168, % -10.2% average 75, , , % -0.8%

38 Result: Timing Optimization Critical path manual optimization (Circuit: 8051) Original Optimized Timing Logic Depth Gate Hole(%) Electron (%) Gate Hole(%) Electron (%) Arc Original Delay(ns) Optimized Delay(ns) Reduction Ratio DFFPOSX1 DFFPOSX1 fall % 1 NOR3X NOR3X rise % 2 AND2X AND2X rise % 3 INVX INVX fall % 4 INVX INVX rise % 5 AND2X AND2X rise % 6 BUFX BUFX rise % 7 AOI22X AOI22X fall % 8 INVX INVX rise % 9 OR2X OR2X1 2 8 rise % 10 OR2X OR2X rise % 11 NOR3X NOR3X fall % 12 NAND3X NAND3X rise % 13 BUFX BUFX rise % 14 OR2X2-8 OR2X2 2 8 rise % 15 AOI22X AOI22X fall % 16 OAI21X OAI21X rise % 17 NOR3X NOR3X fall % 18 AOI21X AOI21X rise % 19 INVX INVX fall % 20 OAI21X OAI21X rise % Path Delay % 38

39 Result: Cell Perturbation Original cell placement After cell perturbation Rising critical optimization with hole contour Falling critical optimization with electron contour

40 TSV Stress/Reliability & EM Issues Consider TSV stress during placement [ICCAD 10] Full-chip TSV stress modeling with multiple TSVs and physical layout optimization issues [Mitra+, ECTC 11] TSV EMI analysis [Pak+, ECTC 11] Due to vast difference is size differences A Current B C D E I H G F

41 Conclusion Some new research problems in nanolithography and design-technology co-optimization Pushing the lithography limits:» double patterning, triple/quadruple patterning» E-beam lithography (stencil planning, e-beam proximity effects)» EUV lithography (flare effects, etc.) Resilient design with built-in compensation and error correction (NBTI/PBTI, overlay effects, etc.) 3D-IC manufacturability and reliability issues Holistic treatment in a vertically integrated manner 41

42 Synergistic Design-Technology Co-opt Need good levers at different levels for designtechnology co-optimization (DTC) Give me a place to stand on, and I can move the earth. - Archimedes Lever DTC lever for your sub- 22nm billion transistor design!