Department of Electrical and Electronic Engineering Imperial College London

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1 Department of Electrical and Electronic Engineering mperial College London EE 2.3: Semiconductor Modelling in SPCE Course homepage: Paul D. Mitcheson Room, EEE EE2.3 Semiconductor Modelling in SPCE / PDM v.4

2 . Aims and Objectives.. Course Aims To show how SPCE solves circuit problems To explain the three main SPCE semiconductor models.2. Learning Objectives By the end of these lectures you should be able to: Understand the internal operation of 3 types of simulation in SPCE Know what the SPCE model parameters mean and how they relate to physical quantities Appreciate the issue of simulation convergence and how the semiconductor models used try to improve convergence Be able to use your own custom semiconductor models in SPCE (see study group sheet) 2. Syllabus SPCE internals and algorithms SPCE semiconductor models o Diode o BJT o MOSET 3. Problem Sheet An exercise done in SPCE in the labs which gets you used to the SPCE model parameters, and shows you some of the dynamic effects of devices that you have seen the theory for in the first part of the course. 4. Recommended Reading This part of the devices course is relatively self contained. f, however, you want to know more about SPCE, the following are good books: Semiconductor Device Modelling with SPCE, Giuseppe Massobrio and Paolo Antognetti, McGraw-Hill nc. nside SPCE, overcoming the obstacles of circuit simulation, Ron Kielkowski, McGraw-Hill nc. SPCE for circuits and electronics using PSpice, Muhammad H. Rashid, Prentice Hall EE2.3 Semiconductor Modelling in SPCE / PDM v.4 2

3 5. ntroduction You received an introduction to SPCE in the first year design project. Briefly, to remind you of the history and development of the software: SPCE (Simulation Program with ntegrated Circuit Emphasis) is a well-known circuit simulator computer program which began with a mainframe program written at UC Berkeley by Lawrence Nagel (and others) during his PhD. The SPCE solver or engine (the core part of the program i.e. the part that solves the circuit equations) is free software but it is command line driven and is thus regarded as difficult to use. Consequently, several commercial versions (mostly based on the 2G7 release of the Berkeley program [PSpice is based on 2G7]) are available which provide a graphical interface and up to date component libraries (models of commercially available semiconductor components provided by the semiconductor manufacturers). n this part of the course we will look briefly at the internal workings of SPCE, the semiconductor models that are used and how they relate to the device theory you have already studied. 6. How SPCE solves circuit bias points a first stage of the simulation process Why do we care how SPCE works internally? Because when things go wrong with a simulation, having some insight into the operation of the program helps you figure out how to make your simulation run and also allows you to use the program in a more efficient way. We will look in detail at how SPCE solves DC bias point simulations and then look briefly at some other types of simulation. We do it this way because the DC type calculations are fundamental to the operation of the other types of simulation and (with the exception of transient simulations) it is easy to extend the DC analysis that SPCE does to the other types of analysis. 6.. Overview for a simple resistive circuit SPCE firstly forms a set of nodal equations for a circuit is it trying to solve. These are formed from the netlist. Let s see with an example. Consider the following basic circuit: n n 3 R n n2 5 R2 n n2 R3 n2 n3 5 R4 n n3 igure Simple circuit with current source excitaiton irstly, SPCE forms a set of nodal equations based on KCL: EE2.3 Semiconductor Modelling in SPCE / PDM v.4 3

4 Which are rearranged and written in matrix form: Then, Gaussian elimination is used to form an upper triangular matrix which is solved using back substitution (first solve for 3, then 2, then ) You can see that this matrix is very easy to solve on computer, no matter how big it is. n essence, SPCE always tries to solve for nodal voltages which satisfy KCL by forming an equation of the form: [ G ] [ ] [ ] Note that the current matrix is known. or many equations, the entry in the current matrix will be zero as KCL requires currents into a node sum to zero), but it will be non-zero if an active device, such as a current source, is present. n other words, the matrix lists the current being actively injected into each node. Changing the current source for a voltage source makes it harder to solve(!) because it does not fit into our nice simple framework quite so easily. You might initially think that we could reformulate the expressions in the form of: [ R ] [ ] [ ] And then do Gaussian elimination to solve for the current matrix Consider the circuit below and the equivalent nodal equations igure 2 Simple circuit with voltage excitation EE2.3 Semiconductor Modelling in SPCE / PDM v.4 4

5 Unfortunately we cannot form the matrix equations the voltages at the nodes (other than n) are not known we do not know the [] matrix in its entirety and thus cannot perform Gaussian elimination. Therefore, we would like to analyse circuits with current sources instead of voltage sources because the [] matrix is always known, and we can therefore solve the circuit using Gaussian elimination. This is a special property about current excited circuits. Remarkable but true! So how do we cope with a voltage source in the circuit? After all, power supplies and batteries are voltage sources, not current sources! Use a Norton Equivalent circuit. Although it is not always clear how to do this as we will now see. t is clear that in the case of igure 2, the voltage source and current source could easily be converted into a Norton equivalent source. But how can you do it with the circuit branches as shown below? igure 3 Tricky to convert to a Norton source? igure 4 Not really! 6.2. Automatic Construction of the Matrix Equations The above is all very well, but how do we construct the matrices from the netlist? We did it in the example above by: Taking the netlist Drawing the circuit Using KCL to write the nodal equations Writing those equations in a matrix form [ G ] [ ] [ ] That algorithm is quite hard to program into a computer! There must be a better way. and indeed there is! EE2.3 Semiconductor Modelling in SPCE / PDM v.4 5

6 t s called matrix construction by inspection and lets us go directly from the netlist to the matrix equation. This construction is done by using predefined element matrix templates which can be added together automatically as we step through the netlist if the templates are designed properly. Each template consists of a conductance matrix of N by N, where N is the number of terminals on the device and an Nx voltage array and an Nx current array, in the usual form of [ G ] [ ] [ ]. This means that the template conductance matrix for a resistor is 2x2, a BJT is 3x3 and a MOSET (with separate body contact) is represented by a 4x4 conductance matrix. Let s take the example of a resistor: Node row Node row Node col GR GR Node col GR G R Current Array Conductance Array oltage Array And the example for a current source: Node col Node col Node row Node row Current Array Conductance Array oltage Array Let s see how SPCE constructs the equations for our earlier circuit of igure : n n 3 R n n2 5 R2 n n2 R3 n2 n3 5 R4 n n3 EE2.3 Semiconductor Modelling in SPCE / PDM v.4 6

7 rom the first line of the netlist, we have the current source definition: n n n n 3 3 On reading the second line of the netlist we add the definition of R: n n n2 n n.2.2 n Then on the third line we add R2: n n n2 n.. n.2.2 n On the fourth line add the R3 template: n n n2 n3 n.. n n2 n And finally add the last line and the R4 template: n n n2 n3 n.2.. n n2 n EE2.3 Semiconductor Modelling in SPCE / PDM v.4 7

8 As we define as ground, our final matrix equation to solve is: Note that we can add the matrices because as we add components into the circuit, any additional branch conductances appear in parallel with the existing elements and conductances in parallel G R form! add up. Another nice reason to use the [ ] [ ] [ ] instead of the [ ] [ ] [ ] But this equation by inspection is different from the one we derived using nodal analysis. s it valid? Use a Of course! Remove the first row and column (which you can do as the voltage was zero) and you have the same matrix as we started with. Now we know how SPCE solves any resistive circuit bias point with both voltage and current sources. What about simulations with capacitors and inductors? How are inductors and capacitors solved in a DC bias point simulation? Simple - Capacitors are set open circuit and inductors to short circuit. So, what about solving for non-linear elements, like a diode, or BJT? 6.3. Solving circuits with non-linear elements Let s look at a simple circuit with a diode present. What happens to the matrix equation that SPCE has to work with? Non-linear elements, such as diodes, cannot be solved using the simple Gaussian elimination technique alone because we run into a problem. Consider the following circuit with just unknown nodal voltage: sexp 2 v t EE2.3 Semiconductor Modelling in SPCE / PDM v.4 8

9 This single nodal KCL equation is a transcendental (meaning it is an equation involving terms other than simple polynomials which generally cannot be rearranged so that the variable becomes the subject of the equation) and thus the equation can only be solved numerically. f we tried to form this into our G* form and solve the normal way we would get: [.5][ ] 5 s exp t We do not need to make any Gaussian elimination operations to solve this because there is only node But it is still not clear how to solve it because it is transcendental. We can solve it using the Newton-Raphson algorithm, with which you should be familiar. Let s remind ourselves how this works. The Newton-Raphson algorithm is as follows: n+ n ( n ) ' ( ) n Where n+ is the voltage at the next iteration and n is the voltage at the current iteration. This does not mean the voltage at node n or node n+. or the simple circuit above, ( ) 5 s exp. 5 t Therefore we have: n 5 exp s.5 n t n + n n exp s.5 n t Which is easy to solve on computer using a simple loop Bringing it all together So, in slightly a larger circuit, let s see what happens: irstly, all voltage sources are replaced with current sources to give a circuit that looks something like the example below: igure 5 Solve using Gaussian Elimination and Newton-Raphson EE2.3 Semiconductor Modelling in SPCE / PDM v.4 9

10 The equations are: At node : At node 2: exp 5 s t Which can be formed into the following matrix equations (of course done in SPCE by inspection): s 3 2 exp t To solve these matrix equations, SPCE first uses Gaussian elimination to form the following matrices: s 3 2 exp t 3 Then, Newton-Raphson will be used to solve the transcendental equation for 2, before back substitution is used to find. Now we have some idea of how SPCE can solve circuits of any combination of linear and nonlinear elements with both voltage and current source excitation. You now know the basics of how SPCE solves operating point (static DC analysis) problems with R, L, C and non-linear elements. The topic of Newton-Raphson brings us nicely onto the next topic 7. Simulation Convergence and Convergence Aids Anyone who has used SPCE in simulating anything other than very basic circuits will probably be familiar with those times during which the simulator does not converge. f you have not seen a non-convergence of a simulation yet, don t worry, you will at some point! You may well have already encountered convergence problems in the first year design project. When SPCE fails to converge, the program stops with an error message about the voltages and currents that failed to converge. EE2.3 Semiconductor Modelling in SPCE / PDM v.4

11 Given the high frequency at which you can encounter convergence issues when simulating circuits in SPCE, it may surprise you to know that SPCE was designed with the convergence issue in mind as it is a known problem with iterative solution methods (i.e. Newton-Raphson) used in the internals of the program. 7.. Basic Convergence Parameters The iterative Newton-Raphson algorithm, if converging, produces more and more accurate estimates of a solution with each iteration. There is a trade-off here with the time taken to find a result and the accuracy of the result. n order to control this accuracy/time trade off, there are limits that must be set by the SPCE user for the accuracy of the simulations (or, as you have done up to now, you can simply accept the default values). The important parameters are: RELTOL ractional tolerance of voltages and currents NTOL Node voltage tolerance ABSTOL Current branch tolerance TL The number of iterations allowed for a bias point calculation So far, NTOL and RELTOL will make sense to you. We have seen SPCE always solves equations for the nodal voltages. RELTOL is the relative voltage (and current) tolerance for the node voltages, i.e. if the voltage at each node in the simulation changes by less than RELTOL percent of the absolute value from one iteration to the next, then the node voltages are said to have converged to the answer. This is fine unless the node voltages are very small. As the node voltages reduce, then RELTOL requires SPCE to converge to smaller and smaller absolute numbers. This is where NTOL comes in. NTOL is the absolute nodal voltage tolerance. f the node voltages change by less than NTOL from iteration to iteration, the simulation is also said to have converged. Thus, once the node voltages converge to within the limits of one of these parameters (whichever has the larger tolerance), the simulation might be in a position to stop. SPCE used only these two parameters to control the algorithm accuracy. However, non-linear devices (semiconductor devices!) can have very large changes in currents with only small changes in voltage. This means that even if the nodal voltages are converged to within tolerance, Kirchhoff s current law may not have converged (i.e. the sum of currents into a junction may not be close to zero). Thus, SPCE 2 (on which all modern SPCE based simulators are based) introduced some basic parameters for tolerances on currents. RELTOL was expanded to cover maximum fractional changes in branch currents between iterations (as well as nodal voltages) and ABSTOL was introduces. ABSTOL, which is absolute branch current tolerance, is the maximum allowed absolute change in branch currents from one iteration to the next. There is also a limit on the total number of allowed iterations. This is controlled by the TL parameter. Thus, the flow of the program is thus:. f number of iterations > TL, break 2. Do Newton-Raphson iteration to solve for nodal voltages 3. Check the solutions against NTOL and RELTOL 4. f solution not converged within parameters, goto 2, else goto Check branch currents (known from the nodal voltages) against ABSTOL and RELTOL 6. f not converged, goto else finish EE2.3 Semiconductor Modelling in SPCE / PDM v.4

12 7.2. Convergence Problems An example Again, we are going to concentrate on the convergence problems for simple DC bias point simulations (although this type of convergence problem could very well also appear in a transient simulation). Let s consider SPCE trying to solve the following simple circuit with a Newton-Raphson algorithm and see where we might run into trouble. We ll do Newton-Raphson graphically to see how the problems might arise. Newton-Raphson tries to find the intersection of the diode characteristic with the load line. Make sure you understand how the load line is drawn you are probably used to drawing them for voltage excited series circuits but this is a current excited parallel circuit. We first pick a starting point for the iterations. Let s choose somewhere around to start with. Graphically, the Newton-Raphson algorithm does the following: Take a tangent to the diode curve at the starting point (this tangent is of course a small signal linearised model of the diode!) and see where that crosses the load line This voltage is the starting point for the next iteration Repeat You can see how this iterates towards the solution in the diagrams below. igure 6 nitial guess igure 7 irst iteration igure 8 Second iteration EE2.3 Semiconductor Modelling in SPCE / PDM v.4 2

13 magine that the first guess had been at a lower voltage. Then the tangent at the second guess would be almost vertical and the algorithm can get stuck. We can see that we are always going to have a problem with the Newton-Raphson algorithm whenever we have a very high value of conductance on an element (in this case the diode) because the time taken for convergence of the algorithm may be large, or if the gradient is steep enough, the algorithm may not converge at all, with the next iteration voltage being the same as the last, and potentially no where near the actual solution 2, 3 There will also be a problem if the algorithm ends up in the part of the curve where the conductance of the diode is too small i.e. the slope of the graph is too shallow. We can see this because in the Newton-Raphson algorithm we will approach a divide by zero error as the derivative of the curve approaches zero. Graphically it means that the next guess at a node voltage will be very far from the actual answer- and back on a step part of the curve where we have long convergence times The GMN Convergence Parameter This brings us to another more advanced convergence parameter you might find useful when using SPCE. This is a parameter called GMN and is designed to stop divide by zero errors when simulating the exponentials of pn junctions, and to reduce the problem that an iteration may take the next voltage iteration far from the final solution. GMN is a pure conductance and one is placed in parallel with every pn junction implemented in SPCE. igure 9 pn junction with GMN convergence parameter This means that the slope of the exponential of the diode in reverse bias is at least equal to GMN. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 3

14 n addition, GMN is the minimum conductance allowed between any two neighbouring nodes in SPCE. f you set a resistance between two nodes with a conductance of less than GMN, the simulator will not run. Note that there may be certain circumstances where you have to reduce GMN the default value in SPCE is e-2. f the impedance of some components in your circuit are of this order of magnitude, although GMN will aid convergence, it will potentially ruin the accuracy of your simulations. Think before you simulate! Essentially, if you have both a parallel GMN with a pn junction, and a series resistance, simulating the resistance of the wires, the overall slope conductance is always kept within manageable levels so that the next iteration will neither be too far away from the previous guess (and possibly wildly inaccurate), or too close (long iteration times) Setting the convergence parameters Novice SPCE users would not necessarily think to change the default settings of the convergence parameters. However, it is often worth thinking whether the defaults make sense for the simulation you are doing. or low voltage low power work, they are almost always a good starting point (this is what SPCE was designed for). The default value of NTOL is μ. Do we really care about resolving voltages to μ when simulating a power supply? Probably not. So how do we set these convergence parameters? igure PSpice simulation options dialogue n PSpice Capture, go to Pspice Edit Simulation Profile Options tab We have looked in some detail at the operation of the DC bias point analysis. We will look briefly now at the other types of simulation that SPCE can do. 7.. DC sweep simulations The DC sweep simulation is an extension to the bias point simulation. n a DC sweep, the steady state solutions to a circuit are simulated for a range of DC voltages of a chosen voltage source in the circuit (which could be a power supply or an input to an amplifier etc). or the first voltage value to be simulated, SPCE solves the matrix equations in the normal way, doing iteration if non-linear elements are present. The outcome of this simulation is then used as the starting points for the nodal voltages for the first value in the DC sweep (if iterations were requires and thus a starting guess is required for the next DC step). The outcome of that simulation is then used for the starting point for the nodal voltages in the next value of the DC sweep etc. Problems can arise in convergence when a voltage changes particularly quickly. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 4

15 The DC sweep has a further convergence parameter associated with it TL2. This is the number of iterations that can be done at each step in the DC sweep, i.e. it provides the same function as TL in the DC bias analysis. 7.. AC Simulations So far, we have seen SPCE effectively solve linear and non-linear elements in DC simulations. Performing an AC simulation is not so different from a DC simulation. However, the AC SPCE simulation does not solve for non-linear elements it does not have to perform Newton-Raphson. When you do an AC simulation in SPCE to get a bode plot of a circuit s frequency response, the simulator makes linearised small-signal models of any non-linear devices. These are essentially the same models as you have seen in your analogue electronics courses and consist of (controlled) current and voltage sources and R, L and C. The component values are all constant during the simulation (which is necessary for the model to be linear of course) SPCE solves the nodal equations in almost exactly the same way as it would for a DC simulation only now the program cannot set inductances to short circuits and capacitors to open circuit. They simply become complex impedances. Consequently, at each given frequency, SPCE solves the matrix equations of the form [G][][], where the matrices now become complex. One anomaly with the AC simulation therefore, is that if you simulate something like a closed loop opamp circuit with a gain of and an AC input voltage of, the output will be shown as (if we are below the G*BW product) even through the power supplies to the opamp might only be 5. This is the problem with a linear model. f you want to really see the exact behaviour of a circuit, accurate at all voltages, then the best way to do it is with Large signal Transient Simulations These are the most complex type of simulation because they show the complete semiconductor models realistically at all operating points the full non-linear models are used (as in a DC bias point simulation and therefore Newton-Raphson is heavily used), but in contrast to the DC bias point simulations, capacitors and inductors cannot be set to open and short circuit respectively. SPCE therefore makes heavy use of numerical integration in these simulations. The exact detail of these simulations is however beyond the scope of this course for the time we have. So, what models does SPCE use internally for its semiconductor devices and how do they relate to the understanding you already have of semiconductor devices? We will look at the three most common devices, the p-n diode, the BJT and the MOSET. You have been shown small signal models of devices in other devices lectures and in your analogue courses. SPCE uses similar small signal device models when performing an AC analysis. n this part of the course, however, we will be looking at the large signal models used by SPCE in a transient (time domain) analysis and how they relate to the device physics you have already learnt. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 5

16 8. Types of Model used in SPCE There are three types of semiconductor model used in SPCE. One is the DC static model, one is the small signal AC model and one is the large signal transient model. We will look here at the DC models and transient models. The small signal models are essentially the same as you have seen in your analogue courses. The DC models are effectively the transient models with capacitors open circuited and inductances shorted. We will thus look at the models by starting with the DC model and then build them into the transient models with the addition of capacitances to take into account the dynamic effects. 9. The SPCE Diode Model 9.. DC Model You have already been shown the equations which describe the diode model, in both static and AC conditions. The simple DC equation you know is the well known Shockley equation, that is: D s exp t Where S is the diode s reverse saturation current, is the applied voltage bias, t is the thermal voltage (equal to kt/q which is about 25m at room temperature) and D is the current through the device. The simple DC model used in SPCE is very similar to the Shockley equation, with the addition of a parameter n, and a convergence aid of a the GMN parallel conductance (see igure ). The basic static diode model equation is thus: s exp n t D + D GMN D s exp nt igure The SPCE diode model has a parallel conductance to aid convergence The parameter n is an ideality factor for the diode, known as the emission coefficient. t has a SPCE parameter called N (all SPCE parameters are given in capitals). So far we have assumed n EE2.3 Semiconductor Modelling in SPCE / PDM v.4 6

17 to be, and indeed, in a good diode it will almost be. This parameter will rise above if there is significant recombination of carriers in the depletion layer. Therefore, n tends to be closer to under high forward bias and more than under small bias voltages because the depletion layer gets thinner as the forward bias is increased. The other SPCE parameter from this basic equation is S. n order to allow faster simulations than this equation would provide, a simple approximation is made in moderate reverse bias. When D <-5n t, SPCE uses the assumption that the leakage current through the p-n junction is simply equal to S, rather than calculating the exact exponential term. This means that the total current through the complete static SPCE diode model is: D s + D GMN What is a physical meaning of S? t is the limit of the current in the diode under high reverse bias. f the diode did not exhibit breakdown, the maximum reverse current that you could get through the diode with an infinite reverse bias would be s. You can now appreciate why the GMN component is vital in achieving convergence in the region of D <-5n t, because the conductance would otherwise be zero in that region. So far we have a model that reproduces the simple diode characteristic but does not include zener breakdown. However, SPCE does include breakdown in the model, and is modelled as an exponential breakdown past a certain voltage, the breakdown voltage, specified as SPCE parameter B, with current at breakdown of B. The current after breakdown is modelled with the following equation: B + D B D S exp + t t You can see that when the diode voltage is equal to B, the diode current as specified by this equation is - s B/ t. t is therefore important that the SPCE parameter B is somewhat near to - s B/ t to allow continuity in the DC characteristic. n summery, the static characteristic curve, simulated by SPCE is shown below: EE2.3 Semiconductor Modelling in SPCE / PDM v.4 7

18 igure 2 SPCE model DC diode characteristic split into 3 regions inally, a series resistance is added to the diode model to simulate the resistances of the connecting wires and the ohmic contact resistances, giving us the following simple static model: And so, D ' D + D RS igure 3 Static DC diode model n summary, the important SPCE parameters (given in capitals and corresponding to the physical parameters in italics) for setting the DC characteristic are: S ( s ) RS (R s ) N (n) B B The reverse saturation current The Ohmic resistance of the contacts and bond wires The emission (or ideality) coefficient The breakdown voltage (inputted to SPCE as a positive number) The current at reverse breakdown (inputted to SPCE as a positive number) With these parameters you can specify the complete static diode characteristic. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 8

19 9... Limitation of the Diode Model The SPCE diode model does not include the effects of high level injection. When deriving the Shockley equation you previously made the assumption (although you probably did not realise it) that the number of minority carriers was much less than the number of majority carriers (this is low level injection). n power semiconductors, this is not necessarily the case because they operate in what is known as high level injection. The SPCE model does not include this effect (because it was originally designed to be used with low power signal devices). do not expect you to understand how the physics changes in the device with low and high level injection just want you to be aware of this limitation. f you take the power electronics course in 3 rd year you will look briefly at these effects Large Signal Transient Model We now need to add dynamic effects to the diode model. This is fundamentally done by adding in capacitances to the model, as shown in igure 4. D C GMN D RS igure 4 SPCE Large signal transient model We know the equations used for the current source (the Shockley equation with the addition of the non-ideality factor) and we understand the physical meaning of the series resistance RS and the reason for the GMN resistor (that of Newton-Raphson algorithm convergence). The question we now face is What equation does SPCE use to calculate the parallel capacitance and how does it relate to the physics? You know that there are two contributions to capacitance between the terminals of a diode. These are the diffusion capacitance and the depletion (or junction) capacitance. The depletion (junction) capacitance, dominant in reverse bias, is given by the following equation, which you have seen the derivation of earlier in the course: C j ε A en AN D 2ε ( N + N )( ) A D SPCE implements essentially the same equation, written slightly differently: EE2.3 Semiconductor Modelling in SPCE / PDM v.4 9

20 C j A εen 2( N A A N D + N ) D Which can be written as: C j C j () This is the equation SPCE uses to calculate the depletion capacitance, where C j (o) is the junction capacitance at zero applied bias. The diffusion capacitance, C d, is dominant in forward bias. This is the capacitance associated with the stored minority carriers injected into the neutral regions. You have seen an equation for the diffusion capacitance written as: e C d τ kt SPCE uses the same equation, but adds in the diode ideality coefficient: C d e nkt τ Consequently you can see the additional parameters (over and above the DC parameters) needed to specify the dynamic behaviour of a diode in SPCE: CJ (C j ()) TT (τ) J ( ) Zero bias junction capacitance The transit time Built in junction voltage You now know the most important parameters to allow you to specify a custom diode model in SPCE. There are a few more parameters which exist that we are not going to look at as we have covered the important ones A Note on the SPCE Area Parameter A and Device Scaling SPCE has an area parameter called A, which can be used to scale any pn junction. The parameters S, CJ, RS and B are all proportional to device area. You therefore have two choices when entering these parameters: Enter them as parameters per unit cross sectional area and set the A parameter to the correct cross sectional area of the device Enter them as the values for a specific device and set the Area value to. Then if you want to have multiple devices in parallel, setting A3 means your device will behave as if there were three devices in parallel. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 2

21 . The SPCE BJT model.. DC model This section of the notes is based on an npn transistor. have chosen to use this as believe most of you are more at home with it at the circuit level than the pnp transistor and here we are on the boundary of device physics and circuits so being able to relate the device physics with circuits is important.... Ebers-Moll injection model The model of the BJT used in SPCE is based around a set of equations known as the Ebers-Moll equations. One of the reasons that SPCE uses these equations is because, as you will see, the Ebers-Moll model is based on current sources and diodes, which are models we now already have in SPCE. We simply use them to build a sub-circuit of a bipolar transistor without needing to introduce any new components or equations into SPCE. There are actually 2 versions of the Ebers-Moll model, the injection model and the transport model. SPCE uses the transport model, however, we will start by looking at the injection model because it is easier to relate to the device physics. We will then modify it into the transport model so that we can relate the device physics to the SPCE parameters. You are aware that a BJT is physically built as two back to back diodes, as shown below: B E C B E C igure 5 The npn transistor as two diodes MPORTANT: it does not really behave like this but this description is important to understanding the SPCE model! You also know it DOES NOT BEHAE like two discrete back to back diodes connected together two back to back diodes would not allow conduction between emitter and collector because one of them would always be in the blocking state. Transistor action (the effect of being able to control the current through one p-n junction by altering the bias across another nearby junction) only occurs because the two p-n junctions are physically very close together and have shared energy levels, so that carriers emitted from the emitter can be collected by the collector without flowing out of the base contact. n short, these two p-n junctions are not discrete they interact. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 2

22 The BJT in Active Mode Before we look specifically at the Ebers-Moll model we should refresh our memory of the carrier flows in an npn BJT. You have previously seen a diagram something like that shown in igure 6. n+ p n Electron current Normal injection at b-e junction Recombination in base Collection of electrons by collector Reverse leakage of holes Hole current e b c igure 6 Electron and hole current in an npn BJT in the forward active region n the forward active region, the base emitter junction is forward biased. The heavily doped emitter injects many electrons into the base region. Some of these escape out of the base contact (which is normal p-n diode behaviour if we consider the base-emitter junction to be a diode), some recombine with holes in the p-type base and the rest make it to the collector. Electrons are collected by the collector because they are attracted by the electric field in the depletion region of the base-collector junction. (The part of the depletion layer in the collector has ionised donor atoms which are positively charged and thus attract the negatively charged electrons). The electron concentrations along the length of the device are look as below: n+ p n n pe n pc e b c igure 7 Electron carrier concentration in forward active region of operation EE2.3 Semiconductor Modelling in SPCE / PDM v.4 22

23 The collector current is proportional to the minority carrier concentration gradient in the base. n active mode, n pc is approximately zero because the collector-base junction is reverse biased. Hence, the emitter current is controlled completely by the base emitter voltage (when the device is operating in the active mode) as this alters the concentration gradient by altering n pe. We can think of the BJT operating in this way as the following large signal equivalent circuit. igure 8 Equivalent circuit of npn BJT operating in active mode: derived from device physics Where: Nbe electron current through the base emitter junction Pbe hole current through the base emitter junction the total current through the base-emitter junction ( Nbe + Pbe ) B fraction of electrons injected by the emitter which are collected by the collector You should be able to see that this is an equivalent circuit of the device physics. There is: Current through the base-emitter junction, which is made of electron and hole current (mainly electron current in this npn device) A proportion (B ) of the electrons emitted from the emitter are collected by the collector We neglect any contribution that flow of holes from the reverse biased collector-base junction have to collector current You can thus see that the base current makes up (-B ) part of the collector current, plus the contribution of holes to the base emitter current ( Pbe ). Using the normal definition of the forward current transfer ratio, α, α c e We know we can simplify the diagram: igure 9 Transistor equivalent circuit - forward active region EE2.3 Semiconductor Modelling in SPCE / PDM v.4 23

24 And thus: α B Nbe Which we need to remember for construction of the final model, in a few moments. The BJT in saturation Now let s look at what happens to the device saturation. n saturation, both junctions are forward biased. f we look at the concentration of electrons in the device, we have: igure 2 BJT electron concentration in saturation f we now look at a diagram of the carrier flows again, we have: igure 2 BJT carrier flows in saturation both junctions are forward biased The main points to note here are: The injected electron current from the emitter is significantly less than in the active mode because the concentration gradient of electrons in the base is reduced because n pc has increased. Both junctions are forward biased, meaning there is significantly increased base current due to forward hole injection across the base-collector junction. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 24

25 Let s look at the electron current for a moment. We can think of this as being made of a forward and a reverse flow of electrons, due to the principle of linear superposition: igure 22 Carrier concentration in saturation region in base split into two components The line marked on the diagram shows the net concentration gradient of electrons in the base and hence electron current is proportional to this gradient Line 2 shows the electron concentration gradient that would be achieved if the emitter-base junction was isolated from the collector with the given base-emitter voltage Line 3 shows the electron concentration gradient that would be achieved if the collectorbase junction was isolated from the emitter with the given collector-base voltage The total current, t, is proportional to the net gradient, i.e.: t n K pe 'n L b pc ' Where K is just a constant of proportionality and L b is the length of the base The forward current is: f n pe ' K L b The reverse current is: r n pc ' K L b Thus t f r n K pe 'n L b pc ' Which we can see is the net current from the concentration gradient. We can therefore think of the electron current as being the sum of the current injected from the emitter and that current injected from the collector, as shown in igure 23, if the carrier concentration at the collector and emitter respectively, are zero. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 25

26 n+ p n Collection of electrons by emitter Electron current Normal injection at b-e junction Recombination in base Collection of electrons by collector Hole current Normal injection at b-c junction e b c igure 23 BJT operation in saturation mode - thinking of the electron current as two separate currents - one injected from the emitter and one from the collector This shows us we can think of the transistor, in the saturation region, as two back to back diodes, where a proportion of the injected emitter (collector) current makes it to the collector (emitter). The part that doesn t make it all the way across the base region is either involved in recombination or flows out of the base. The base current supplies the recombination current and, in the case of the npn transistor, supplies two small hole currents to feed the two forward biased junctions. The Ebers Moll model makes use of the fact that the two separate p-n junctions exist, but adds an additional two current sources to allow for the interaction between them, so that the transistor action can be described. igure 8 and igure 9 showed only part of this story the device operating in saturation. The Ebers-Moll model effectively models a forward and a reverse BJT, each operating in active mode, to produce a complete BJT model that can also work in the saturation region. rom igure 23, we should now be able to see the physical mechanisms that lead us to the complete Ebers-Moll model equivalent circuit shown below, for an n-p-n transistor: igure 24 Ebers-Moll model of BJT (injection version) EE2.3 Semiconductor Modelling in SPCE / PDM v.4 26

27 forward transistor current (through the base emitter junction) R reverse transistor current (through the base collector junction) Nbc electron current through the base collector junction Pbc hole current through the base collector junction Nbe electron current through the base emitter junction Pbe hole current through the base emitter junction B fraction of electrons injected by the emitter which are collected by the collector B R fraction of electrons injected by the collector which are collected by the emitter n summary: The diodes in igure 24 represent the two p-n junctions of the BJT and the currents through them represent the current that would flow through them if each junction was discrete (i.e. if it was a simple diode) with the voltages BE and BC across them. They refer therefore to the current marked normal injection in igure 23. Note that is mainly electron current because of the heavy doping of the emitter. The current sources in igure 24 represent the interaction between the junctions i.e. some (most in a good BJT!) of the electron current which is injected into the base from the emitter passes through the base into the collector. The current sources correspond to the carrier flows marked collection of electrons by collector/emitter in igure 23. We had already showed that: α B Nbe And therefore we can also write: α B R R R Nbc This gives us the final well known Ebers-Moll injection model: B B R E E C C R R igure 25 Ebers-Moll BJT model - injection version EE2.3 Semiconductor Modelling in SPCE / PDM v.4 27

28 The currents flowing in these diodes are given by: exp t BE ES n exp t BC CS R n And thus the currents in the BJT terminals are given by the Ebers-Moll equations: exp exp t BC CS t BE ES R C n n α α exp exp t BE ES t BC CS R R R E n n α α ) ( ) ( R R C E B α α + You can see from the above equations that four parameters are needed to specify the Ebers-Moll model. These are: ES, CS, α R and α. However, it can be shown that α ES α R CS (See the original paper by Ebers and Moll Large- Signal behaviour of junction transistors ), and this is written as the parameter you know already know for a BJT s. S CS R ES α α This makes sense the equation you know for the behaviour of the BJT in the active mode is: exp t be s c n active mode, we assume the current contribution from the reverse biased base-collector junction is minimal and so: exp exp t be S t be ES c α α EE2.3 Semiconductor Modelling in SPCE / PDM v.4 28

29 When you think about it, the emitter current is just the diode equation for the base-emitter junction. The collector current is just a proportion, α of this. Hence s for the BJT is just the SE (saturation current of the base-emitter junction) multiplied by the proportion of this current that is collected at the collector. Apart from the fact that SPCE can use the existing diode models and existing current source models to make a BJT with the Ebers-Moll model, what is so great about the Ebers-Moll model for computer simulation? t works under all operating conditions active, saturation etc. SPCE does not need to implement different equations for different regions of operation...2. Ebers-Moll Transport Model used in SPCE So far we have looked at the Ebers-Moll injection model and we said SPCE actually uses the transport model. To make things slightly more complex, SPCE does not use the standard Ebers- Moll transport model, but actually a modified transport model. We will look at the modified model (we need it to see how the SPCE parameters relate to the physics) but we will look at the standard transport model as a way through to understanding the modified model. igure 26 Ebers-Moll model - transport version n this model, the equations for the currents in the current sources are given by: CC EC BE S exp nt BC S exp nt Where s is the saturation current of each diode ( ES and CS ) multiplied by the gain, α and α R, as we defined before. All we have done here is introduced a change in notation the transport model is exactly the same as the injection model in terms of meaning and operation but is less easy to relate to the device physics. Unfortunately this is still not the final BJT model used by SPCE. There is one modification left to make before we can see the final model and how the parameters relate to the physics. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 29

30 SPCE uses a model with only a single current source, as shown below: igure 27 Modified Ebers-Moll transport model used in SPCE Note that the definitions of the diode currents are now different. This is in order to keep the terminal currents the same as the previous (two current source) model. n this model: β β R α α α R α R CT CC EC You can prove that the terminal currents in the double and single current source models are identical hence the models give the same result they are just a little different internally. You can now see how the BJT parameters in SPCE are essentially two sets of diode parameters which we have seen previously, plus the factors B (β ) and BR (β R ), which accounts for the interaction between the junctions. So what are physical meanings of β and β R? β is the current gain ( C / B ) of the device when it is operating with the emitter as the emitter and the collector as the collector in the active mode β R is the current gain of the device when it is operating with the emitter as a collector and the collector as an emitter in the reverse active mode EE2.3 Semiconductor Modelling in SPCE / PDM v.4 3

31 Note that as the device is made to have higher forward current gain (the terminals for emitter and collector are not completely interchangeable due to different dopings of the collector and emitter) than reverse current gain. inally, SPCE includes the effects of the contact resistances, and the convergence aid conductance, GMN, is also present. So, the final large signal DC SPCE BJT model is given by: B B r b CC / EC / R E E r e r c C C GMN GMN CT igure 28 Large signal DC BJT model S ( s ) RE (r e ) RB (r b ) RC (r c ) N (n) NR (n) B (β ) BR (β R ) The transistor saturation current The Ohmic resistance of the contact and bond wire at the emitter The Ohmic resistance of the contact and bond wire at the base The Ohmic resistance of the contact and bond wire at the collector The emission (or ideality) coefficient for the base-emitter junction The emission (or ideality) coefficient for the base-collector junction The forward current gain The reverse current gain Note that the BJT diode equations do not model breakdown, hence there are no B and B parameters for the BJT model..2. Large Signal Transient Model The transient model is built from the DC model in the same way that the diode model was built. We can therefore see very quickly what the parameters are for this model and how they relate to the physics. There are two junction capacitances, and essentially there are the same parameters used to specify these capacitances as there was in the diode. The only difference is we now have two times as many parameters one of each for each of the two capacitors. The parameters are: CJE CJC JE JC T TR Zero bias base-emitter junction capacitance Zero bias base-collector junction capacitance Base-emitter junction built in voltage Base-collector junction built in voltage orward transit time Reverse transit time EE2.3 Semiconductor Modelling in SPCE / PDM v.4 3

32 The forward transit time T is the transit time associated with the base-emitter junction and the reverse transit time TR is the transit time associated with the base-collector junction. igure 29 SPCE Large Signal Transient BJT Model There is also an area scaling parameter A for the BJT, which works in exactly the same way as for the diode. EE2.3 Semiconductor Modelling in SPCE / PDM v.4 32

33 . The SPCE MOSET Models.. DC Model Whilst there is essentially only diode model used in SPCE and BJT model, to complicate matters there are several MOSET models in common use. The reason for this is that MOSETS are very much the device of choice in modern circuit design, be it analogue or digital and consequently models have been developed which have got more accurate with time, and which model new occurrences in the device physics when as the device manufacturing allows devices to be made smaller. t is interesting to note that nowadays MOSET is a rather outdated name for the device. The gate is no longer made of metal, normally being made of poly Silicon. Thus, you may occasionally see the MOSET referred to as an GET nsulated gate ET. The original set of SPCE MOSET models are known as the level, level 2 and level 3 models. These are the models used in the simulator PSpice, with which you are familiar. There are some other, much more complex (although of course more accurate) used by more specialist analogue design tools such as the Cadence design suite. One of the most important models used in Cadence is the BSM (Berkeley Short Channel GET model) model. However, this model is way beyond the scope of this course because it has over parameters in the DC model alone! (But it is good you are now aware of its existence.) The basic SPCE level static model (as proposed by Shichman and Hodges) is as follows: igure 3 MOSET characteristic You have seen the proof of the MOSET equation in your st year lectures: μ C DS ox W L eff 2 DS ( GS TH ) DS 2 When the channel becomes pinched off, DS saturates and barely rises further. At pinch-off DS GS - TH and so the current in saturation is given by setting DS GS - TH in the equation above, to give: EE2.3 Semiconductor Modelling in SPCE / PDM v.4 33