ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
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1 ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
2 SEQUENTIAL CIRCUITS: LATCHES
3 Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine when to store values. A clock signal can determine storage times Clock signals are periodic Single bit storage element is a flip flop A basic type of flip flop is a latch Latches are made from logic gates NAND, NOR, AND, OR, Inverter
4 The story so far... Logical operations which respond to combinations of inputs to produce an output. Call these combinational logic circuits. Usually these circuits do not contain loops However, some combinational circuits have loops:
5 The story so far... Combinational circuits No way of remembering or storing information after inputs have been removed. To handle this, we need sequential logic capable of storing intermediate (and final) results.
6 Sequential Circuits Inputs Combinational circuit Next state Flip Flops Outputs Present state Timing signal (clock) Clock a periodic external event (input) synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems
7 Cross-coupled Inverters The system has two stable states A stable value can be stored at inverter outputs Not possible to set a desired state State 1 State 2
8 Cross-coupled Inverters (cont.) This circuit has no stable states
9 SR Latch
10 S-R Latch with NORs R (reset) Q S R Q Q S (set) Q Forbidden 1 0 Set 0 1 Reset Stable S-R latch made from cross-coupled NORs If Q = 1, set state set S If Q = 0, reset state Usually S=0 and R=0 reset R S=1 and R=1 generates unpredictable results Q Q
11 S-R Latch with NORs R (reset) Q S R Q Q S (set) Q Forbidden 1 0 Set 0 1 Reset Stable
12 S-R Latch with NORs R (reset) Q S R Q Q S (set) Q Forbidden 1 0 Set 0 1 Reset Stable What happens if both inputs R and S simultaneously change from 1 to 0? Race conditions
13 S-R Latch with NANDs S R Q Qʼ S R Q Q Forbidden 1 0 Set 0 1 Reset Store Latch made from cross-coupled NANDs Sometimes called S -R latch Usually S=1 and R=1 S=0 and R=0 generates unpredictable results
14 S-R Latches
15 NOR S-R Latch with Control Input Only stores data if C = 0 R Q C S Q Input sampling enabled by gates
16 S-R Latch with control input Occasionally, desirable to avoid latch changes C = 0 disables all latch state changes Control signal enables data change when C = 1 Right side of circuit same as ordinary S-R latch.
17 D-Latch
18 D Latch Q 0 indicates the previous state (the previously stored value) X D S Q C Y R Qʼ D C Q Q X 0 Q 0 Q 0 X Y C Q Q Q 0 Q 0 Store Reset Set Disallowed X X 0 Q 0 Q 0 Store
19 D Latch D C X S Q Qʼ Y R D C Q Q X 0 Q 0 Q 0 Input value D is passed to output Q when C is high Input value D is ignored when C is low
20 D Latch x D Q z Latches on following edge of clock E Clk E Z only changes when E is high If E is high, Z will follow X x z
21 D Latch Latches on following edge of clock E x D Q z x E C z The D latch stores data indefinitely, regardless of input D values, if C = 0 Forms basic storage element in computers
22 Symbols for Latches SR latch is based on NOR gates S R latch based on NAND gates D latch can be based on either. D latch sometimes called transparent latch
23 Summary Latches are based on combinational gates (e.g. NAND, NOR) Latches store data even after data input has been removed S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) With additional gates, an S-R latch can be converted to a D latch (D stands for data) D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q
24 Flip-Flops
25 Disadvantage of Transparent Latches
26 Clocking Event What if the output only changed on a C transition? Negative edge triggered C The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. D Q Qʼ D C Q Q X 0 Q 0 Q 0
27 Master-Slave D Flip Flop Consider two latches combined together Only one C value active at a time Output changes on falling edge of the clock D C Q Q X 0 Q 0 Q 0
28 Positive and Negative Edge D Flip-Flop D flops can be triggered on positive or negative edge Bubble before Clock (C) input indicates negative edge trigger
29 Clocked D Flip-Flop Stores a value on the positive edge of C Input changes at other times have no effect on output
30 JK Flip-Flop
31 Positive Edge-Triggered J-K Flip-Flop Created from D flop D = JQ +K Q J sets K resets J=K=1 invert output J K CLK Q Qʼ 0 0 Q 0 Q TOGGLE
32 Clocked J-K Flip Flop Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output Characteristic Table
33 T Flip-Flop
34 Positive Edge-Triggered T Flip-Flop Created from D flop T=0 -> keep current K resets T=1 -> invert current T C Q Qʼ 0 Q 0 Q 0 1 TOGGLE
35 Asynchronous Inputs
36 Asynchronous Inputs J, K are synchronous inputs o Effects on the output are synchronized with the CLK input. Asynchronous inputs operate independently of the synchronous inputs and clock o Set the FF to 1/0 states at any time.
37 Asynchronous Inputs
38 Asynchronous Inputs Note reset signal (R) for D flip flop If R = 0, the output Q is cleared This event can occur at any time, regardless of the value of the CLK
39 Summary Flip flops are powerful storage elements They can be constructed from gates and latches! D flip flop is simplest and most widely used Asynchronous inputs allow for clearing and presetting the flip flop output Multiple flops allow for data storage The basis of computer memory! Combine storage and logic to make a computation circuit Next time: Analyzing sequential circuits.
40 ANALYSIS OF SEQUENTIAL CIRCUITS
41 Overview Understanding flip flop state: Stored values inside flip flops Clocked sequential circuits: Contain flip flops Representations of state: State equations State table State diagram Finite state machines Mealy machine Moore machine
42 Flip Flop State Behavior of clocked sequential circuit can be determined from inputs, outputs and FF state x D 0 Q 1 Q 0 D 1 D D Q Q Q Q Q 0 Q 1 y Clk y(t) = x(t)q 1 (t)q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t)
43 Output and State Equations Next state dependent on previous state. x D 0 Q 1 Q 0 D 1 D D Q Q Q Q Q 0 Q 1 y Output equation State equations Clk y(t) = x(t)q 1 (t)q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t)
44 State Table Sequence of outputs, inputs, and flip flop states enumerated in state table Present state indicates current value of flip flops Next state indicates state after next rising clock edge Output is output value on current clock edge State Table Present State Next State x=0 x=1 Output x=0 x= Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1)
45 State Table All possible input combinations enumerated All possible state combinations enumerated Separate columns for each output value. Sometimes easier to designate a symbol for each state. Let: s 0 = 00 s 1 = 01 s 2 = 10 s 3 = 11 Present State s 0 s 1 s 2 s 3 Next State x=0 x=1 Output x=0 x=1 s 0 s s 2 s s 0 s s 2 s 3 0 1
46 State Diagram Circles indicate current state Arrows point to next state For x/y, x is input and y is output 0/0 00 0/0 1/0 Present State Next State x=0 x=1 0/0 1/ /0 0/0 Output x=0 x= /1
47 State Diagram Each state has two arrows leaving One for x = 0 and one for x = 1 Unlimited arrows can enter a state Note use of state names in this example Easier to identify 0/0 0/0 0/0 1/0 s 0 s 1 s 2 1/0 1/0 0/0 s 3 1/1
48 Flip Flop Input Equations Boolean expressions which indicate the input to the flip flops. x D 0 Q 1 Q 0 D 1 D D Q Q Q Q Q 0 Q 1 y Clk D Q0 = xq 1 D Q1 = x + Q 0 Format implies type of flop used
49 Analysis with D Flip-Flops Identify flip flop input equations Identify output equation Note: this example has no output
50 Mealy Machine Output based on state and present input X(t) present input Comb. Logic Q(t+1) next state Flip Flops Q(t) present state Comb. Logic Y(t) clk
51 Moore Machine Output based on state only X(t) present input Comb. Logic Q(t+1) next state Flip Flops Q(t) present state Comb. Logic Y(t) clk
52 Mealy versus Moore
53 State Diagram with One Input & One Mealy Output State transitions are shown as a function of inputs and current outputs. e.g. 1 1/1 0/0 S1 1/0 Input(s)/Output(s) shown in transition 0/0 S4 1/0 0/0 S3 1/0 S2 0/0
54 State Diagram with One Input & a Moore Output Moore machine: outputs only depend on the current state Outputs cannot change during a clock pulse if the input variables change Moore Machines usually have more states. No direct path from inputs to outputs Can be more reliable
55 Summary Flip flops contain state information State can be represented in several forms: State equations State table State diagram Possible to convert between these forms Circuits with state can take on a finite set of values Finite state machine Two types of machines Mealy machine Moore machine
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