Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Transcription

1 Solid-State Electronics 47 (23) Strained Si CMOS (SS CMOS) technology: opportunities and challenges K. Rim a, *, R. Anderson b, D. Boyd b, F. Cardone a, K. Chan a, H. Chen b, S. Christansen a, J. Chu a, K. Jenkins a, T. Kanarsky b, S. Koester a, B.H. Lee b, K. Lee a, V. Mazzeo b, A. Mocuta b, D. Mocuta b, P.M. Mooney a, P. Oldiges b, J. Ott a, P. Ronsheim b, R. Roy a, A. Steegen b, M. Yang a, H. Zhu b, M. Ieong b, H.-S.P. Wong a a IBM T.J. Watson Research Center, Yorktown Heights, NY 1598, USA b IBM Microelectronics SRDC, Hopewell Junction, NY 12533, USA Abstract Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern dayõs CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted. Ó 23 Elsevier Science Ltd. All rights reserved. 1. Introduction Strained Si (SS) MOSFETs are device structures that take advantage of strain-induced enhancement of carrier transport in silicon. Fig. 1(a) illustrates the structure of strained Si MOSFETs. When a thin layer of Si is pseudomorphically grown on a thick, relaxed SiGe layer (Fig. 1(b)), the lattice constant of the Si film conforms to that of the SiGe layer, and the lattice mismatch between Si and SiGe leads to biaxial tensile strain in the Si layer. If the SiGe layer is fully relaxed and the Si layer fully strained, the amount of strain in Si is approximately 4:2 x% where x is the Ge mole fraction in the SiGe layer. A Si surface channel is formed in a SS MOSFET at the oxide/si interface. This is in contrast to a buried channel structure in a SiGe/Si/SiGe FET [1,2], or a SiGe surface channel in a SiGe MOSFET [3] with gate oxide * Corresponding author. Tel.: ; fax: address: rim@us.ibm.com (K. Rim). formed on SiGe. Compared to the alternatives, strained Si surface channel MOSFETs have the following advantages: a single epi layer can potentially enhance both electron and hole mobilities, the surface channel architecture leads to better scaling behavior in deep submicron channel lengths, and advanced gate oxides can be thermally grown on pure Si as opposed to SiGe. Obtaining high quality oxide interface is difficult in thermal oxidation of SiGe. Theoretical calculations [4 8] predict electron and hole mobility enhancements in strained Si. In the conduction band (Fig. 2(a)), tensile strain splits the sixfold degeneracy, and lowers the two-fold degenerate perpendicular D-valleys with respect to the four-fold inplane D-valleys in energy space. Such energy splitting suppresses inter-valley carrier scattering between the two-fold and four-fold degenerate valleys, and causes preferential occupation of the two-fold valleys where the in-plane conduction mass is lower. These two effects lead to increased electron mobility. Similarly, strain splits the valence band degeneracy (Fig. 2(b)) at the C-point and shifts the spin orbit band [9], improving the in-plane hole mobility /3/$ - see front matter Ó 23 Elsevier Science Ltd. All rights reserved. doi:1.116/s38-111(3)41-8

2 1134 K. Rim et al. / Solid-State Electronics 47 (23) Fig. 1. Typical structures of strained Si/relaxed SiGe bulk MOSFETs. Fig. 2. Biaxial tension-induced changes in (a) conduction and (b) valence bands in strained Si. Various experiments reported during the past eight years have demonstrated electron and hole mobility enhancements in SS MOSFETs [1 18]. In this paper some of the recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted. 2. Device performance enhancements To investigate the feasibility of manufacturable integration, strained Si MOSFETs were fabricated with a.13 lm CMOS technology [16] complete with shallow trench isolation and salicide. The fabrication process was modified to accommodate the material compatibility with SiGe and strained Si. Fig. 3 shows the TEM micrograph of a SS device after fabrication. The quality of epi layer and gate oxide interface can be maintained during the device fabrication steps. Fig. 3. TEM micrograph of a fabricated strained Si MOSFET. Fig. 4 shows the NFET mobility measured on large area, long channel devices. The mobility of the SS device is 7% higher than the universal MOSFET mobility [19] or the mobility of the control device. What is remarkable is that the electron mobility enhancement persists even at high effective fields where the so-called surface roughness scattering was expected to dominate the mobility. The observed enhancement at high vertical field suggests that the strain may influence the surface roughness scattering in addition to the phonon scattering. Fig. 5 illustrates this point with a simple curve-fitting analysis. Fig. 5(a) shows the result of curve fitting assuming that only the phonon scattering-limited mobility is enhanced by strain. Such assumption underpredicts the mobility of the strained Si MOSFET at high vertical fields. Enhancements of both phonon scattering mobility and surface roughness scattering mobility are required (Fig. 5(b)) to describe the observed mobility characteristics of the SS device. Drain current characteristics of the short channel devices (L eff ¼ 67 nm) are compared in Fig. 6. Both control and SS devices were fabricated using the same Effective Mobility, eff (cm 2 /V*s) Universal Mobility Strained Si on SiGe 2% Unstrained Si control Strained Si on SiGe 15%. 5.k 1.M 1.5M Vertical Effective Field, E eff (V/cm) Fig. 4. Effective electron mobility of strained Si MOSFETs [16].

3 K. Rim et al. / Solid-State Electronics 47 (23) lower gate overdrive. Fig. 7 compares current drive at various L eff. Current drive enhancement is observed at L eff as small as 5 nm. Fig. 8 summarizes some of the SS PFET mobility data reported in the recent literature, and compares them to the results in this work. Unlike electron mobility which 7.x1-4 I g -V T =.9 V (A/um) 6.x1-4 5.x1-4 Control Strained Si 4.x L eff,cap (nm) Fig. 7. Current drive vs. L eff of strained Si NFETs. Fig. 5. Mobility enhancements in strained Si NMOSFETs. Curve fitting (a) with only phonon mobility enhanced and (b) with both phonon and surface roughness mobility enhanced. implant and activation annealing condition in this preliminary experiment. Note that due to the changes in the band structure and difference in dopant diffusion properties in SiGe, the SS devices exhibited lower V T and larger overlap capacitance C ov [16] (and thus longer physical gate length for a given L eff ). At gate overdrive (V GS V T ) of 1. V, the current drive of strained Si device is 2 25% larger, and the enhancement is larger at Effective Hole Mobility (cm 2 /V*s) k 4.k 6.k 8.k 1.M Effective Field (V/cm) Universal Mobility control (Rim, IEDM 95) 2% [Ge] (Rim, IEDM 95) 3%[Ge](RimIEDM95) 2% [Ge] (Huang VLSI 1) 25% [Ge] (Huang VLSI 1) control (Mizuno IEDM ) 18% [Ge] (Mizuno IEDM ) Control (this work) 3% [Ge] (this work) Fig. 8. Effective hole mobility of strained Si MOSFETs. Normalized Drain Current (A/µm) 6.x1-4 4.x1-4 2.x1-4 Normalized Drain Current (A/ m) 6.x1 4.x1 2.x V ds (V) V ds (V) Fig. 6. NFET I V characteristics. The SS device exhibits 2 25% increase in current.

4 1136 K. Rim et al. / Solid-State Electronics 47 (23) exhibits dramatic increases even at low strain and low Ge content, hole mobility enhancement is only significant at [Ge] of >2%, and diminishes at high vertical fields. 3. Device physics and design issues In order to realize the strain-enhanced CMOS performance to the fullest extent, both fundamental and technological challenges need to be addressed. As discussed above, strain-induced hole mobility enhancement requires a large amount of strain (i.e. [Ge]), and diminishes at high vertical field, consistent with the calculation in [8]. High Ge content increases the difficulty of various process integration issues, and due to the lack of mobility enhancement at high vertical fields, strained Si is expected to provide only limited enhancement in the future bulk and PDSOI PFETs with high channel doping and vertical field. On the other hand, for device structures such as symmetric double gate or FDSOI PMOSFETs in which the vertical field is inherently low, strained Si can provide a significant hole mobility enhancement. Recent experimental results [18] suggest that a significant hole mobility enhancement at high vertical field might be possible with an optimized epi layer preparation technique, but further investigation is needed. On the other hand, the large enhancements of electron mobility at high vertical fields require fundamental understanding. Although low field mobility is a property that can be measured and compared with relatively little ambiguity and is an essential parameter for device and circuit modeling, it is inadequate in quantitatively predicting the actual current drive of the deep sub-micron devices. Velocity saturation effect dominates in short channel lengths, reducing the impact by the changes in low field mobility. In addition, accurately extracting the instrinsic enhancement in device performance is difficult because the short channel device characteristic is a sensitive function of many device design parameters such as the junction profiles and extrinsic resistance. However, strain-induced energy splitting may also influence the transport of warm carriers in addition to the low field mobility. Fig. 9 [2] shows an estimated comparison of the density of states in the conduction band of strained Si and unstrained Si. Smaller density of states in strained Si should contribute to reduction of scattering rates even at carrier energies several times larger than kt, contributing to enhanced non-equilibrium transport and deep submicron NMOSFET current drive. In order to maximize the impact of strain-induced enhancement of intrinsic device performance, device scaling and design have to be optimized without compromise. This point is illustrated in Fig. 1 with a simple DOS Unstrained / DOS Strained Bulk Unstrained Si Strained Si ( E S =14 mev) E-E C (ev) Fig. 9. Estimated density of states (3D) in strained Si [2]. For carriers with energy up to.3 ev, the DOS in strained Si is significantly reduced compared to bulk Si. Expected Enhancement Factor: SS/Control Total Extrinsic G m,sat of Control Device ( µ S/ µ m) R EXT = 1 Ω-µ m 1.6 R EXT = 2 Ω-µ m 1.6 R EXT = 3 Ω-µ m Total R ON of Control Device ( Ω-µ m) Fig. 1. Expected enhancement in total R ON and external g m as a function of extrinsic resistance R ext assuming 7% and 3% increase in mobility and intrinsic g m in the SS devices. estimation of expected enhancements in the device onresistance R ON (which is inversely proportional to the drain current in the linear region) and the saturation transconductance g m;sat. For instance, assuming R ON ¼ 3 Xlm for the control device and parasitic resistance R ext ¼ 2 Xlm for both the control and SS devices, a 7% increase in mobility will be diluted to provide only 16% improvement in R ON. Similarly, assuming g m;sat ¼ 1 ls/lm for the control device, R ext of 2 Xlm (equally divided between source and drain) dilutes a 3% enhancement in intrinsic g m to 26% even in this simplified (neglecting the impact of a finite drain conductance in saturation) and optimistic estimation. Due to the low thermal conductivity of the thick SiGe layer, the SS MOSFETs exhibit significant self-heating, 2 1 Density of States (1 22 cm -2 ev -1 )

5 K. Rim et al. / Solid-State Electronics 47 (23) Fig. 11. Comparison of pulse- (symbols) and DC- (lines) measured I V [21]. Significant self-heating is observed in the SS devices. analogous that observed in SOI MOSFETs. Fig. 11 shows a comparison of DC- and pulse-measured I V of a SS NMOSFET [21]. In typical CMOS digital logic circuits, device duty cycle is expected to be much shorter than the thermal time constant of self-heating. However, in analog applications, self-heating will in effect induce a significant rise in device operation temperature, affecting the performance. Techniques to reduce the SiGe layer thickness in the structure can improve the self-heating characteristics. 4. Material and integration issues The foremost critical challenge in the SS CMOS technology is the control of dislocation defects in the epitaxial layers. Fig. 12 shows a cross-sectional TEM of dislocations in an unoptimized SiGe buffer reaching up to the device region. A finite density of misfit and threading dislocations are present in the SiGe buffers grown by the graded buffer growth techniques ([22,23] Fig. 12. XTEM of dislocation in the SiGe buffer. for example). Such dislocations can cause increase in junction leakage and device OFF current I off. For ULSI implementation, innovations and optimizations are required to minimize the propagation of dislocations in strained Si/relaxed SiGe structures. Thermal processing during CMOS fabrication steps can cause relaxation of the strain in the Si layer [24], or out-diffusion of Ge. Raman spectroscopy was used to measure the changes in strained Si/relaxed SiGe before and after RTA steps (Fig. 13) [25]. The position of the strained Si peak does not shift distinctly, while the signal strength decreases with RTA. This indicates that while the RTA at 1 C does not cause measurable strain relaxation, it effectively reduces the Si thickness by Ge out-diffusion. The thermal budget during device fabrication has to be optimized carefully to avoid strain relaxation and Ge out-diffusion into the channel layer. In addition, geometric effects and interaction with processrelated stress have to be understood and controlled. Understanding in this area is very limited at this time. Doping diffusion in SiGe affects device design. Fig. 14 shows SIMS profile of As before and after RTA. Arsenic diffusion in SiGe is significantly enhanced in comparison.15 Anneal Temp = 1 C (a) Anneal Temp = 1 C (b) Normalized Intensity (a.u.).1.5 no anneal 5sec 3 sec. 3 sec Wavenumber (cm -1 ) no anneal 3 sec Wavenumber (cm -1 ) Fig. 13. Intensity vs Raman shift for Si/SiGe layers with 2 nm Si capping layer, for no anneal, and the anneals at 1 C, 5 s, 3 s, and 5 min [25]. (a) Raman spectrum as measured and (b) curve fit to the strained Si peaks.

6 1138 K. Rim et al. / Solid-State Electronics 47 (23) to that in Si. In future device experiments, such a difference must be taken into account for the proper design of junction depth, overlap capacitance, and V T. SiGe also interacts with silicide formation. For the cobalt salicide process, Ge hinders transition to the low resistivity disilicide phase. Alternative material or integration schemes are required to achieve acceptable salicide properties. Lastly, implementing strained Si devices on SGOI (SiGe-on-insulator) structures to realize strained Si-oninsulator (SSOI) is a challenging materials problem. The (a) Concentration (cm -3 ) 1E22 1E21 1E2 1E19 1E18 1E17 as implanted As in SiGe (2%) after As in Si after 1E Depth (A) Fig. 14. Arsenic profile before and after RTA. As motion in SiGe is significantly enhanced compared to in Si. SSOI has the potential to combine the advantages of strained Si and SOI, and mitigate some of the SS devicespecific disadvantages such as higher junction leakage and junction capacitance. Methodologies proposed and reported so far include layer transfer by wafer bonding [17], SIMOX in relaxed SiGe [14], and Ge condensation in strained SiGe/SOI structure by thermal annealing and oxidation [26], which are summarized in Fig. 15. A successful SGOI technology will require high material quality and path to scaling the total SiGe/Si thickness to enable ultrathin SGOI structures. 5. Conclusion Numerous challenges and questions remain before the realization of a manufacturable strained Si CMOS technology, but the potential of geometric scaling-independent performance enhancement provides a strong motivation. Fig. 16 shows the estimated trade-off between physical gate length L gate and equivalent oxide thickness at inversion T inv, required to achieve a given CV =I metric. In this particular regime of scaling, a 15% improvement in current drive by strained Si can relax the T inv requirement by.4 nm for a given L gate, (assuming for a device design point where T ox is not the limiting factor for controlling short channel effects and off current) or relax the L gate requirement by 1 nm for a given T inv while accomplishing the same performance. For low power applications, strain-induced enhancement allows reduction of stand-by and switching power by scaling the supply voltage V DD or V T while maintaining a given current drive. Because the strain-induced enhancement adds to the improvement provided by continued geometric scaling of CMOS, it can be used to achieve high speed, lower power [2], or a relaxed geometric scaling requirement. 4 (b) Physical Gate Length L gate (nm) Control Strained Si 15% I ON increase (c) Fig. 15. Methods to form SGOI: (a) wafer bonding [17], (b) SIMOX [14], and (c) Ge condensation [26] Inversion T inv (nm) Fig. 16. L gate T inv trade-off to achieve a given CV =I. Straininduced current drive increase can relax the requirement for geometric scaling to achieve a given CMOS performance target.

7 K. Rim et al. / Solid-State Electronics 47 (23) References [1] Ismail K. Si/SiGe high speed field effect transistors. IEDM Tech Digest 1995: [2] Kesan VP, Subbana S, Restle PJ, Tejwani MJ, Aitken JM, Iyer SS, et al. High performance.25 mm p-mosfets with silicon-germanium channels for 3 K and 77 K operation. IEDM Tech Digest 1991: [3] Tezuka T, Sugiyama N, Mizuno T, Takagi S. Novel fullydepleted SiGe-on-insulator p-mosfets with high-mobility SiGe surface channels. IEDM Tech Digest 21: [4] Fischetti MV, Laux SE. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J Appl Phys 1994;8(4): [5] Takagi S, Hoyt JL, Welser JJ, Gibbons JF. Comparative study of phonon limited mobility of two dimensional electrons in strained and unstrained Si metal oxide semiconductor field effect transistors. J Appl Phys 1994;8(3): [6] Roldan JB, Gamiz F, Lopez-Villanueva JA, Carceller JE. A Monte Carlo study on the electron transport properties of high performance strained Si on relaxed SiGe channel MOSFETs. J Appl Phys 1996;8(9): [7] Formicone GF, Vasileska D, Ferry DK. Transport in the surface channel of strained Si on a relaxed Si 1 x /Ge x / substrate. Solid State Electron 1997;41(6): [8] Oberhuber R, Zandler G, Vogl P. Subband structure and mobility of two dimensional holes in strained Si/SiGe MOSFETÕs. Phys Rev B 1998;58(15): [9] Nayak D, Woo JCS, Park JS, Wang L, MacWilliams KP. High-mobility p-channel metal-oxide-semiconductor fieldeffect transistor on strained Si. Appl Phys Lett 1993;62: [1] Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement in strained-si n- MOSFETs. IEDM Tech Digest 1994: [11] Nayak DK, Goto K, Yutani A, Murota J, Shiraki Y. High mobility strained Si PMOSFETÕs. IEEE Trans Electron Dev 1996;43(1): [12] Rim K, Welser J, Hoyt JL, Gibbons JF. Enhanced hole mobilities in surface channel strained Si p MOSFETs. IEDM Tech Digest 1995: [13] Rim K, Hoyt JL, Gibbons JF. Transconductance enhancement in deep submicron strained Si n MOSFETs. IEDM Tech Digest 1998:77 1. [14] Mizuno T, Takagi S, Sugiyama N, Koga J, Tezuka T, Usuda K, et al. High performance strained Si p MOSFETs on SiGe on insulator substrates fabricated by SIMOX technology. IEDM Tech Digest 1999: [15] Mizuno T, Sugiyama N, Satake H, Takagi S, Advanced SOI MOSFETs with strained Si channel for high speed CMOS electron/hole mobility enhancement. Symposium on VLSI Technology, 2. p [16] Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J, et al. Strained Si NMOSFETs for high performance CMOS technology. Symposium on VLSI Technology, 21. p [17] Huang LJ, Chu JO, Goma S, DÕEmic CP, Koester SJ, Canaperi DF, et al. Carrier mobility enhancement in strained Si on insulator fabricated by wafer bonding. Symposium on VLSI Technology, 21. p [18] Sugii N, Hisamoto D, Washio K, Yokoyama N, Kimura S. Enhanced performance of strained-si MOSFETs on CMP SiGe virtual substrate. IEDM Tech Digest 21: [19] Takagi S, Toriumi A, Iwase M, Tango H. On the universality of inversion layer mobility in Si MOSFETs: Part I Effects of substrate impurity concentration. IEEE Trans Electron Dev 1994;41(12): [2] Rim K, Hoyt JL, Gibbons JF. Fabrication and analysis of deep submicron strained Si nmosfetõs. IEEE Trans Electron Dev 1994;47(8): [21] Jenkins K, Rim K. Measurement of the effect of selfheating in strained-silicon MOSFETs. IEEE Electron Dev Lett 22;23(6):36 2. [22] LeGoues FK, Meyerson BS, Morar JF, Kirchner PD. Mechanism and conditions for anomalous strain relaxation in graded thin films and superlattices. J Appl Phys 1992;71: [23] Fitzgerald EA, Xie YH, Monroe D, Silverman PJ, Kuo JM, Kortan AR, et al. Relaxed GeSi structures for III V integration with Si and high mobility two-dimensional electron gases in Si. J Vac Sci Technol B 1992;1:187. [24] Mooney PM et al. Mat Res Symp Proc Fall, 21. [25] Koester SJ, Rim K, Chu JO, Mooney PM, Ott JA, Hargrove MA. Effect of thermal processing on strain relaxation and interdiffusion in Si/SiGe heterostructures studied using Raman spectroscopy. Appl Phys Lett 22; 79(14): [26] Tezuka T, Sugiyama N, Mizuno T, Suzuki M, Takagi S. A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub 1 nm strained silicon on insulator MOSFETs. Jpn J Appl Phys 21; 4(4B):