TK28F K (256K X 8) CMOS FLASH MEMORY

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1 TK28F K (256K X 8 CMOS FLASH MEMORY Nvember 16, 2017 Prduct Overview Features General Descriptin Nn-vlatile Flash Memry Fast Read access Time = 120 ns. Flash Electrical Chip-Erase 3 Secnd Typical Chip-Erase Quick Prgramming Algrithm 10 μs Typical Byte-Prgram 12.5 Secnd Chip-Prgram 12.0 V ±5% VPP chip erase 100,000 Erase/Prgram Cycles 10 year data retentin CMOS Lw Pwer Cnsumptin 10 ma Typical Active Current 50 μa Typical Standby Current Cmmand Register Architecture fr Micrprcessr/Micrcntrller Cmpatible Write Interface Great Nise Immunity Features ±10% VCC Tlerance -40 C t +85 C peratin Industrial Safely abrt Erase r Prgram sequence at any time including Integrated Prgram/Erase Stp Timer Prtectin against inadvertent prgramming during pwer up. JEDEC-Standard Pinuts 32-Pin Plastic Dip 32-Lead PLCC 32-Lead TSOP The Tekms TK28F020 is a high speed 2M CMOS nn-vlatile flash memry arranged as 256K x 8. (262,144 x 8 bits It is electrically erasable and reprgrammable. It is well suited fr use in applicatins where cdes are changed after the initial prgramming, during manufacture, final test r after sale. Memry cntents can be changed in a test fixture, in a PROM prgrammer, r in system. The TK28F020 is manufactured t allw fr lw pwer cnsumptin and immunity t nise. The device is designed t withstand 100,000 prgram/erase cycles withut lsing data integrity. Data retentin is at least 10 years. Standby current maximum is 100 μa prviding significant pwer saving when the device is deselected. Access time f 120 ns prvides zer wait state perfrmance cmpatible with many micrcntrllers and micrprcessrs. Electrical erasure f the entire memry is typically achieved in less than 5 secnds. 12 vlt prgramming and erase vltage makes it cmpatible with similar devices. The erase prcedure has a tw-step prcess that ensures against accidental erasure f the cntents f the memry. The erase cmmand is actually written twice befre it is executed. An integrated stp feature allws fr autmatic timing cntrl eliminating the need fr a maximum erase timing specificatin. An Abrt/Reset cmmand is available t allw the user t safely abrt an erase r prgram sequence. The abrt/reset peratin can interrupt at any time in a prgram r erase peratin and the device is reset t the Read Mde. Prtectin against inadvertent prgramming during pwer up is prvided. VPP and VCC may be pwered up in any rder, n sequencing is required. The TK28F020 is ffered in 32-Pin Plastic DIP, 32- Lead PLCC and 32-Lead TSOP packages. Cnfrming t JEDEC standards, it is pin fr pin cmpatible with standard EPROM and EEPROM devices. The TK28F020 is ften used as a drp in replacement in systems riginally designed fr ther manufacturer s 28F020 devices /16/17

2 TK28F020 CMOS 2048K Flash Memry 2,097,152 Bit Memry Array Pin Cnfiguratins PLCC Package PDIP Package /16/17

3 TK28F020 CMOS 2048K Flash Memry TSOP Pin Functins DIP/ PCC Pin # TSOP Pin # Pin Name Type Functin DIP/ PCC Pin # TSOP Pin # Pin Name Type Functin 1 9 V PP Input Prgram Erase Vltage Supply I/O 3 Input Data Input/ Output 2 10 A16 Input Address memry I/O 4 Input Data Input/ Output 3 11 A15 Input Address memry I/O 5 Input Data Input/ Output 4 12 A12 Input Address memry I/O 6 Input Data Input/ Output 5 13 A7 Input Address memry I/O 7 Input Data Input/ Output 6 14 A6 Input Address memry CE Input Chip Enable 7 15 A5 Input Address memry A10 Input Address memry 8 16 A4 Input Address memry OE Input Output Enable 9 17 A3 Input Address memry 25 1 A11 Input Address memry A2 Input Address memry 26 2 A9 Input Address memry A1 Input Address memry 27 3 A8 Input Address memry A0 Input Address memry 28 4 A13 Input Address memry I/O 0 I/O Data Input/ Output 29 5 A14 Input Data Input/ Output I/O 1 I/O Data Input/ Output 30 6 A17 Input Address Memry I/O 2 I/O Data Input/ Output 31 7 WE Input Data Input/ Output V SS Supply Grund 32 8 V CC Supply Vltage Supply /16/17

4 TK28F020 CMOS 2048K Flash Memry Abslute Maximum Ratings* Temperature Under Bias -50 C t +95 C Strage Temperature -55 C t 150 C Vltage n Any Pin with Respect t Grund(1-2.0V t VCC + 2.0V Vltage n Pin A9 with Respect t Grund(1-2.0V t +13.5V VPP with Respect t Grund during Prgram/Erase(1-2.0V t +14.0V Package Pwer Dissipatin Capability (TA = 25 C 1.0 W Lead Sldering Temperature (10 secnds 300 C Output Shrt Circuit Current(2 100 ma Reliability Characteristics Symbl Parameter Min Max Units Test Methd N END (3 Endurance 100K Cycles/Byte MIL-STD-883, Test Methd 1033 T DR (3 Data Retentin 10 Years MIL-STD-883, Test Methd 1008 V ZAP (3(5 ESD Susceptibility 2000 Vlts MIL-STD-883, Test Methd 3015 I LTH (3(4 Latch-Up 100 ma JEDEC Standard 17 CAPACITANCE T A = 25 C, f = 1.0 MHz Limits Symbl Test Min Max. Units Cnditins C IN (3 Input Pin Capacitance 6 pf VIN = 0V C OUT (3 Output Pin Capacitance 10 pf VOUT = 0V C VPP (3 VPP Supply Capacitance 25 pf VPP = 0V NOTE: Stresses abve thse listed under Abslute Maximum Ratings may cause permanent damage t the device. These are stress ratings nly, and functinal peratin f the device at these r any ther cnditins utside f thse listed in the peratinal sectins f this specificatin is nt implied. Expsure t any abslute maximum rating fr extended perids may affect device perfrmance and reliability. Other Ntes: (1 The minimum DC input vltage is 0.5V. During transitins, inputs may undersht t 2.0V fr perids f less than 20 ns. Maximum DC vltage n utput pins is V CC +0.5V, which may versht t V CC + 2.0V fr perids f less than 20ns. (2 Output shrted fr n mre than ne secnd. N mre than ne utput shrted at a time. (3 This parameter is tested initially and after a design r prcess change that affects the parameter. (4 Latch-up prtectin is prvided fr stresses up t 100 ma n address and data pins frm 1V t V CC +1V. (5 Pins A9 and Vpp are tested t the /16/17

5 TK28F020 CMOS 2048K Flash Memry D.C. Operating Characteristics Symbl Parameter (V CC = +5V 10%, unless therwise specified Limits Min. Max. Unit Test Cnditins I LI Input Leakage Current 1 A I LO Output Leakage Current 1 A I SB1 VCC Standby Current CMOS 100 A VIN = VCC r VSS VCC = 5.5V, OE = VIH VOUT = VCC r VSS, VCC = 5.5V, OE = VIH CE = VCC 0.5V, VCC = 5.5V I SB2 VCC Standby Current TTL 1 ma CE = VIH, VCC = 5.5V I CC1 VCC Active Read Current 30 ma I (1 CC2 VCC Prgramming Current 15 ma I CC3 VCC Erase Current 15 ma I CC4 VCC Prg./Erase Verify Current 15 ma VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 6 MHz VCC = 5.5V, Prgramming in Prgress VCC = 5.5V, Erasure in Prgress VCC = 5.5V, Prgram r Erase Verify in Prgress I PPS VPP Standby Current 10 A V PP = V PPL I PP1 VPP Read Current 200 A V PP = V PPH I PP2 (1 VPP Prgramming Current 30 ma I PP3 (1 VPP Erase Current 30 ma I PP4 (1 VPP Prg./Erase Verify Current 5 ma V PP = V PPH, Prgramming in Prgress V PP = V PPH, Erasure in Prgress VPP = VPPH, Prgram r Erase Verify in Prgress V IL Input Lw Level TTL V V ILC Input Lw Level CMOS V V OL Output Lw Level 0.45 V IOL = 5.8mA, VCC = 4.5V V IH Input High Level TTL 2 VCC+0.5 V V IHC Input High Level CMOS VCC*0.7 VCC+0.5 V V OH1 Output High Level TTL 2.4 V IOH = 2.5mA, VCC = 4.5V V OH2 Output High Level CMOS VCC 0.4 V IOH = 400 A, VCC = 4.5V V ID A9 Signature Vltage V A9 = VID (1 I ID A9 Signature Current 200 A V LO VCC Erase/Prg. Lckut Vltage 2.5 V Nte: (1 This parameter is tested initially and after a design r prcess change that affects the parameter /16/17

6 TK28F020 CMOS 2048K Flash Memry SUPPLY CHARACTERISTICS Limits Symbl Parameter Min Max. Unit V CC V CC Supply Vltage V V PPL V PP During Read Operatins 0 Vcc+0.5 V V PPH V PP During Read/Erase/Prgram V A.C. CHARACTERISTICS, Read Operatin V CC = +5V 10%, unless therwise specified. Temperature -40 C t +85 C, unless therwise specified. JEDEC Symbl Standard Symbl Parameter Min Max Unit t AVAV t RC Read Cycle Time 120 ns t ELQV t CE Access Time 120 ns t AVQV t ACC Address Access Time 120 ns t GLQV t OE Access Time 50 ns t AXQX t OH Output Hld frm Address / Change 0 ns t GLQX t OLZ (1(6 t Output in Lw-Z 0 ns t ELZX t LZ (1(6 t Output in Lw-Z 0 ns t GHQZ t (1(2 DF High t Output High-Z 20 ns t EHQZ t (1(2 DF High t Output High-Z 30 ns t WHGL (1 Write Recvery Time Befre Read 6 s Figure 1. A.C. Testing Input / Output Wavefrms (3(4(5 2.4 V 2.0 V 0.45 V 0.8 V UNDER TEST C L = 100 pf C L Includes Jig Capacitance 51This parameter is tested initially and after a design r prcess change that affects the parameter. (1 Output flating (High-Z is defined as the state where the external data line is n lnger driven by the utput buffer. (2 Input Rise and Fall Times (10% t 90% < 10 ns /16/17

7 TK28F020 CMOS 2048K Flash Memry (3 Input Pulse Levels = 0.45V and 2.4V. Fr High Speed Input Pulse Levels 0.0V and 3.0V. (4 Input and Output Timing Reference = 0.8V and 2.0V. Fr High Speed Input and Output Timing Reference = 1.5V. (5 Lw-Z is defined as the state where the external data may be driven by the utput buffer but may nt be valid. (6 Fr lad and reference pints, see Fig. 1 A.C. CHARACTERISTICS, Prgram/Erase Operatin V CC = +5V ±10%, unless therwise specified. JEDEC Symbl Standard Symbl Parameter Min Typ Max Unit tavav twc Write Cycle Time 120 ns tavwl tas Address Setup Time 0 ns twlax tah Address Hld Time 40 ns tdvwh tds Data Setup Time 40 ns twhdx tdh Data Hld Time 10 ns telwl tcs Setup Time 0 ns twheh t CH Hld Time 0 ns twlwh twp Pulse Width 40 ns twhwl twph High Pulse Width 20 ns twhwh1 (2 - Prgram Pulse Width 10 s twhwh (2 - Erase Pulse Width 9.5 ms twhgl - Write Recvery Time Befre 6 s R d tghwl - Read Recvery Time Befre 0 s Wit tvpel - VPP Setup Time t 100 ns Erase and Prgramming Perfrmance (1 Parameter Min Typ Max Unit Chip Erase Time ( Sec Chip Prgram Time (3( Sec Nte: (1 Please refer t Supply characteristics fr the value f V PPH and V PPL. The V PP supply can be either hardwired r switched. If V PP is switched, V PPL can be grund, less than V CC + 2.0V r a n cnnect with a resistr tied t grund. (2 Prgram and Erase peratins are cntrlled by internal stp timers. (3 Typicals are nt guaranteed, but based n characterizatin data. Data taken at 25 C, 12.0V V PP. (4 Minimum byte prgramming time (excluding system verhead is 16 s (10 s prgram + 6 s write recvery, while maximum is 400 s/ byte (16 s x 25 lps. Max chip prgramming time is specified lwer than the wrst case allwed by the prgramming algrithm since mst bytes prgram significantly faster than the wrst case byte /16/17

8 TK28F020 CMOS 2048K Flash Memry Functin Table (1 Mde Pins CE OE WE V PP I/O Ntes Read V IL V IL V IH V PPL D OUT Output Disable V IL V IH V IH X High-Z Standby V IH X X V PPL High-Z Signature (MFG V IL V IL V IH X 31H A 0 = V IL, A 9 = 12V Signature (Device V IL V IL V IH X B4H A 0 = V IH, A 9 = 12V Prgram/Erase V IL V IH V IL V PPH D IN See Cmmand Table Write Cycle V IL V IH V IL V PPH D IN During Write Cycle Read Cycle V IL V IL V IH V PPH D OUT During Write Cycle Write Cmmand Table Cmmands are written int the cmmand register in ne r tw write cycles. The cmmand register can be altered nly when V PP is high and the instructin byte is latched n the rising edge f. Write cycles als internally latch addresses and data required fr prgramming and erase peratins. Mde Pins First Bus Cycle Secnd Bus Cycle Operatin Address D IN Operatin Address D IN D OUT Set Read Write X 00H Read A IN D OUT Read Sig. (MFG Write X 90H Read 00 31H Read Sig. (Device Write X 90H Read 01 B4H Erase Write X 20H Write X 20H Erase Verify Write A IN A0H Read X D OUT Prgram Write X 40H Write A IN D IN Prgram Verify Write X C0H Read X D OUT Reset Write X FFH Write X FFH Nte: (1 Lgic Levels: X = Lgic D nt care (V IH, V IL, V PPL, V PPH /16/17

9 TK28F020 CMOS 2048K Flash Memry READ OPERATIONS Read Mde A Read peratin is perfrmed with bth and lw and with high. VPP can be either high r lw, hwever, if VPP is high, the Set READ cmmand has t be sent befre reading data (see Write Operatins. The data retrieved frm the I/O pins reflects the cntents f the memry lcatin crrespnding t the state f the 17 address pins. The respective timing wavefrms fr the read peratin are shwn in Figure 3. Refer t the AC Read characteristics fr specific timing parameters. Signature Mde The signature mde allws the user t identify the IC manufacturer and the type f device while the device resides in the target system. This mde can be activated in either f tw ways; thrugh the cnventinal methd f applying a high vltage (12V t address pin A9 r by sending an instructin t the cmmand register (see Write Operatins. The cnventinal mde is entered as a regular READ mde by driving the and pins lw (with high, and applying the required high vltage n address pin A9 while all ther address lines are held at VIL. A Read cycle frm address 0000H retrieves the binary cde fr the IC manufacturer n utputs I/O0 t I/O7: Tekms Cde = (34H A Read cycle frm address 0001H retrieves the binary cde fr the device n utputs I/O0 t I/O7. Standby Mde 28F020 Cde = (B4H With at a lgic-high level, the TK28F020 is placed in a standby mde where mst f the device circuitry is disabled, thereby substantially reducing pwer cnsumptin. The utputs are placed in a high-impedance state. Figure 3. A.C. Timing fr Read Operatin POWER UP STANDBY DEVICE AND ADDRESS SELECTION OUPUTS ENABLED DATA VALID STANDBY POWER DOWN ADDRESSES ADDRESS STABLE t AVAV (t RC CE (E t EHQZ t( DF OE (G t WHGL t GHQZ (t DF WE (W t GLQV (t OE t GLQX (t OLZ t ELQX (t LZ t ELQV (t CE t AXQX t( OH DATA (I/O HIGH-Z OUTPUT VALID HIGH-Z t AVQV (t ACC /16/17

10 TK28F020 CMOS 2048K Flash Memry WRITE OPERATIONS The fllwing peratins are initiated by bserving the sequence specified in the Write Cmmand Table. Read Mde The device can be put int a standard READ mde by initiating a write cycle with 00H n the data bus. The subsequent read cycles will be perfrmed similar t a standard EPROM r EEPROM Read. Signature Mde An alternative methd fr reading device signature (see Read Operatins Signature Mde, is initiated by writing the cde 90H int the cmmand register while keeping VPP high. A read cycle frm address 0000H with and lw (and high will utput the device signature. Tekms Cde = (34H A Read cycle frm address 0001H retrieves the binary cde fr the device n utputs I/O 0 t I/O 7. 28F020 Cde = (B4H /16/17

11 TK28F020 CMOS 2048K Flash Memry u Nte: (1 The algrithm MUST BE FOLLOWED t ensure prper and reliable peratin f the device /16/17

12 TK28F020 CMOS 2048K Flash Memry Erase Mde During the first Write cycle, the cmmand 20H is written int the cmmand register. In rder t cmmence the erase peratin, the identical cmmand f 20H has t be written again int the register. This tw-step prcess ensures against accidental erasure f the memry cntents. The final erase cycle will be stpped at the rising edge f, at which time the Erase Verify cmmand (A0H is sent t the cmmand register. During this cycle, the address t be verified is sent t the address bus and latched when ges lw. An integrated stp timer allws fr autmatic timing cntrl ver this peratin, eliminating the need fr a maximum erase timing specificatin. Refer t AC Characteristics (Prgram/Erase fr specific timing parameters. Erase-Verify Mde The Erase-Verify peratin is perfrmed n every byte after each erase pulse t verify that the bits have been erased. Prgramming Mde The prgramming peratin is initiated using the prgramming algrithm f Figure 7. During the first write cycle, the cmmand 40H is written int the cmmand register. During the secnd write cycle, the address f the memry lcatin t be prgrammed is latched n the falling edge f, while the data is latched n the rising edge f. The prgram peratin terminates with the next rising edge f. An integrated stp timer allws fr autmatic timing cntrl ver this peratin, eliminating the need fr a maximum prgram timing specificatin. Refer t AC Characteristics (Prgram/Erase fr specific timing parameters /16/17

13 TK28F020 CMOS 2048K Flash Memry u u Nte: (1 The algrithm MUST BE FOLLOWED t ensure prper and reliable peratin f the device /16/17

14 TK28F020 CMOS 2048K Flash Memry Prgram-Verify Mde A Prgram-Verify cycle is perfrmed t ensure that all bits have been crrectly prgrammed fllwing each byte prgramming peratin. The specific address is already latched frm the write cycle just cmpleted, and stays latched until the verify is cmpleted. The Prgram-Verify peratin is initiated by writing C0H int the cmmand register. An internal reference generates the necessary high vltages s that the user des nt need t mdify VCC. Refer t AC Characteristics (Prgram/Erase fr specific timing parameters. Abrt/Reset An Abrt/Reset cmmand is available t allw the user t safely abrt an erase r prgram sequence. Tw cnsecutive prgram cycles with FFH n the data bus will abrt an erase r a prgram peratin. The abrt/ reset peratin can interrupt at any time in a prgram r erase peratin and the device is reset t the Read Mde. POWER UP/DOWN PROTECTION The TK28F020 ffers prtectin against inadvertent prgramming during VPP and VCC pwer transitins. When pwering up the device there is n pwer-n sequencing necessary. In ther wrds, VPP and VCC may pwer up in any rder. Additinally VPP may be hardwired t VPPH independent f the state f VCC and any pwer up/dwn cycling. The internal cmmand register f the TK28F020 is reset t the Read Mde n pwer up. POWER SUPPLY DECOUPLING T reduce the effect f transient pwer supply vltage spikes, it is gd practice t use a 0.1 μf ceramic capacitr between VCC and VSS and VPP and VSS. These high-frequency capacitrs shuld be placed as clse as pssible t the device fr ptimum decupling /16/17

15 TK28F020 CMOS 2048K Flash Memry Ordering Infrmatin Package Temperature Speed Order Number 32 Pin PLCC -40 C t +85 C 120 ns TK28F020NI Pin PDIP -40 C t +85 C 120 ns TK28F020PI Pin TSOP -40 C t +85 C 120 ns TK28F020TI-120 Nte: An earlier data sheet described the 120 ns part as the TK28F020NI-12. This was a typ, and the crrect suffix is The -120 is an Intel naming cnventin, while the -12 is a Catalyst naming cnventin. Tekms fllws the Intel cnventin fr speed classificatin. Cntact Infrmatin The TK28F020 can be rdered directly frm Tekms: Tekms, Inc phne 7901 E Riverside Rd. Sales@Tekms.Cm Bldg. 2, Suite Austin, TX Revisin Histry Date Revisin Descriptin 1/08/ Initial Release 9/24/ Specificatin Data Added 1/27/ Ordering Infrmatin fr 90ns added, 4/11/ Crrect pin numbering. Make military part a -95 speed 11/16/ Add PDIP and TSOP package, Remve -90 and -95 parts. Crrect typs 2017 Tekms, Inc. Infrmatin cntained in this publicatin regarding device applicatins and the like is intended fr suggestin nly and may be superseded by updates. N representatin r warranty is given and n liability is assumed by Tekms Incrprated with respect t the accuracy r use f such infrmatin, r infringement f patents r ther intellectual prperty rights arising frm such use r therwise. Use f Tekms prducts as critical cmpnents in life supprt systems is nt authrized except with express written apprval by Tekms. N licenses are cnveyed, implicitly r therwise, under any intellectual prperty rights. The Tekms lg and name are registered trademarks f Tekms, Inc. All rights reserved. All ther trademarks mentined herein are the prperty f their respective cmpanies. All rights reserved. Terms and prduct names in this dcument may be trademarks f thers /16/17

3.3 V 256 K 16 CMOS SRAM

August 2004 AS7C34098A 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed