2 Megabit (256K x 8) SuperFlash MTP SST27SF020, SST27VF020

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Richard Bradley
5 years ago
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v Standby Current: µa (typical) for both SF00 and VF00 Fast Access ime.0-volt Read - 0 and 0 ns.

1 查询 SSVF00 供应商捷多邦, 专业 PCB 打样工厂, 小时加急出货 Megabit (K x ) SuperFlash MP SSSF00, SSVF00.0-Volt Read Operation for SF00.-Volt Read Operation for VF00 Superior Reliability Endurance: Minimum 00 Cycles Greater than 0 years Data Retention Low Power Consumption Active Current: 0 ma (typical) for V and ma (typical) for.v Standby Current: µa (typical) for both SF00 and VF00 Fast Access ime.0-volt Read - 0 and 0 ns.-volt Read - 00 and 0 ns PRODUC DESCRIPION he SF00/VF00 are a K x CMOS, many time programmable (MP) low cost flash memories, manufactured with SS s proprietary, high performance SuperFlash technology. he split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. he SF00/VF00 can be electrically erased and programmed at least 00 times using an external programmer. he SF00/VF00 have to be erased prior to programming. he SF00/VF00 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance byte programming, the SF00/VF00 provide a byte-program time of 0 µs. he entire memory can be programmed byte by byte in. seconds. Designed, manufactured, and tested for a wide spectrum of applications, the SF00/ VF00 are offered with an endurance of 00 cycles. Data retention is rated at greater than 0 years. he SF00/VF00 are suited for applications that require infrequent writes and low power nonvolatile storage. he SF00/VF00 will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV- EPROMs, OPs, and mask ROMs. o meet surface mount and conventional through hole requirements, the SF00/VF00 are offered in -pin PLCC, -pin PDIP and -pin SOP packages. See Figures and for pinouts. Fast Programming Operation 0 µs per byte. second for the entire chip Features Electrical Erase Does Not Require UV Source Chip Erase ime: 0 ms L I/O Compatibility JEDEC Standard Byte-wide EPROM Pinouts V Power Supply for Programming/Erase Packages Available -Pin PLCC -Pin Plastic DIP -Pin SOP Device Operation he SF00/VF00 are low cost flash solutions that can be used to replace existing UV-EPROM, OP, and mask ROM sockets. It is functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, the device also supports electrical erase operation via an external programmer. he SF00/VF00 do not require a UV source to erase, and therefore the packages do not have a window. Read he Read operation of the SF00/VF00 are controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output ( CE). Data is available at the output after a delay of OE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least CE - OE. When the CE# pin is high, the chip is deselected and a typical standby current of µa is consumed. OE# is the output control and is used to gate data from the output pins. he data bus is in high impedance state when either CE# or OE# is high. Programming operation he SF00/VF00 are programmed by using an external programmer. he programming mode is activated by asserting V (±%) on Vpp pin, Vcc = V±%, V IL on CE# pin, and V IH on OE# pin. he device is programmed byte by byte with the desired data at the desired address using a single pulse (PGM# pin low) of

2 Megabit SuperFlash MP SSSF00, SSVF00 0 µs. Using the MP programming algorithm, the byte programming process continues byte by byte until the entire chip (K bytes) has been programmed. Chip Erase Operation he only way to change a data from a 0 to is by electrical erase that changes every bit in the device to. Unlike traditional EPROMs, which use UV light to do the chip erase, the SF00/VF00 use an electrical chip erase operation. his saves a significant amount of time (about 0 minutes for erase operation). he entire chip can be erased in a single pulse of 0 ms (PGM# pin low). In order to activate the erase mode, the V (±%) is applied to V PP and A pins, Vcc = V±%, V IL on CE# pin, and V IH on OE# pin. All other address and data pins are don t care. he falling edge of PGM# will start the Chip Erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to figure for the flow chart. he SF00/VF00 can also be reprogrammed in the system. his requires the availability of V for V PP to program and an additional V for address A to erase. Product Identification Mode he product identification mode identifies the device as the SF00/VF00 and manufacturer as SS. his mode may be accessed by hardware method. o activate this mode, the programming equipment must force V H (V±%) on address A with V PP pin at V±%. wo identifier bytes may then be sequenced from the device outputs by toggling address line A 0. For details, see able for hardware operation. ABLE : PRODUC IDENIFICAION ABLE Byte Data Manufacturer s Code 0000 H BF H SF00 Device Code 000 H A H VF00 Device Code 000 H C H PGM.0 FUNCIONAL BLOCK DIAGRAM OF HE SSSF00/VF00 X-Decoder,0, Bit EEPROM Cell Array A - A 0 Address buffer Y-Decoder CE# OE# A V PP PGM# Control Logic I/O Buffers DQ - DQ 0 MSW B.0

3 Megabit SuperFlash MP SSSF00, SSVF00 A A A A A A PGM# Vcc Vpp A A A A A A A Standard Pinout op View Die up 0 0 OE# A CE# DQ DQ DQ DQ DQ Vss DQ DQ DQ0 A0 A A A MSW F0.0 FIGURE : PIN ASSIGNMENS FOR -PIN SOP PACKAGES V PP A A A A A A A A A A A0 DQ0 DQ DQ V SS 0 Pin PDIP op View 0 V CC PGM# A A A A A A OE# A CE# DQ DQ DQ DQ DQ A A A A A A A A0 DQ0 A V PP PGM# A A V CC A 0 -Lead PLCC op View 0 DQ V SS DQ DQ DQ DQ DQ A A A A A OE# A CE# DQ MSW F0.0 FIGURE : PIN ASSIGNMENS FOR -PIN PLASIC DIPS AND -LEAD PLCCS ABLE : PIN DESCRIPION Symbol Pin Name Functions A -A 0 Address Inputs o provide memory addresses DQ -DQ 0 Data Input/Output o output data during read cycles and receive input data during program cycle, the outputs are in tri-state when OE# or CE# is high CE# Chip Enable o activate the device when CE# is low OE# Output Enable o gate the data output buffers during read operation PGM# Program/Erase Pin Used for program or erase (PGM# = V IL pulse during program or erase) V PP Power Supply for High voltage pin during chip erase and programming operation Program or Erase -volt (±%) V CC Power Supply o provide -volt supply (±%) for the SF00 and -volt supply (.-. V) for the VF00 Ground V SS PGM.

4 ABLE : OPERAION MODES SELECION Megabit SuperFlash MP SSSF00, SSVF00 Mode CE# OE# PGM# A V PP DQ Address Read V IL V IL X A IN V CC or D OU A IN V SS Output Disable V IL V IH X X V CC or High Z A IN V SS Program V IL V IH V IL A IN V PPH D IN A IN Standby V IH X X X V CC or High Z X V SS Chip Erase V IL V IH V IL V H V PPH High Z X Program/Erase V IH X X X V PPH High Z X Inhibit Product V IL V IL X V H V CC or Manufacturer Code (BF) A -A = V IL, A 0 = V IL Identification V SS Device Code (A for A -A = V IL, A 0 = V IH SF00 & C for VF00) Note: X = V IL or V IH V PPH = V±%, V H = V±% PGM.0 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) emperature Under Bias... - C to + C Storage emperature... - C to + C D. C. Voltage on Any Pin to Ground Potential V to V CC+ 0.V ransient Voltage (<0 ns) on Any Pin to Ground Potential V to V CC +.0V Voltage on A and V PP Pin to Ground Potential V to.0v Package Power Dissipation Capability ( A = C)....0W hrough Hole Lead Soldering emperature ( Seconds) C Surface Mount Lead Soldering emperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. SF00 OPERAING RANGE (READ) Range Ambient emp V CC Commercial 0 C to +0 C V±% Industrial -0 C to + C V±% AC CONDIIONS OF ES Input Rise/Fall ime... ns Output Load... L Gate and C L = 0 pf See Figures and VF00 OPERAING RANGE (READ) Range Ambient emp V CC Commercial 0 C to +0 C.-.V Industrial -0 C to + C.-.V AC CONDIIONS OF ES Input Rise/Fall ime... ns Output Load... L Gate and C L = 0 pf See Figures and

5 Megabit SuperFlash MP SSSF00, SSVF00 ABLE : SF00 READ MODE DC OPERAING CHARACERISICS V cc = V±%, A = 0 C to 0 C (Commercial) or -0 C to + C (Industrial) Limits Symbol Parameter Min Max Units est Conditions I CC V CC Read Current 0 ma CE# = OE# = V IL all I/Os open, Address Input = V IL /V IH at f = / RC Min, V CC = V CC Max I PPR V PP Read Current 0 µa CE# = OE# = V IL, all I/Os open, Address Input = V IL/V IH at f = / RC Min, V CC = V CC Max, Vpp = Vcc I SB Standby V CC Current ma CE# = OE# = V IH, V CC = V CC Max (L input) I SB Standby V CC Current 0 µa CE#=OE#=V CC -0.V (CMOS input) V CC = V CC Max. I LI Input Leakage Current µa V IN = GND to V CC, V CC = V CC Max I LO Output Leakage Current µa V OU = GND to V CC, V CC = V CC Max V IL Input Low Voltage 0. V V CC = V CC Max V IH Input High Voltage.0 Vcc+0. V V CC = V CC Max V OL Output Low Voltage 0. V I OL =. ma, V CC = V CC Min V OH Output High Voltage. V I OH = -00µA, V CC = V CC Min I H Supervoltage Current 0 µa CE# = OE# = V IL, A = V H for A PGM. ABLE : VF00 READ MODE DC OPERAING CHARACERISICS V cc =.-.V, A = 0 C to 0 C (Commercial) or -0 C to + C (Industrial) Limits Symbol Parameter Min Max Units est Conditions I CC Vcc Read Current ma CE#=OE#=V IL all I/Os open, Address input = V IL/V IH at f=/ RC Min., V CC=V CC Max I PPR V PP Read Current 0 µa CE# = OE# = V IL, all I/Os open, Address Input = V IL /V IH at f = / RC Min, V CC = V CC Max, Vpp = Vcc I SB Standby V CC Current ma CE#=OE#=V IH, V CC =V CC Max. (L input) I SB Standby V CC Current µa CE#=OE#=V CC -0.V. (CMOS input) V CC = V CC Max. I LI Input Leakage Current µa V IN =GND to V CC, V CC = V CC Max. I LO Output Leakage Current µa V OU =GND to V CC, V CC = V CC Max. V IL Input Low Voltage 0. V V CC = V CC Max. V IH Input High Voltage.0 Vcc+0. V V CC = V CC Max. V OL Output Low Voltage 0. V I OL = 0 µa, V CC = V CC Min. V OH Output High Voltage. V I OH = -0 µa, V CC = V CC Min. I H Supervoltage Current 0 µa CE# = OE# = V IL, A = V H for A PGM.

6 Megabit SuperFlash MP SSSF00, SSVF00 ABLE : SF00/VF00 PROGRAM/ERASE DC OPERAING CHARACERISICS V cc = V±%, V pp = V PPH, A = C± C Limits Symbol Parameter Min Max Units est Conditions I CP V CC Erase or Program 0 ma CE# = V IL, Vpp = V±%, V CC = V CC Max Current I PP V PP Erase or Program ma CE# = V IL, Vpp = V±%, V CC = V CC Max Current I LI Input Leakage Current µa V IN = GND to V CC, V CC = V CC Max I LO Output Leakage Current µa V OU = GND to V CC, V CC = V CC Max V H Supervoltage for A.. V CE# = OE# = V IL I () H Supervoltage Current 00 µa CE# = OE# = V IL, A = V H Max for A V PPH High Voltage for V PP Pin.. V Note: () PGM.0 his parameter is measured only for initial qualification and after the design or process change that could affect this parameter. ABLE : POWER-UP IMINGS Symbol Parameter Maximum Units () PU-READ Power-up to Read Operation 0 µs PGM.0 Note: () his parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ABLE : CAPACIANCE ( A = C, f= MHz, other pins open) Parameter Description est Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf CI () N Input Capacitance V IN = 0V pf PGM.0 Note: () his parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ABLE : RELIABILIY CHARACERISICS Symbol Parameter Minimum Specification Units est Method N END Endurance 00 Cycles MIL-SD-, Method () DR Data Retention 0 Years JEDEC Standard A V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LH Latch Up 0 ma JEDEC Standard Note: PGM. () his parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

7 Megabit SuperFlash MP SSSF00, SSVF00 AC CHARACERISICS ABLE : SF00 READ CYCLE IMING PARAMEERS SF00-0 SF00-0 Symbol Parameter Min Max Min Max Units RC Read Cycle ime 0 0 ns CE Chip Enable Access ime 0 0 ns AA Address Access ime 0 0 ns OE Output Enable Access ime 0 0 ns () CLZ CE# Low to Active Output 0 0 ns () OLZ OE# Low to Active Output 0 0 ns () CHZ CE# High to High-Z Output 0 0 ns () OHZ OE# High to High-Z Output 0 0 ns () OH Output Hold from Address Change 0 0 ns ABLE : VF00 READ CYCLE IMING PARAMEERS PGM.0 VF00-00 VF00-0 Symbol Parameter Min Max Min Max Units RC Read Cycle ime 00 0 ns CE Chip Enable Access ime 00 0 ns AA Address Access ime 00 0 ns OE Output Enable Access ime 0 0 ns () CLZ CE# Low to Active Output 0 0 ns () OLZ OE# Low to Active Output 0 0 ns () CHZ CE# High to High-Z Output 0 0 ns () OHZ OE# High to High-Z Output 0 0 ns () OH Output Hold from Address Change 0 0 ns PGM.0

8 ABLE : PROGRAMMING/ERASE CYCLE IMING PARAMEERS Symbol Parameter Min Max Units () CES CE# Setup ime µs () CEH CE# Hold ime µs () AS Address Setup ime µs () AH Address Hold ime µs () PR V PP Pulse Rise ime 0 ns () VPS V PP Setup ime µs () VPH V PP Hold ime µs PW PGM# Program Pulse Width 0 0 µs EW PGM# Erase Pulse Width 0 00 ms () DS Data Setup ime µs () DH Data Hold ime µs () VR A Recovery ime for Erase µs AR A Rise ime to V during Erase 0 ns () AS A Setup ime during Erase µs () AH A Hold ime during Erase µs Megabit SuperFlash MP SSSF00, SSVF00 PGM.0 Note: () his parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

9 Megabit SuperFlash MP SSSF00, SSVF00 RC AA ADDRESS CE# CE OE# OE OHZ DQ -0 HIGH-Z OLZ OH DAA VALID CHZ DAA VALID CLZ Vpp V CC V SS PGM# V IH V IL FIGURE : READ CYCLE IMING DIAGRAM AC F0.0 ADDRESS (EXCEP A ) CE# OE# DQ -0 V IH V PPH CEH Vpp V CC V SS PR VPS VPH A V PPH V IH AS VR V IL AR AH PGM# CES EW FIGURE : ERASE IMING DIAGRAM AC F0.0

10 Megabit SuperFlash MP SSSF00, SSVF00 ADDRESS ADDRESS VALID AH CE# AS CEH OE# V IH DS DH DQ -0 HIGH-Z DAA VALID V PPH V CC VPS Vpp V SS PR PW VPH PGM# CES FIGURE : PROGRAM IMING DIAGRAM AC F0.0. INPU.0 REFERENCE POINS.0 OUPU MSW F0.0 AC test inputs are driven at V OH (. V L) for a logic and V OL (0. V L) for a logic 0. Measurement reference points for inputs and outputs are V IH (.0 V L) and V IL (0. V L). Inputs rise and fall times (% 0%) are < ns. FIGURE : AC INPU/OUPU REFERENCE WAVEFORMS

11 Megabit SuperFlash MP SSSF00, SSVF00 ES LOAD EXAMPLE O ESER V CC R L HIGH O DU C L R L LOW MSW F0.0 FIGURE : ES LOAD EXAMPLE

12 Megabit SuperFlash MP SSSF00, SSVF00 Start A = V H, V PP = V PPH CE# = V IL, OE# = V IH Erase 0 ms pulse (PGM# = V IL ) PGM# = V IH A = V IL or V IH A Recovery ime Device into Read mode Compare All bytes to FF No Yes Device Passed Device Failed MSW F0.0 FIGURE : ERASE ALGORIHM

13 Megabit SuperFlash MP SSSF00, SSVF00 Start Erase See Figure VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 0µs pulse (PGM# = VIL) Increment Address No Last Address? Yes Device into Read mode Yes Compare all bytes to original data No Device Passed Device Failed ILL F0. FIGURE : PROGRAMMING ALGORIHM

14 Megabit SuperFlash MP SSSF00, SSVF00 PRODUC ORDERING INFORMAION Device Speed Suffix Suffix SSXF00 - XXX - XX - XX Package Modifier H = leads Numeric = Die modifier Package ype P = PDIP N = PLCC E = SOP (die up) U = Unencapsulated die Operating emperature C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance = 00 cycles Read Access Speed 0 = 0 ns, 0 = 0 ns 00 = 00 ns, 0 = 0 ns Read Voltage S =.0 Volt Read V =. Volt Read (.-.V)

15 Megabit SuperFlash MP SSSF00, SSVF00 SF00 Valid combinations SSSF00-0-C-EH SSSF00-0-C-NH SSSF00-0-C-PH SSSF00-0-C-EH SSSF00-0-C-NH SSSF00-0-C-PH SSSF00-0-I-EH SSSF00-0-I-NH SSSF00-0-I-EH SSSF00-0-I-NH SSSF00-0-C-U VF00 Valid combinations SSVF00-00-C-EH SSVF00-00-C-NH SSVF00-00-C-PH SSVF00-0-C-EH SSVF00-0-C-NH SSVF00-0-C-PH SSVF00-00-I-EH SSVF00-00-I-NH SSVF00-0-C-U Example:Valid combinations are those products in mass production or will be in mass production. Consult your SS sales representative to confirm availability of valid combinations and to determine availability of new combinations.

16 PACKAGING DIAGRAMS Megabit SuperFlash MP SSSF00, SSVF00 pn SOP EH AC. Note:. Complies with JEDEC publication MO- BD dimensions, although some dimensions may be more stringent.. All linear dimensions are in metric (min/max).. Coplanarity: 0. (±.0) mm. -LEAD HIN SMALL OULINE PACKAGE (SOP) SS PACKAGE CODE: EH Note:. Complies with JEDEC publication MO-0 AP dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.0 inches. pn PDIP PH AC. -LEAD PLASIC DUAL-IN-LINE PACKAGE (PDIP) SS PACKAGE CODE: PH

17 Megabit SuperFlash MP SSSF00, SSVF00 Note:. Complies with JEDEC publication MS-0 AE dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches. -LEAD PLASIC LEAD CHIP CARRIER (PLCC) SS PACKAGE CODE: NH pn PLCC NH AC.

HN27C1024HG/HCC Series

HN27C1024HG/HCC Series 65536-word 16-bit CMOS UV Erasable and Programmable ROM Description The Hitachi HN27C1024H series is a 1-Mbit (64-kword 16-bit) ultraviolet erasable and electrically programmable ROM. Fabricated on new