DM74LS14 Hex Inverter with Schmitt Trigger Inputs

Transcription

1 DM74LS14 Hex Inverter with Schmitt Trigger Inputs General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. Ordering Code: August 1986 Revised March 2000 Order Number Package Number Package Description DM74LS14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow DM74LS14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Function Table Input A L H Y = A Output Y H L DM74LS14 Hex Inverter with Schmitt Trigger Inputs H = HIGH Logic Level L = LOW Logic Level 2000 Fairchild Semiconductor Corporation DS

2 DM74LS14 Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0 C to +70 C Storage Temperature Range 65 C to +150 C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter Min Nom Max Units V CC Supply Voltage V V T+ Positive-Going Input Threshold Voltage (Note 2) V V T Negative-Going Input Threshold Voltage (Note 2) V HYS Input Hysteresis (Note 2) V I OH HIGH Level Output Current 0.4 ma I OL LOW Level Output Current 8 ma T A Free Air Operating Temperature 0 70 C Note 2: V CC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Symbol Parameter Conditions Min (Note 3) Max Units V I Input Clamp Voltage V CC = Min, I I = 18 ma 1.5 V V OH HIGH Level V CC = Min, I OH = Max Output Voltage V IL = Max V V OL LOW Level V CC = Min, I OL = Max Output Voltage V IH = Min V V CC = Min, I OL = 4 ma I T+ Input Current at V CC = 5V, V I = V T ma Positive-Going Threshold I T Input Current at V CC = 5V, V I = V T 0.18 ma Negative-Going Threshold I I Input Max Input Voltage V CC = Max, V I = 7V 0.1 ma I IH HIGH Level Input Current V CC = Max, V I = 2.7V 20 µa I IL LOW Level Input Current V CC = Max, V I = 0.4V 0.4 ma I OS Short Circuit Output Current V CC = Max (Note 4) ma I CCH Supply Current with Outputs HIGH V CC = Max ma I CCL Supply Current with Outputs LOW V CC = Max ma Note 3: All typicals are at V CC = 5V, T A = 25 C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at V CC = 5V and T A = 25 C R L = 2 kω Symbol Parameter C L = 15 pf C L = 50 pf Units Min Max Min Max t PLH Propagation Delay Time LOW-to-HIGH Level Output ns t PHL Propagation Delay Time HIGH-to-LOW Level Output ns 2

3 Physical Dimensions inches (millimeters) unless otherwise noted DM74LS14 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow Package Number M14A 3

4 DM74LS14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 4

5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) DM74LS14 Hex Inverter with Schmitt Trigger Inputs 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

6 DM74LS32 Quad 2-Input OR Gate General Description This device contains four independent gates each of which performs the logic OR function. Ordering Code: June 1986 Revised March 2000 Order Number Package Number Package Description DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. DM74LS32 Quad 2-Input OR Gate Connection Diagram Function Table Y = A + B Inputs Output A B Y L L L L H H H L H H H H H = HIGH Logic Level L = LOW Logic Level 2000 Fairchild Semiconductor Corporation DS

7 DM74LS32 Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0 C to +70 C Storage Temperature Range 65 C to +150 C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter Min Nom Max Units V CC Supply Voltage V V IH HIGH Level Input Voltage 2 V V IL LOW Level Input Voltage 0.8 V I OH HIGH Level Output Current 0.4 ma I OL LOW Level Output Current 8 ma T A Free Air Operating Temperature 0 70 C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Symbol Parameter Conditions Min (Note 2) Max Units V I Input Clamp Voltage V CC = Min, I I = 18 ma 1.5 V V OH HIGH Level V CC = Min, I OH = Max Output Voltage V IH = Min V V OL LOW Level V CC = Min, I OL = Max Output Voltage V IL = Max V I OL = 4 ma, V CC = Min I I Input Max Input Voltage V CC = Max, V I = 7V 0.1 ma I IH HIGH Level Input Current V CC = Max, V I = 2.7V 20 µa I IL LOW Level Input Current V CC = Max, V I = 0.4V 0.36 ma I OS Short Circuit Output Current V CC = Max (Note 3) ma I CCH Supply Current with Outputs HIGH V CC = Max ma I CCL Supply Current with Outputs LOW V CC = Max ma Note 2: All typicals are at V CC = 5V, T A = 25 C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at V CC = 5V and T A = 25 C R L = 2 kω Symbol Parameter C L = 15 pf C L = 50 pf Units Min Max Min Max t PLH Propagation Delay Time LOW-to-HIGH Level Output ns t PHL Propagation Delay Time HIGH-to-LOW Level Output ns 2

8 Physical Dimensions inches (millimeters) unless otherwise noted DM74LS32 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow Package Number M14A 3

9 DM74LS32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 4

10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) DM74LS32 Quad 2-Input OR Gate 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

11 DM74LS181 4-Bit Arithmetic Logic Unit General Description The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. Ordering Code: Features October 1988 Revised April 2000 Provides 16 arithmetic operations: add, subtract, compare, double, plus twelve other arithmetic operations Provides all 16 logic operations of two variables: exclusive-or, compare, AND, NAND, OR, NOR, plus ten other logic operations Full lookahead for high speed arithmetic operation on long words DM74LS181 4-Bit Arithmetic Logic Unit Order Number Package Number Package Description DM74LS181N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, Wide Logic Symbols Connection Diagram Active High Operands Active Low Operands Pin Descriptions V CC = Pin 24 GND = Pin 12 Pin Names A0 A3 B0 B3 S0 S3 M C n F0 F3 A = B G P C n+4 Description Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output 2000 Fairchild Semiconductor Corporation DS

12 DM74LS181 Functional Description The DM74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0 S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table lists these operations When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the C n+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the SUBTRACT mode, P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (C n+4 ) signal to the Carry input (C n ) of the next unit. For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit. One carry lookahead package is required for each group of four DM74LS181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wired- AND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the C n+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol. Function Table Mode Select Active LOW Operands Active HIGH Operands Inputs & F n Outputs & F n Outputs Logic Arithmetic (Note 2) Logic Arithmetic (Note 2) S3 S2 S1 S0 (M = H) (M = L) (C n = L) (M = H) (M = L) (C n = H) L L L L A A minus 1 A A L L L H AB AB minus 1 A + B A + B L L H L A + B AB minus 1 A B A + B L L H H Logic 1 minus 1 Logic 0 minus 1 L H L L A + B A plus (A + B) AB A plus AB L H L H B AB plus (A + B) B (A + B) plus AB L H H L A B A minus B minus 1 A B A minus B minus 1 L H H H A + B A + B AB AB minus 1 H L L L A B A plus (A + B) A + B A plus AB H L L H A B A plus B A B A plus B H L H L B AB plus (A + B) B (A + B) plus AB H L H H A + B A + B AB AB minus 1 H H L L Logic 0 A plus A (Note 1) Logic 1 A plus A (Note 1) H H L H AB AB plus A A + B (A + B) plus A H H H L AB AB minus A A + B (A + B) plus A H H H H A A A A minus 1 Note 1: Each bit is shifted to the next most significant position. Note 2: Arithmetic operations expressed in 2s complement notation. 2

13 Logic Diagram DM74LS

14 DM74LS181 Absolute Maximum Ratings(Note 3) Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0 C to +70 C Storage Temperature Range 65 C to +150 C Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter Min Nom Max Units V CC Supply Voltage V V IH HIGH Level Input Voltage 2 V V IL LOW Level Input Voltage 0.8 V I OH HIGH Level Output Current 0.4 ma I OL LOW Level Output Current 8 ma T A Free Air Operating Temperature 0 70 C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Symbol Parameter Conditions Min (Note 4) Max Units V I Input Clamp Voltage V CC = Min, I I = 18 ma 1.5 V V OH HIGH Level V CC = Min, I OH = Max, Output Voltage V IL = Max 2.7 V V OL LOW Level V CC = Min, I OL = Max, Output Voltage V IH = Min V I OL = 4 ma, V CC = Min I I Input Max V CC = Max, V I = 7V M input 0.1 Input Voltage A n, B n 0.3 S n 0.4 ma C n 0.5 I IH HIGH Level V CC = Max, V I = 2.7V M input 20 Input Current A n, B n 60 S n 80 µa C n 100 I IL LOW Level V CC = Max, V I = 0.4V M input 0.4 Input Current A n, B n 1.2 S n 1.6 ma C n 2.0 I OS Short Circuit V CC = Max Output Current (Note 5) ma I CC Supply Current V CC = Max, B n, C n = GND S n, M, A n = 4.5V 37 ma Note 4: All typicals are at V CC = 5V, T A = 25 C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. 4

15 Switching Characteristics V CC = 5V, T A = 25 C C L = 15 pf Symbol Parameter Conditions Min Max t PLH Propagation Delay M = GND 27 t PHL C n to C n+4 20 t PLH Propagation Delay M = GND 26 t PHL C n to F 20 t PLH Propagation Delay M, S 1, S 2 = GND; 29 t PHL A or B to G (Sum) S 1, S 3 = 4.5V 23 t PLH Propagation Delay M, S 0, S 3 = GND; 32 t PHL A or B to G (Diff) S 1, S 2 = 4.5V 26 t PLH Propagation Delay M, S 1, S 2 = GND; 30 t PHL A or B to P (Sum) S 0, S 3 = 4.5V 30 t PLH Propagation Delay M, S 0, S 3 = GND; 30 t PHL A or B to P (Diff) S 1, S 2 = 4.5V 33 t PLH Propagation Delay M, S 1, S 2 = GND; 32 t PHL A i or B i to F i (Sum) S 0, S 3 = 4.5V 25 t PLH Propagation Delay M, S 0, S 3 = GND; 32 t PHL A i or B i to F i (Diff) S 1, S 2 = 4.5V 33 t PLH Propagation Delay M = 4.5V 33 t PHL A or B to F (Logic) 29 t PLH Propagation Delay M, S 1, S 2 = GND; 38 t PHL A or B to C n+4 (Sum) S 0, S 3 = 4.5V 38 t PLH Propagation Delay M, S 0, S 3 = GND; 41 t PHL A or B to C n+4 (Diff) S 1, S 2 = 4.5V 41 t PLH Propagation Delay M, S 0, S 3 = GND; 50 t PHL A or B to A = B S 1, S 2 = 4.5V; 62 R L = 2 kω to 5.0V Units ns ns ns ns ns ns ns ns ns ns ns ns DM74LS181 Sum Mode Test Table 1 Function Inputs S0 = S3 = 4.5V, S1 = S2 = M = 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND t PLH A i B i None Remaining C n F i t PHL A and B t PLH B i A i None Remaining C n F i t PHL A and B t PLH A B None None Remaining P t PHL A and B, C n t PLH B A None None Remaining P t PHL A and B, C n t PLH A None B Remaining Remaining G t PHL B A, C n t PLH B None A Remaining Remaining G t PHL B A, C n t PLH A None B Remaining Remaining C n+4 t PHL B A, C n t PLH B None A Remaining Remaining C n+4 t PHL B A, C n t PLH C n None None All All Any F t PHL A B or C n+4 5

16 DM74LS181 Diff Mode Test Table 2 Function Inputs S1 = S2 = 4.5V, S0 = S3 = M = 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND t PLH A None B Remaining Remaining F i t PHL A B, C n t PLH B A None Remaining Remaining F i t PHL A B, C n t PLH A None B None Remaining P t PHL A and B, C n t PLH B A None None Remaining P t PHL A and B, C n t PLH A B None None Remaining G t PHL A and B, C n t PLH B None A None Remaining G t PHL A and B, C n t PLH A None B Remaining Remaining A = B t PHL A B, C n t PLH B A None Remaining Remaining A = B t PHL A B, C n t PLH A B None None Remaining C n+4 t PHL A and B, C n t PLH B None A None Remaining C n+4 t PHL A and B, C n t PLH C n None None All None C n+4 t PHL A and B Logic Mode Test Table 3 Function Inputs S1 = S2 = M = 4.5V, S0 = S3 = 0V Input Other Input Other Data Inputs Output Symbol Under Same Bit Under Test Apply Apply Apply Apply Test 4.5V GND 4.5V GND t PLH A B None None Remaining Any F t PHL A and B, C n t PLH B A None None Remaining Any F t PHL A and B, C n 6

17 Physical Dimensions inches (millimeters) unless otherwise noted DM74LS181 4-Bit Arithmetic Logic Unit 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

18 UNIVERSAL 4-BIT SHIFT REGISTER The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) 16 1 J SUFFIX CERAMIC CASE NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package N SUFFIX PLASTIC CASE PIN NAMES LOADING (Note a) HIGH LOW PE Parallel Enable (Active LOW) Input 0.5 U.L U.L. P0 P3 Parallel Data Inputs 0.5 U.L U.L. J First Stage J (Active HIGH) Input 0.5 U.L U.L. K First Stage K (Active LOW) Input 0.5 U.L U.L. CP Clock (Active HIGH Going Edge) Input 0.5 U.L U.L. MR Master Reset (Active LOW) Input 0.5 U.L U.L. Q0 Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L. Q3 Complementary Last Stage Output (Note b) 10 U.L. 5 (2.5) U.L ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD D SUFFIX SOIC CASE 751B-03 Ceramic Plastic SOIC LOGIC SYMBOL NOTES: a. 1 TTL Unit Load (U.L.) = 40 µa HIGH/1.6 ma LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-366

19 SN54/74LS195A LOGIC DIAGRAM FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right (Q0 Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 Q1 Q2 Q3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 Q2) can be achieved by tying the Qn Outputs to the Pn 1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. MODE SELECT TRUTH TABLE INPUTS OUTPUTS OPERATING MODES MR PE J K Pn Q0 Q1 Q2 Q3 Q3 Asynchronous Reset L X X X X L L L L H Shift, Set First Stage H h h h X H q0 q1 q2 q2 Shift, Reset First H h I I X L q0 q1 q2 q2 Shift, Toggle First Stage H h h I X q0 q0 q1 q2 q2 Shift, Retain First Stage H h I h X q0 q0 q1 q2 q2 Parallel Load H I X X pn p0 p1 p2 p3 p3 L = LOW voltage levels H = HIGH voltage levels X = Don t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. p n (q n ) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-367

20 SN54/74LS195A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage V TA Operating Ambient Temperature Range C IOH Output Current High 54, ma IOL Output Current Low ma DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage V VCC = MIN, IIN = 18 ma VOH VOL Output HIGH Voltage Output LOW Voltage V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table 54, V IOL = 4.0 ma VCC = VCC MIN, VIN = VIL or VIH V IOL = 8.0 ma per Truth Table IIH Input HIGH Current 20 µa VCC = MAX, VIN = 2.7 V 0.1 ma VCC = MAX, VIN = 7.0 V IIL Input LOW Current 0.4 ma VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) ma VCC = MAX ICC Power Supply Current 21 ma VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions fmax Maximum Clock Frequency MHz tplh tphl tphl Propagation Delay, Clock to Output Propagation Delay, MR to Output AC SETUP REQUIREMENTS (TA = 25 C) ns ns Limits VCC = 5.0 V CL = 15 pf Symbol Parameter Min Typ Max Unit Test Conditions tw CP Clock Pulse Width 16 ns tw MR Pulse Width 12 ns ts PE Setup Time 25 ns ts Data Setup Time 15 ns VCC = 5.0 V trec Recovery Time 25 ns trel PE Release Time 10 ns th Data Hold Time 0 ns FAST AND LS TTL DATA 5-368

21 SN54/74LS195A DEFINITIONS OF TERMS SETUP TIME(ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Clock to Output Delays and Clock Pulse Width Figure 3. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0, P1, P2, P3) Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time Figure 4. Setup (ts) and Hold (th) Time for PE Input FAST AND LS TTL DATA 5-369

22 -A- Case 751B-03 D Suffix 16-Pin Plastic SO B- P -T- D G K C M R X 45 F J -A- Case N Suffix 16-Pin Plastic B F S C -T- L H G D K J M -A- Case J Suffix 16-Pin Ceramic Dual In-Line B- 1 8 C L -T- K E N F G J D M FAST AND LS TTL DATA 5-370

23 The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. Hysteresis at Inputs to Improve Noise Margins 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 3.0 ma 15 ma I OL Output Current Low 24 ma 20 1 PLASTIC N SUFFIX CASE SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device Package Shipping SN74LS240N 16 Pin DIP 1440 Units/Box SN74LS240DW 16 Pin 2500/Tape & Reel SN74LS244N 16 Pin DIP 1440 Units/Box SN74LS244DW 16 Pin 2500/Tape & Reel Semiconductor Components Industries, LLC, 1999 December, 1999 Rev. 6 1 Publication Order Number: SN74LS240/D

24 SN74LS240 SN74LS244 LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) V CC SN74LS240 2G 1Y1 2A4 1Y2 2A3 1Y3 2A Y4 2A G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A Y1 GND SN74LS244 V CC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A Y4 2A G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A Y1 GND SN74LS240 INPUTS OUTPUT 1G, 2G D L L H L H X H L (Z) TRUTH TABLES H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance SN74LS244 INPUTS OUTPUT 1G, 2G D L L H L H X L H (Z) 2

25 SN74LS240 SN74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions V IH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs V IL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs V T+ V T Hysteresis V V CC = MIN V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 18 ma V OH V OL Output HIGH Voltage Output LOW Voltage V V CC = MIN, I OH = 3.0 ma 2.0 V V CC = MIN, I OH = MAX V I OL = 12 ma V CC = V CC MIN, V IN =V IL or V IH V I OL = 24 ma per Truth Table I OZH Output Off Current HIGH 20 µa V CC = MAX, V OUT = 2.7 V I OZL Output Off Current LOW 20 µa V CC = MAX, V OUT = 0.4 V I IH Input HIGH Current 20 µa V CC = MAX, V IN = 2.7 V 0.1 ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.2 ma V CC = MAX, V IN = 0.4 V I OS Output Short Circuit Current (Note 1) ma V CC = MAX Power Supply Current Total, Output HIGH 27 Total, Output LOW LS I CC LS ma V CC = MAX Total at HIGH Z LS LS Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (T A = 25 C, V CC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit Test Conditions t PLH t PHL Propagation Delay, Data to Output LS ns t PLH t PHL Propagation Delay, Data to Output LS244 t PZH Output Enable Time to HIGH Level ns t PZL Output Enable Time to LOW Level ns ns C L = 45 pf, R L = 667 Ω t PLZ Output Disable Time from LOW Level ns C L = 5.0 pf, t PHZ Output Disable Time from HIGH Level ns R L = 667 Ω 3

26 SN74LS240 SN74LS244 AC WAVEFORMS V IN 1.3 V 1.3 V t PLH t PHL V CC V OUT 1.3 V 1.3 V R L Figure 1. SW1 TO OUTPUT UNDER TEST V IN 1.3 V 1.3 V t PHL t PLH 5 kω V OUT 1.3 V 1.3 V CL * SW2 Figure 2. V E V E V OUT 1.3 V 1.3 V t PZL t PLZ 1.3 V 1.3 V V OL 0.5 V Figure 3. SWITCH POSITIONS SYMBOL SW1 t PZH Open t PZL Closed t PLZ Closed t PHZ Closed SW2 Closed Open Closed Closed Figure 5. V E V E 1.3 V 1.3 V t PZH t PHZ V OUT 1.3 V V OH 1.3 V 0.5 V Figure

27 SN74LS240 SN74LS244 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE E T SEATING PLANE 20 1 G E A F N B K C D 20 PL 0.25 (0.010) M T A M L M J 20 PL 0.25 (0.010) M T B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E BSC 1.27 BSC F G BSC 2.54 BSC J K L BSC 7.62 BSC M N

28 SN74LS240 SN74LS244 D SUFFIX PLASTIC SOIC PACKAGE CASE 751D 05 ISSUE F D A H 10X 0.25 M B M E h X 45 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 20X B 0.25 M T A S 18X e B B S A A1 T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e 1.27 BSC H h L

29 LH5116/H CMOS 16K (2K 8) Static RAM FEATURES 2,048 8 bit organization Access time: 100 ns (MAX.) Power consumption: Operating: 220 mw (MAX.) Standby: 5.5 µw (MAX.) Single +5 V power supply Fully-static operation DESCRIPTION The LH5116/H are static RAMs organized as 2,048 8 bits. It is fabricated using silicon-gate CMOS process technology. It features high speed access in read mode using output enable (t OE ). PIN CONNECTIONS 24-PIN DIP 24-PIN SK-DIP 24-PIN SOP A 7 A Vcc A 8 TOP VIEW TTL compatible I/O Three-state outputs A 5 A 4 A A 9 WE OE Wide temperature range available LH5116H: -40 to +85 C A A A A 10 CE I/O 8 Packages: 24-pin, 600-mil DIP 24-pin, 300-mil SK-DIP 24-pin, 450-mil SOP I/O 1 I/O 2 I/O 3 GND I/O 7 I/O 6 I/O 5 I/O Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages 1

30 LH5116/H CMOS 16K (2K 8) Static RAM A 0 8 A 5 3 A 6 2 A 7 1 A 8 A 9 A ROW ADDRESS BUFFERS ROW DECODERS MEMORY CELL ARRAY (128 x128) V CC GND I/O 1 9 I/O 2 10 I/O 3 11 I/O 4 13 I/O 5 14 I/O 6 15 I/O 7 16 I/O 8 17 CE DATA CONTROL CE COLUMN I/O CIRCUIT COLUMN DECODERS COLUMN ADDRESS BUFFERS CE WE OE A 4 A 3 A 2 A Figure 2. LH5116/H Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A 0 - A 10 CE OE WE Address input Chip Enable input Output Enable input Write Enable input I/O 1 - I/O 8 V CC GND Data input/output Power supply Ground TRUTH TABLE CE OE WE MODE I/O 1 - I/O 8 SUPPLY CURRENT NOTE L X L Write D IN Operating (ICC) 1 L L H Read D OUT Operating (I CC ) H X X Deselect High-Z Standby (I SB ) 1 L H X Outputs disable High-Z Operating (I CC ) 1 NOTE: 1. X = H or L 2

31 CMOS 16K (2K 8) Static RAM LH5116/H ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage V CC -0.3 to +7.0 V 1 Input voltage V IN -0.3 to V CC V 1 Operating temperature Topr 0 to C -40 to Storage temperature Tstg -55 to +150 C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. Applied to the LH5116/D/NA 3. Applied to the LH5116H/HD/HN RECOMMENDED OPERATING CONDITIONS 1 PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage V CC V V IH 2.2 V CC V Input voltage V IL V NOTE: 1. T A = 0 to 70 C (LH5116/D/NA), T A = -40 to +85 C (LH5116H/HD/HN) DC CHARACTERISTICS 1 (VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Output LOW voltage V OL I OL = 2.1 ma 0.4 V Output HIGH voltage V OH I OH = -1.0 ma 2.4 V Input leakage current I LI V IN = 0 V to V CC µa Output leakage current I LO CE = V IH, V I/O = 0 V to V CC µa Operating current I CC1 Outputs open (OE = V CC ) ma 2 I CC2 Outputs open (OE = V IH ) ma 3 CE V Standby current I CC V 1.0 SB µa All other input pins = 0 V to V CC NOTES: 1. T A = 0 to 70 C (LH5116/D/NA), T A = -40 to +85 C (LH5116H/HD/HN) 2. CE = 0 V; all other input pins = 0 V to V CC 3. CE = V IL ; all other input pins = V IL to V IH 4. T A = 25 C AC CHARACTERISTICS 1 (1) READ CYCLE (V CC = 5 V ±10%) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Read cycle time t RC 100 ns Address access time t AA 100 ns Chip enable access time t ACE 100 ns Chip enable Low to output in Low-Z t CLZ 10 ns 2 Output enable access time t OE 40 ns Output enable Low to output in Low-Z t OLZ 10 ns 2 Chip disable to output in High-Z t CHZ 0 40 ns 2 Output disable to output in High-Z t OHZ 0 40 ns 2 Output hold time t OH 10 ns NOTES: 1. T A = 0 to 70 C (LH5116/NA/D). T A = -40 to 85 C (LH5116H/HD/HN). 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mv transition from steady state levels into the test load. 3

32 LH5116/H CMOS 16K (2K 8) Static RAM (2) WRITE CYCLE 1 (V CC = 5 V ±10%) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Write cycle time t WC 100 ns Chip enable to end of write t CW 80 ns Address valid time t AW 80 ns Address setup time t AS 0 ns Write pulse width t WP 60 ns Write recovery time t WR 10 ns Output active from end of write t OW 10 ns 2 WE Low to output in High-Z t WHZ 0 30 ns 2 Data valid to end of write t DW 30 ns Data hold time t DH 10 ns Output enable to output in High-Z t OHZ 0 40 ns 2 Output active from end of write t OW 10 ns 2 NOTES: 1. T A = 0 to +70 C (LH5116/D/NA), T A = -40 to +85 C (LH5116H/HD/HN) 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mv transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE NOTE Input voltage amplitude 0.8 V to 2.2 V Input rise/fall time 10 ns Timing reference level 1.5 V Output load condition 1TTL + C L (100 pf) 1 NOTE: 1. Includes scope and jig capacitance. DATA RETENTION CHARACTERISTICS 1 PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Data retention voltage V CCDR CE V CCRC V V Data retention current I CCDR CE V CCDR V, V CCDR = 2.0 V 1.0 µa Chip disable to data retention t CDR 0 ns Recovery time t R t RC ns 3 NOTES: 1. T A = 0 to +70 C (LH5116/D/NA), T A = -40 to +85 C (LH5116H/HD/HN) 2. T A = 25 C 3. t RC = Read cycle time CAPACITANCE 1 (f = 1 MHz, T A = 25 C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input capacitance C IN V IN = 0 V 7 pf Input/output capacitance C I/O V I/O = 0 V 10 pf NOTE: 1. This parameter is sampled and not production tested. 4

33 CMOS 16K (2K 8) Static RAM LH5116/H t CDR DATA RETENTION MODE t R V CC 4.5 V 2.2 V V CCDR CE 0 V CE V CCDR -0.2 V Figure 3. Low Voltage Data Retention t RC A 0 - A 10 t AA t OH t ACE CE t OE t CHZ OE t OLZ t OHZ t CLZ D OUT DATA VALID NOTE: WE = "HIGH" Figure 4. Read Cycle 5

34 LH5116/H CMOS 16K (2K 8) Static RAM t WC A 0 - A 10 t AW t WR (NOTE 3) t CW CE t AS t WP (NOTE 2) WE (NOTE 4) t WHZ tow (NOTE 5) D OUT t DW t DH (NOTE 6) D IN NOTES: OE = 'LOW' 1. WE must be HIGH when there is a change in A 0 - A When CE and WE are both LOW at the same time, write occurs during the period t WP. 3. t WR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. D OUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input signals of opposite logic level must not be applied Figure 5. Write Cycle 1 t WC A 0 - A 10 t AW (NOTE 3) t WR OE t CW CE t AS t WP (NOTE 2) WE t OLZ t OHZ t OW (NOTE 5) D OUT (NOTE 4) t DW t DH (NOTE 6) NOTES: D IN 1. WE must be HIGH when there is a change in A 0 - A When CE and WE are both LOW at the same time, write occurs during the period t WP. 3. t WR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. D OUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied Figure 6. Write Cycle 2 6

35 CMOS 16K (2K 8) Static RAM LH5116/H ACCESS TIME t AA, t ACE (RELATIVE VALUE) ACCESS TIME VS. SUPPLY VOLTAGE SUPPLY VOLTAGE V CC (V) ACCESS TIME t AA, t ACE (RELATIVE VALUE) ACCESS TIME VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE T A ( C) 25 AVERAGE SUPPLY CURRENT VS. SUPPLY VOLTAGE 25 AVERAGE SUPPLY CURRENT VS. AMBIENT TEMPERATURE AVERAGE SUPPLY CURRENT I CC (ma) INPUT VOLTAGE V IH, V IL (V) SUPPLY VOLTAGE V CC (V) INPUT VOLTAGE VS. SUPPLY VOLTAGE V IH V IL INPUT VOLTAGE V IH, V IL (V) AVERAGE SUPPLY CURRENT I CC (ma) AMBIENT TEMPERATURE T A ( C) INPUT VOLTAGE VS. AMBIENT TEMPERATURE V IH V IL SUPPLY VOLTAGE V CC (V) AMBIENT TEMPERATURE T A ( C) Figure 7. Electrical Characteristic Curves (VCC = 5 V, TA = 25 C unless otherwise specified) 7

36 LH5116/H CMOS 16K (2K 8) Static RAM PACKAGE DIAGRAMS 24DIP (DIP024-P-0600) DETAIL [1.232] [1.209] [0.530] [0.510] 0.30 [0.012] 0.20 [0.008] 0 TO [0.100] TYP [0.024] 0.40 [0.016] 4.45 [0.175] 4.05 [0.159] 0.51 [0.020] MIN 5.30 [0.209] 4.90 [0.193] 3.45 [0.136] 3.05 [0.120] [0.600] TYP. DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24DIP-2 24-pin, 600-mil DIP 24SDIP (SDIP024-P-0300) DETAIL [0.258] 6.15 [0.242] [0.876] [0.856] 0.30 [0.012] 0.20 [0.008] 0 TO [0.144] 3.25 [0.128] 7.62 [0.300] TYP [0.070] TYP [0.022] 0.36 [0.014] 0.51 [0.020] MIN 4.40 [0.173] 4.00 [0.157] 3.45 [0.136] 3.05 [0.120] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24SDIP 24-pin, 300-mil SK-DIP 8

37 CMOS 16K (2K 8) Static RAM LH5116/H 24SOP (SOP024-P-0450B) 0.50 [0.120] 0.30 [0.012] 1.27 [0.050] TYP [0.067] [0.346] 8.40 [0.331] [0.488] [0.457] [0.417] [0.614] [0.598] [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24SOP 24-pin, 450-mil SOP 9

38 LH5116/H CMOS 16K (2K 8) Static RAM ORDERING INFORMATION (T A = 0 C to 70 C) LH5116 Device Type X Package - ## Speed Access Time (ns) Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116N-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP) ORDERING INFORMATION (T A = -40 C to +85 C) LH5116H Device Type X Package - ## Speed Access Time (ns) Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116HN-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP)