In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Transcription

1 Imprtant ntice Dear Custmer, On 7 February 2017 the frmer NXP Standard Prduct business became a new cmpany with the tradename Nexperia. Nexperia is an industry leading supplier f Discrete, Lgic and PwerMOS semicnductrs with its fcus n the autmtive, industrial, cmputing, cnsumer and wearable applicatin markets In data sheets and applicatin ntes which still cntain NXP r Philips Semicnductrs references, use the references t Nexperia, as shwn belw. Instead f r use Instead f sales.addresses@ r sales.addresses@ use salesaddresses@nexperia.cm ( ) Replace the cpyright ntice at the bttm f each page r elsewhere in the dcument, depending n the versin, as shwn belw: - NXP N.V. (year). ll rights reserved r Kninklijke Philips Electrnics N.V. (year). ll rights reserved Shuld be replaced with: - Nexperia B.V. (year). ll rights reserved. If yu have any questins related t the data sheet, please cntact ur nearest sales ffice via r telephne (details via salesaddresses@nexperia.cm). Thank yu fr yur cperatin and understanding, Kind regards, Team Nexperia

2 Rev Nvember 2009 Prduct data sheet 1. General descriptin 2. Features 3. Ordering infrmatin The prvides ten bits f high-speed TTL-cmpatible bus switching. The lw ON resistance f the switch allws cnnectins t be made with minimal prpagatin delay. The device is rganized as tw 5-bit bus switches with tw separate utput enable (1OE, 2OE) inputs. When noe is LOW, the switch is n and prt is cnnected t the B prt. When noe is HIGH, each switch is disabled. The is characterized fr peratin frm 40 C t +5 C. 5 Ω switch cnnectin between tw prts TTL-cmpatible cntrl input levels Multiple package ptins See CBTD334 fr with level shifting dides Latch-up prtectin exceeds 100 m per JESD7 ESD prtectin: HBM JESD22-114E exceeds 2000 V CDM JESD22-C101C exceeds 1000 V Table 1. Ordering infrmatin Type number Package Temperature range Name Descriptin Versin D 40 C t +5 C SO24 plastic small utline package; 24 leads; bdy width 7.5 mm SOT137-1 DB 40 C t +5 C SSOP24 plastic shrink small utline package; 24 leads; SOT340-1 bdy width 5.3 mm DK 40 C t +5 C SSOP24 [1] plastic shrink small utline package; 24 leads; bdy width 3.9 mm; lead pitch mm SOT556-1 PW 40 C t +5 C TSSOP24 plastic thin shrink small utline package; 24 leads; bdy width 4.4 mm SOT355-1 [1] ls knwn as QSOP24 package

3 4. Functinal diagram B B5 1 1OE B OE 23 2B5 001aak77 Fig 1. Lgic diagram 5. Pinning infrmatin 5.1 Pinning 1OE 1 24 V CC 1OE 1 24 V CC 1B B5 1B B B B4 1B B4 1B B3 1B B B B2 1B B2 1B B1 1B B GND OE GND OE 001aak7 001aak79 Fig 2. Pin cnfiguratin fr SO24 (SOT137-1) Fig 3. Pin cnfiguratin fr SSOP24 (SOT340-1) and TSSOP24 (SOT355-1) _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

4 1OE 1 24 V CC 1B B B B4 1B B B B2 1B B GND OE 001aak0 Fig 4. Pin cnfiguratin fr SSOP24 (SOT556-1) 5.2 Pin descriptin Table 2. Pin descriptin Symbl Pin Descriptin 1OE, 2OE 1, 13 utput enable input (active LOW) 11 t 15 3, 4, 7,, 11 data input/utput ( prt) 21 t 25 14, 17, 1, 21, 22 data input/utput ( prt) 1B1 t 1B5 2, 5, 6, 9, 10 data input/utput (B prt) 2B1 t 2B5 15, 16, 19, 20, 23 data input/utput (B prt) GND 12 grund (0 V) V CC 24 psitive supply vltage 6. Functinal descriptin Table 3. Functin selectin [1] Input Input/utput 1OE 2OE 1n, 1Bn 2n, 2Bn L L 1n = 1Bn 2n = 2Bn L H 1n = 1Bn Z H L Z 2n = 2Bn H H Z Z [1] H = HIGH vltage level; L = LOW vltage level; Z = high-impedance OFF-state. _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

5 7. Limiting values Table 4. Limiting values In accrdance with the bslute Maximum Rating System (IEC 60134). [1] T amb = 40 C t +5 C, unless therwise specified. Symbl Parameter Cnditins Min Max Unit V CC supply vltage V V I input vltage [2] V I O utput current V O <0V - ±12 m I IK input clamping current V I/O =0V 50 - m T stg strage temperature C [1] Stresses beynd thse listed may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated under Sectin. is nt implied. Expsure t abslute-maximum-rated cnditins fr extended perids may affect device reliability. [2] The input and utput negative-vltage ratings may be exceeded if the input and utput clamp-current ratings are bserved.. Recmmended perating cnditins Table 5. Operating cnditins ll unused cntrl inputs f the device must be held at V CC r GND t ensure prper device peratin. Symbl Parameter Cnditins Min Typ Max Unit V CC supply vltage V V IH HIGH-state input vltage V V IL LOW-state input vltage V T amb ambient temperature perating in free air C 9. Static characteristics Table 6. Static characteristics Vltages are referenced t GND (grund = 0 V). Symbl Parameter Cnditins T amb = 40 C t +5 C Unit Min Typ [1] Max V IK input clamping vltage V CC = 4.5 V; I I = 1 m V I I input leakage current V CC = 5.5 V; V I = GND r 5.5 V - - ±1 µ I CC supply current V CC = 5.5 V; I O = 0 m; µ V I =V CC r GND I CC additinal supply current per input pin; V CC = 5.5 V; ne input at [2] m 3.4 V, ther inputs at V CC r GND V pass pass vltage utput HIGH; V I =V CC = 5.0 V; V I O = 100 µ C I input capacitance cntrl pins; V I = 3 V r 0 V pf C i(ff) ff-state input/utput capacitance prt ff; V I = 3 V r 0 V; noe = V CC pf _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

6 Table 6. Static characteristics cntinued Vltages are referenced t GND (grund = 0 V). Symbl Parameter Cnditins T amb = 40 C t +5 C Unit Min Typ [1] Max R ON ON resistance V CC = 4.5 V; V I =0V; I I =64m [3] Ω V CC = 4.5 V; V I =0V; I I =30m [3] Ω V CC = 4.5 V; V I = 2.4 V; I I = 15 m [3] Ω [1] ll typical values are at V CC =5V, T amb =25 C. [2] This is the increase in supply current fr each input that is at the specified TTL vltage level rather than V CC r GND. [3] Measured by the vltage drp between the nn and the nbn terminals at the indicated current thrugh the switch. ON resistance is determined by the lwest vltage f the tw (nn r nbn) terminals. 10. Dynamic characteristics Table 7. Dynamic characteristics Vltages are referenced t GND (grund = 0 V). Fr test circuit see Figure 7. Symbl Parameter Cnditins T amb = 25 C T amb = 40 C t +5 C Unit Min Typ Max Min Max t pd prpagatin delay nn, nbn t nbn, nn; see Figure 5 [1][2] V CC = 5.0 V ± 0.5 V ns t PZH t PZL t PHZ t PLZ OFF-state t HIGH prpagatin delay OFF-state t LOW prpagatin delay HIGH t OFF-state prpagatin delay LOW t OFF-state prpagatin delay noe t nn r nbn; see Figure 6 V CC = 5.0 V ± 0.5 V ns noe t nn r nbn; see Figure 6 V CC = 5.0 V ± 0.5 V ns noe t nn r nbn; see Figure 6 V CC = 5.0 V ± 0.5 V ns noe t nn r nbn; see Figure 6 V CC = 5.0 V ± 0.5 V ns [1] The prpagatin delay is the calculated RC time cnstant f the typical ON resistance f the switch and the specified lad capacitance, when driven by an ideal vltage surce (zer utput impedance). [2] t pd is the same as t PLH and t PHL. _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

7 11. Wavefrms V I nn, nbn input GND t PHL t PLH V OH nbn, nn utput V OL 001aak1 Fig 5. Measurement pints are given in Table. Lgic levels: V OL and V OH are typical utput vltage levels that ccur with the utput lad. The data input (nn, nbn) t utput (nbn, nn) prpagatin delay times V I noe input GND t PLZ t PZL 3.5 V utput LOW t OFF OFF t LOW V OL V X t PHZ t PZH V OH utput HIGH t OFF OFF t HIGH GND utputs enabled V Y utputs disabled utputs enabled 001aak29 Fig 6. Measurement pints are given in Table. Lgic levels: V OL and V OH are typical utput vltage levels that ccur with the utput lad. Enable and disable times Table. Measurement pints Supply vltage Input Output V CC V I V X V Y V CC = 5.0 V ± 0.5 V GND t 3.0 V 1.5 V 1.5 V V OL V V OH 0.3 V _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

8 12. Test infrmatin V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I psitive pulse 0 V 10 % 90 % t W V EXT V CC G V I DUT V O RL RT CL RL 001aae331 Fig 7. Test data is given in Table 9. ll input pulses are supplied by generatrs having the fllwing characteristics: PRR 10 MHz; Z =50Ω. The utputs are measured ne at a time with ne transitin per measurement. Definitins fr test circuit: R L = Lad resistance. C L = Lad capacitance including jig and prbe capacitance. R T = Terminatin resistance shuld be equal t utput impedance Z f the pulse generatr. V EXT = External vltage fr measuring switching times. Test circuit fr measuring switching times Table 9. Test data Supply vltage Input Lad V EXT V I t r, t f C L R L t PLH, t PHL t PLZ, t PZL t PHZ, t PZH V CC = 5.0 V ± 0.5 V GND t 3.0 V 2.5 ns 50 pf 500 Ω pen 7.0 V pen _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

9 13. Package utline SO24: plastic small utline package; 24 leads; bdy width 7.5 mm SOT137-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p 1 e b p 12 w M detail X mm scale DIMENSIONS (inch dimensins are derived frm the riginal mm dimensins) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Nte 1. Plastic r metal prtrusins f 0.15 mm (0.006 inch) maximum per side are nt included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E05 MS Fig. Package utline SOT137-1 (SO24) _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember 2009 f 14

10 SSOP24: plastic shrink small utline package; 24 leads; bdy width 5.3 mm SOT340-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 L L p 1 12 detail X e b p w M mm scale DIMENSIONS (mm are the riginal dimensins) UNIT b p c D (1) E (1) e H (1) E L L p Q v w y Z max. mm Nte 1. Plastic r metal prtrusins f 0.2 mm maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT340-1 MO-150 EUROPEN PROJECTION ISSUE DTE Fig 9. Package utline SOT340-1 (SSOP24) _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

11 SSOP24: plastic shrink small utline package; 24 leads; bdy width 3.9 mm; lead pitch mm SOT556-1 D E X c y H E v M Z ( ) 3 L p L 1 12 detail X e b p w M mm scale DIMENSIONS (millimetre dimensins are derived frm the riginal inch dimensins) UNIT b p c D (1) E (1) e H E L L p v w y Z max. (1) mm inches Nte 1. Plastic r metal prtrusins f 0.2 mm (0.00 inch) maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT556-1 MO Fig 10. Package utline SOT556-1 (SSOP24) _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

12 TSSOP24: plastic thin shrink small utline package; 24 leads; bdy width 4.4 mm SOT355-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) w M e b p L detail X L p mm scale DIMENSIONS (mm are the riginal dimensins) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm Ntes 1. Plastic r metal prtrusins f 0.15 mm maximum per side are nt included. 2. Plastic interlead prtrusins f mm maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT355-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 11. Package utline SOT355-1 (TSSOP24) _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

13 14. bbreviatins Table 10. crnym CDM DUT ESD FET HBM PRR TTL bbreviatins Descriptin Charged Device Mdel Device Under Test ElectrStatic Discharge Field Effect Transistr Human Bdy Mdel Pulse Rate Repetitin Transistr-Transistr Lgic 15. Revisin histry Table 11. Revisin histry Dcument ID Release date Data sheet status Change ntice Supersedes _ Prduct data sheet - _5 Mdificatins: The frmat f this data sheet has been redesigned t cmply with the new identity guidelines f NXP Semicnductrs. Legal texts have been adapted t the new cmpany name where apprpriate. Changed: Table 6 Static characteristics a. Pass vltage values have changed. b. Undersht static current prtectin remved. Changed: Table 7 Dynamic characteristics a. Enable and disable times values have changed. _ Prduct specificatin - _4 _ Prduct specificatin - _3 _ Prduct specificatin - _2 _ Prduct specificatin - - _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

14 16. Legal infrmatin 16.1 Data sheet status Dcument status [1][2] Prduct status [3] Definitin Objective [shrt] data sheet Develpment This dcument cntains data frm the bjective specificatin fr prduct develpment. Preliminary [shrt] data sheet Qualificatin This dcument cntains data frm the preliminary specificatin. Prduct [shrt] data sheet Prductin This dcument cntains the prduct specificatin. [1] Please cnsult the mst recently issued dcument befre initiating r cmpleting a design. [2] The term shrt data sheet is explained in sectin Definitins. [3] The prduct status f device(s) described in this dcument may have changed since this dcument was published and may differ in case f multiple devices. The latest prduct status infrmatin is available n the Internet at URL Definitins Draft The dcument is a draft versin nly. The cntent is still under internal review and subject t frmal apprval, which may result in mdificatins r additins. NXP Semicnductrs des nt give any representatins r warranties as t the accuracy r cmpleteness f infrmatin included herein and shall have n liability fr the cnsequences f use f such infrmatin. Shrt data sheet shrt data sheet is an extract frm a full data sheet with the same prduct type number(s) and title. shrt data sheet is intended fr quick reference nly and shuld nt be relied upn t cntain detailed and full infrmatin. Fr detailed and full infrmatin see the relevant full data sheet, which is available n request via the lcal NXP Semicnductrs sales ffice. In case f any incnsistency r cnflict with the shrt data sheet, the full data sheet shall prevail Disclaimers General Infrmatin in this dcument is believed t be accurate and reliable. Hwever, NXP Semicnductrs des nt give any representatins r warranties, expressed r implied, as t the accuracy r cmpleteness f such infrmatin and shall have n liability fr the cnsequences f use f such infrmatin. Right t make changes NXP Semicnductrs reserves the right t make changes t infrmatin published in this dcument, including withut limitatin specificatins and prduct descriptins, at any time and withut ntice. This dcument supersedes and replaces all infrmatin supplied prir t the publicatin heref. Suitability fr use NXP Semicnductrs prducts are nt designed, authrized r warranted t be suitable fr use in medical, military, aircraft, space r life supprt equipment, nr in applicatins where failure r malfunctin f an NXP Semicnductrs prduct can reasnably be expected t result in persnal injury, death r severe prperty r envirnmental damage. NXP Semicnductrs accepts n liability fr inclusin and/r use f NXP Semicnductrs prducts in such equipment r applicatins and therefre such inclusin and/r use is at the custmer s wn risk. pplicatins pplicatins that are described herein fr any f these prducts are fr illustrative purpses nly. NXP Semicnductrs makes n representatin r warranty that such applicatins will be suitable fr the specified use withut further testing r mdificatin. Limiting values Stress abve ne r mre limiting values (as defined in the bslute Maximum Ratings System f IEC 60134) may cause permanent damage t the device. Limiting values are stress ratings nly and peratin f the device at these r any ther cnditins abve thse given in the Characteristics sectins f this dcument is nt implied. Expsure t limiting values fr extended perids may affect device reliability. Terms and cnditins f sale NXP Semicnductrs prducts are sld subject t the general terms and cnditins f cmmercial sale, as published at including thse pertaining t warranty, intellectual prperty rights infringement and limitatin f liability, unless explicitly therwise agreed t in writing by NXP Semicnductrs. In case f any incnsistency r cnflict between infrmatin in this dcument and such terms and cnditins, the latter will prevail. N ffer t sell r license Nthing in this dcument may be interpreted r cnstrued as an ffer t sell prducts that is pen fr acceptance r the grant, cnveyance r implicatin f any license under any cpyrights, patents r ther industrial r intellectual prperty rights. Exprt cntrl This dcument as well as the item(s) described herein may be subject t exprt cntrl regulatins. Exprt might require a prir authrizatin frm natinal authrities Trademarks Ntice: ll referenced brands, prduct names, service names and trademarks are the prperty f their respective wners. 17. Cntact infrmatin Fr mre infrmatin, please visit: Fr sales ffice addresses, please send an t: salesaddresses@nxp.cm _6 NXP B.V ll rights reserved. Prduct data sheet Rev Nvember f 14

15 1. Cntents 1 General descriptin Features Ordering infrmatin Functinal diagram Pinning infrmatin Pinning Pin descriptin Functinal descriptin Limiting values Recmmended perating cnditins Static characteristics Dynamic characteristics Wavefrms Test infrmatin Package utline bbreviatins Revisin histry Legal infrmatin Data sheet status Definitins Disclaimers Trademarks Cntact infrmatin Cntents Please be aware that imprtant ntices cncerning this dcument and the prduct(s) described herein, have been included in sectin Legal infrmatin. NXP B.V ll rights reserved. Fr mre infrmatin, please visit: Fr sales ffice addresses, please send an t: salesaddresses@nxp.cm Date f release: 2 Nvember 2009 Dcument identifier: _6