10-bit level shifting bus switch with 5-bit output enables. The CBTD3384 is characterized for operation from 40 C to +85 C.

Transcription

1 Rev December 2012 Prduct data sheet 1. General descriptin The prvides ten bits f high-speed TTL-cmpatible bus switching. The lw ON resistance f the switch allws cnnectins t be made with minimal prpagatin delay. The device is rganized as tw 5-bit bus switches with tw separate utput enable (1OE, 2OE) inputs. When noe is LOW, the switch is n and prt is cnnected t the B prt. When noe is HIGH, each switch is disabled. The is characterized fr peratin frm 40 C t +85 C. 2. Features and benefits 3. Ordering infrmatin Designed t be used in 5 V t 3.3 V level shifting applicatins with internal dide 5 switch cnnectin between tw prts TTL-cmpatible cntrl input levels Multiple package ptins Latch-up prtectin exceeds 100 m per JESD78 ESD prtectin: HBM JESD22-114E exceeds 2000 V CDM JESD22-C101C exceeds 1000 V Table 1. Ordering infrmatin Type number Package Temperature range Name Descriptin Versin D 40 C t +85 C SO24 plastic small utline package; 24 leads; bdy width 7.5 mm SOT137-1 DB 40 C t +85 C SSOP24 plastic shrink small utline package; 24 leads; SOT340-1 bdy width 5.3 mm DK 40 C t +85 C SSOP24 [1] plastic shrink small utline package; 24 leads; SOT556-1 bdy width 3.9 mm; lead pitch mm PW 40 C t +85 C TSSOP24 plastic thin shrink small utline package; 24 leads; bdy width 4.4 mm SOT355-1 [1] ls knwn as QSOP24 package

2 4. Functinal diagram B B5 1 1OE B OE 23 2B5 001aak877 Fig 1. Lgic diagram 5. Pinning infrmatin 5.1 Pinning 1OE 1 24 V CC 1OE 1 24 V CC 1B B5 1B B B B4 1B B4 1B B3 1B B B B2 1B B2 1B B1 1B B GND OE GND OE 001aan aan061 Fig 2. Pin cnfiguratin fr SO24 (SOT137-1) Fig 3. Pin cnfiguratin fr SSOP24 (SOT340-1) and TSSOP24 (SOT355-1) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

3 1OE 1 24 V CC 1B B B B4 1B B B B2 1B B GND OE 001aan062 Fig 4. Pin cnfiguratin fr SSOP24 (SOT556-1) 5.2 Pin descriptin Table 2. Pin descriptin Symbl Pin Descriptin 1OE, 2OE 1, 13 utput enable input (active LOW) 11 t 15 3, 4, 7, 8, 11 data input/utput ( prt) 21 t 25 14, 17, 18, 21, 22 data input/utput ( prt) 1B1 t 1B5 2, 5, 6, 9, 10 data input/utput (B prt) 2B1 t 2B5 15, 16, 19, 20, 23 data input/utput (B prt) GND 12 grund (0 V) V CC 24 psitive supply vltage 6. Functinal descriptin Table 3. Functin selectin [1] Input Input/utput 1OE 2OE 1n, 1Bn 2n, 2Bn L L 1n = 1Bn 2n = 2Bn L H 1n = 1Bn Z H L Z 2n = 2Bn H H Z Z [1] H = HIGH vltage level; L = LOW vltage level; Z = high-impedance OFF-state. ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

4 7. Limiting values Table 4. Limiting values In accrdance with the bslute Maximum Rating System (IEC 60134). [1] T amb = 40 C t +85 C, unless therwise specified. Symbl Parameter Cnditins Min Max Unit V CC supply vltage V V I input vltage [2] V I O utput current V O <0V m I IK input clamping current V I/O =0V 50 - m T stg strage temperature C [1] Stresses beynd thse listed may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated under Sectin 8. is nt implied. Expsure t abslute-maximum-rated cnditins fr extended perids may affect device reliability. [2] The input and utput negative-vltage ratings may be exceeded if the input and utput clamp-current ratings are bserved. 8. Recmmended perating cnditins Table 5. Operating cnditins ll unused cntrl inputs f the device must be held at V CC r GND t ensure prper device peratin. Symbl Parameter Cnditins Min Typ Max Unit V CC supply vltage V V IH HIGH-level input vltage V V IL LOW-level input vltage V T amb ambient temperature perating in free air C 9. Static characteristics Table 6. Static characteristics Vltages are referenced t GND (grund = 0 V). Symbl Parameter Cnditins T amb = 40 C t +85 C Unit Min Typ [1] Max V IK input clamping vltage V CC =4.5V; I I = 18 m V I I input leakage current V CC =5.5V; V I = GND r 5.5 V I CC supply current V CC =5.5V; I O =0m; m V I =V CC r GND I CC additinal supply current per input pin; V CC = 5.5 V; ne input [2] m at 3.4 V, ther inputs at V CC r GND V pass pass vltage see Figure 5 t Figure V C I input capacitance cntrl pins; V I = 3 V r 0 V pf C i(ff) ff-state input/utput capacitance prt ff; V I = 3 V r 0 V; noe =V CC pf ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

5 Table 6. Static characteristics cntinued Vltages are referenced t GND (grund = 0 V). Symbl Parameter Cnditins T amb = 40 C t +85 C Unit R ON ON resistance V CC =4.5V; V I =0V; I I =64m [3] [1] ll typical values are at V CC =5V, T amb =25 C. V CC =4.5V; V I =0V; I I =30m [3] V CC =4.5V; V I =2.4V; I I = 15 m [3] [2] This is the increase in supply current fr each input that is at the specified TTL vltage level rather than V CC r GND. [3] Measured by the vltage drp between the nn and the nbn terminals at the indicated current thrugh the switch. ON resistance is determined by the lwest vltage f the tw (nn r nbn) terminals. 9.1 Typical pass vltage graphs Min Typ [1] Max aak aak835 V pass (V) 3.2 (1) V pass (V) 3.2 (1) 2.8 (2) (3) (4) 2.8 (2) (3) (4) Fig V CC (V) (1) I SW = 100 (2) I SW = 6 m (3) I SW =12 m (4) I SW = 24 m Pass vltage versus supply vltage; T amb =85 C (typical) Fig V CC (V) (1) I SW = 100 (2) I SW = 6 m (3) I SW =12 m (4) I SW = 24 m Pass vltage versus supply vltage; T amb =70 C (typical) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

6 aak aak837 V pass (V) 3.2 (1) V pass (V) 3.2 (1) 2.8 (2) (3) (4) 2.8 (2) (3) (4) Fig V CC (V) (1) I SW = 100 (2) I SW = 6 m (3) I SW =12 m (4) I SW = 24 m Pass vltage versus supply vltage; T amb =25 C (typical) Fig V CC (V) (1) I SW = 100 (2) I SW = 6 m (3) I SW =12 m (4) I SW = 24 m Pass vltage versus supply vltage; T amb =0 C (typical) aak838 V pass (V) 3.2 (1) (2) 2.8 (3) (4) V CC (V) (1) I SW = 100 (2) I SW = 6 m (3) I SW =12 m (4) I SW = 24 m Fig 9. Pass vltage versus supply vltage; T amb = 40 C (typical) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

7 10. Dynamic characteristics Table 7. Dynamic characteristics Vltages are referenced t GND (grund = 0 V). Fr test circuit see Figure 12. Symbl Parameter Cnditins T amb = 40 C t +85 C Unit Min Typ Max t pd prpagatin delay nn, nbn t nbn, nn; see Figure 10 [1][2] V CC = 5.0 V 0.5 V ns t en enable time noe t nn r nbn; see Figure 11 [2] V CC = 5.0 V 0.5 V ns t dis disable time noe t nn r nbn; see Figure 11 [2] [1] The prpagatin delay is the calculated RC time cnstant f the typical ON resistance f the switch and the specified lad capacitance, when driven by an ideal vltage surce (zer utput impedance). [2] t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. 11. Wavefrms V CC = 5.0 V 0.5 V ns V I nn, nbn, input GND t PHL t PLH V OH nbn, nn, utput V OL 001aan063 Fig 10. Measurement pints are given in Table 8. Lgic levels: V OL and V OH are typical utput vltage levels that ccur with the utput lad. The data input (nn, nbn) t utput (nbn, nn) prpagatin delay times ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

8 V I noe input GND t PLZ t PZL 3.5 V utput LOW t OFF OFF t LOW V OL V X t PHZ t PZH V OH utput HIGH t OFF OFF t HIGH GND utputs enabled V Y utputs disabled utputs enabled 001aak298 Fig 11. Measurement pints are given in Table 8. Lgic levels: V OL and V OH are typical utput vltage levels that ccur with the utput lad. Enable and disable times Table 8. Measurement pints Supply vltage Input Output V CC V I V X V Y V CC = 5.0 V 0.5 V GND t 3.0 V 1.5 V 1.5 V V OL V V OH 0.3 V ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

9 12. Test infrmatin V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I psitive pulse 0 V 10 % 90 % t W V EXT V CC G V I DUT V O RL RT CL RL 001aae331 Fig 12. Test data is given in Table 9. ll input pulses are supplied by generatrs having the fllwing characteristics: PRR 10 MHz; Z =50. The utputs are measured ne at a time with ne transitin per measurement. Definitins fr test circuit: R L = Lad resistance. C L = Lad capacitance including jig and prbe capacitance. R T = Terminatin resistance shuld be equal t utput impedance Z f the pulse generatr. V EXT = External vltage fr measuring switching times. Test circuit fr measuring switching times Table 9. Test data Supply vltage Input Lad V EXT V I t r, t f C L R L t PLH, t PHL t PLZ, t PZL t PHZ, t PZH V CC = 5.0 V 0.5 V GND t 3.0 V 2.5 ns 50 pf 500 pen 7.0 V pen ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

10 13. Package utline SO24: plastic small utline package; 24 leads; bdy width 7.5 mm SOT137-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L p L θ 1 e b p 12 w M detail X mm scale DIMENSIONS (inch dimensins are derived frm the riginal mm dimensins) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Nte 1. Plastic r metal prtrusins f 0.15 mm (0.006 inch) maximum per side are nt included θ OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E05 MS Fig 13. Package utline SOT137-1 (SO24) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

11 SSOP24: plastic shrink small utline package; 24 leads; bdy width 5.3 mm SOT340-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ L p L 1 12 detail X e b p w M mm scale DIMENSIONS (mm are the riginal dimensins) UNIT b p c D (1) E (1) e H (1) E L L p Q v w y Z max. mm θ 8 0 Nte 1. Plastic r metal prtrusins f 0.2 mm maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT340-1 MO-150 EUROPEN PROJECTION ISSUE DTE Fig 14. Package utline SOT340-1 (SSOP24) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

12 SSOP24: plastic shrink small utline package; 24 leads; bdy width 3.9 mm; lead pitch mm SOT556-1 D E X c y H E v M Z ( ) 3 θ L p L 1 12 detail X e b p w M mm scale DIMENSIONS (millimetre dimensins are derived frm the riginal inch dimensins) UNIT b p c D (1) E (1) e H E L L p v w y Z max. (1) mm inches θ Nte 1. Plastic r metal prtrusins f 0.2 mm (0.008 inch) maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT556-1 MO Fig 15. Package utline SOT556-1 (SSOP24) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

13 TSSOP24: plastic thin shrink small utline package; 24 leads; bdy width 4.4 mm SOT355-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ 1 12 w M e b p detail X L p L mm scale DIMENSIONS (mm are the riginal dimensins) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ 8 0 Ntes 1. Plastic r metal prtrusins f 0.15 mm maximum per side are nt included. 2. Plastic interlead prtrusins f 0.25 mm maximum per side are nt included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT355-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 16. Package utline SOT355-1 (TSSOP24) ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

14 14. bbreviatins Table 10. crnym CDM ESD HBM PRR TTL bbreviatins Descriptin Charged Device Mdel ElectrStatic Discharge Human Bdy Mdel Pulse Rate Repetitin Transistr-Transistr Lgic 15. Revisin histry Table 11. Revisin histry Dcument ID Release date Data sheet status Change ntice Supersedes v Prduct data sheet - CBT3384 v.7 Mdificatins: Table 1: changed +125 C int +85 C (errata). v Prduct data sheet - CBT3384 v.6 Mdificatins: Table 1: changed +85 C int +125 C (errata). v Prduct data sheet - v.5 Mdificatins: Legal pages updated. v Prduct data sheet - v.4 v Prduct specificatin v.3 v Prduct specificatin - v.2 v Prduct specificatin - - ll infrmatin prvided in this dcument is subject t legal disclaimers. NXP B.V ll rights reserved. Prduct data sheet Rev December f 17

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Limiting values Stress abve ne r mre limiting values (as defined in the bslute Maximum Ratings System f IEC 60134) will cause permanent damage t the device. Limiting values are stress ratings nly and (prper) peratin f the device at these r any ther cnditins abve thse given in the Recmmended perating cnditins sectin (if present) r the Characteristics sectins f this dcument is nt warranted. Cnstant r repeated expsure t limiting values will permanently and irreversibly affect the quality and reliability f the device. Terms and cnditins f cmmercial sale prducts are sld subject t the general terms and cnditins f cmmercial sale, as published at unless therwise agreed in a valid written individual agreement. In case an individual agreement is cncluded nly the terms and cnditins f the respective agreement shall apply. hereby expressly bjects t applying the custmer s general terms and cnditins with regard t the purchase f prducts by custmer. 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17 18. Cntents 1 General descriptin Features and benefits Ordering infrmatin Functinal diagram Pinning infrmatin Pinning Pin descriptin Functinal descriptin Limiting values Recmmended perating cnditins Static characteristics Typical pass vltage graphs Dynamic characteristics Wavefrms Test infrmatin Package utline bbreviatins Revisin histry Legal infrmatin Data sheet status Definitins Disclaimers Trademarks Cntact infrmatin Cntents Please be aware that imprtant ntices cncerning this dcument and the prduct(s) described herein, have been included in sectin Legal infrmatin. NXP B.V ll rights reserved. Fr mre infrmatin, please visit: Fr sales ffice addresses, please send an t: salesaddresses@nxp.cm Date f release: 12 December 2012 Dcument identifier: