ECE 598 JS Lecture 17 Jitter
|
|
- Mildred Snow
- 5 years ago
- Views:
Transcription
1 ECE 598 JS Lecture 17 Jitter Spring 2009 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois 1
2 Jitter Definition Jitter is difference in time of when something was ideally to occur and when it actually did occur. Some devices specify the amount of marginal jitter and total jitter that it can take to operate correctly. If the cable adds more jitter than the receiver s allowed marginal jitter and total jitter the signal will not be received correctly. In this case the jitter is measured as in the below diagram Timing uncertainties in digital transmission systems Utmost importance because timing uncertainties cause bit errors There are different types of jitter 2
3 Jitter Characteristics Jitter is a signal timing deviation referenced to a recovered clock from the recovered bit stream Measured in Unit Intervals and captured visually with eye diagrams Two types of jitter Deterministic (non Gaussian) Random The total jitter (TJ) is the sum of the random (RJ) and deterministic jitter(dj) 3
4 Types of Jitter Deterministic Jitter (DDJ) Data Dependent Jitter (DDJ) Periodic Jitter (PJ) Bounded Uncorrelated Jitter (BUJ) Random Jitter (RJ) Gaussian Jitter f α Higher Order Jitter 4
5 Jitter Effects Bandwidth Limitations Cause intersymbol interference (ISI) ISI occurs if time required by signal to completely charge is longer than bit interval Amount of ISI is function of channel and data content of signal Oscillator Phase Noise Present in reference clocks or high-speed clocks In PLL based clocks, phase noise can be amplified
6 Jitter Statistics Most common way to look at jitter is in statistical domain Because one can observe jitter histograms directly on oscilloscopes No instruments to measure jitter time waveform or frequency spectrum directly Jitter Histograms and Probability Density Functions (PDF) Built directly from time waveforms Frequency information is lost Peak to peak value depends on observation time 6
7 Gaussian Random Jitter Random jitter can be described by a Gaussian distribution with the following probability density function ( x μ ) σ PDFRJ ( x) = e σ 2π x σ μ : independent value : RMS value : mean of distribution (zero by definition) Note: the PDF of a Gaussian process is unbounded, i.e, its PDF is not zero unless the jitter Δt approaches infinity 7
8 Gaussian Jitter PDF P( Δ t μ σ) = ( ) P Δ t μ 2σ = ( ) P Δ t μ 3σ = Can be used to estimate the probability when the deviation of the random jitter variable Δt is within a multiple of its σ value. 8
9 Cummulative Density Function Cummulative density function (CDF) is defined as: t CDF() t = PDF( x) dx CDF(t) tells us the probability that the transition occurred earlier than t. For random jitter, we get: 1 1 x CDFRJ ( x) = + erf 2 2 σ 2 erf is the error function 9
10 PDF and CDF of Random Jitter PDF CDF 10
11 Causes of Deterministic Jitter Crosstalk Noisy neighboring signals Interference Reflections Imperfect terminations Discontinuities (e.g. multidrop buses, stubs) Simultaneous switching noise (SSN) Noisy reference plane or power rail Shift in threshold voltages 11
12 Data-Dependent Jitter Most commonly encountered DJ type Dominant limiting factor for link channels Due to memory of lossy electrical or optical system Bit transition of current bitd epends on the transition times of the previous bits 12
13 Data-Dependent Jitter DDJ depends on the impulse response of the system that generates the pattern DDJ depends on the input pattern DDJ is a distribution with its sample size equal to the number of transitions of the data patent Duty cycle distortion (DCD) occurs for clock patterns of repeating bits 13
14 Data-Dependent Jitter Since channel does not have zero-rise time step response or infinite bandwidth, jitter is to be expected Settling time gives good indication of 14
15 Model for DDJ The generic form for DDJ PDF is: N DDJ DDJ ( Δ ) = i δ Δ i i= 1 ( DDJ ) f t P t D DDJ Pi is the probability for the DDJ value of DDJ D i DDJ P i satisfies the condition N i= 1 P DDJ i = 1 15
16 Periodic Jitter Periodic jitter is a repeating jitter signal at a certain period or frequency. It is described by: Δ t = Acos( ωt+ φ ω : angular frequency o ) φ o : initial phase The PDF for the single PJ is given by 1 fpj ( Δ t) =, A Δt A π 1 Δ / ( t A) 2 Which can be approximated by 1 fpj t t A t A 2 ( Δ ) δ( Δ ) + δ( Δ + ) 16
17 Periodic Jitter PDF for single sinusoidal 1 fpj ( Δ t) =, A Δt A π 1 Δ / ( t A) 2 17
18 Periodic Jitter There are 3 common waveforms for the theoretical analysis of periodic jitter Rectangle Periodic Jitter 1 m 1 m PDFPJ rect ( x) = δ + δ Triangle Periodic Jitter 1 m for x < PDFPJ triang ( x) = m 2 0 otherwise 18
19 Periodic Jitter Sinusoidal Periodic Jitter 1 for x 2 2 PDFPJ line( x) = π m/2 x m 0 otherwise < m 2 19
20 Rectangular Periodic Jitter PDF CDF 20
21 Triangular Periodic Jitter PDF CDF 21
22 Sinusoidal Periodic Jitter PDF CDF 22
23 Phase Noise & Phase Jitter Phase noise in clock oscillators Phase offset term that continually changes timing of signal ( ) St () = Pt+φ() t signal waveform with phase noise undistorted signal phase noise Example: ( 9 P() t = sin π t) 1 ( 9 φ() t = sin π t) St ( ) = sin π t+ 0.25sin( πt) ( ) 23
24 Phase Noise clean signal noisy signal 2 GHz phase noise 24
25 Phase Jitter Phase jitter in digital systems Variability in timing of transition in digital systems is called phase jitter Phase jitter is digital equivalent of phase noise Always defined relative to the ideal position of the transitions t n T n φ n For a jittered digital signal tn = Tn φn is the actual time of the nth transition is the ideal timing value of the nth transition is the time offset of the transition phase jitter term Example: 10 Gbits/s T n has bit intervals of 100 ps. Transitions take place at 0, 100, 200 ps 25
26 Phase Jitter clean signal noisy signal 26
27 Cycle-to-Cycle Jitter Phase jitter causes bit periods to contract and expand Actual bit periods are given by the time difference between 2 consecutive transitions ( φ ) ( φ ) P = t t = T T Ideal bit period: Period jitter: n n+ 1 n n+ 1 n+ 1 n n TB = T T n n+ 1 n PerJ n = TBn Pn ( ) ( ) PerJ = T T T T + φ φ = φ φ n n+ 1 n n+ 1 n n n+ 1 n+ 1 n 27
28 Cycle-to-cycle jitter: CCJit = P P n n+ 1 n Cycle-to-Cycle Jitter CCJit = PerJ PerJ n n+ 1 n 28
29 Bounded Uncorrelated Jitter BUJ is primarily due to crosstalk The PDF for BUJ is given by f PJ 2 pbuj Δ = 2πσBUJ 0 for Δt A ( t) t 2 2σ BUJ e for Δt ABUJ BUJ 29
30 Mix of Random and Periodic Jitters Gaussian RJ and Rectangle PJ Obtain convolution of 2 PDFs + m m RJ* PJrect = RJ( t τ ) δ + δ dτ = e + e 2σ 2π ( t m/2 ) ( t+ m/2) σ 2σ Result is the sum of 2 Gaussian distributions with equal RMS value offset by the PJ peak to peak value. It is called the DUAL DIRAC DISTRIBUTION 30
31 Jitter Mixing Problem In tests, we have measured jitter histograms and need to extract the individual jitter components Ideally, we could use deconvolution into components. However without prior knowledge of deterministic jitter, it is not possible Use dual Dirac distribution model which would yield the worst case deterministic jitter 31
32 Total Jitter Time Waveform TJ(t) = PJ(t) + RJ(t) The total jitter waveform is the sum of individual components 32
33 Jitter Statistics TJ(x) = PJ(x) * RJ(x) The total jitter PDF is the convolution of individual components 33
34 Jitter Mechanisms Transfer of Level Noise into the Time Domain Noise on digital data signals causes jitter because it offsets the threshold crossing point in time Bandwidth Limitations Primarily caused by intersymbol interference Oscillator Phase Noise Phase noise prsent in reference clocks especially in systems based on PLL 34
35 Jitter Mechanisms Jitter Mechanisms Transfer of noise into time domain Bandwidth limitation in channels Oscillator phase noise V NJ = t Noise pk pk t V V H L t t V Noise V H V L rise time pk-pk noise amplitude Hi signal level Lo signal level 35
36 Jitter Mechanisms Transfer of voltage noise into time domain Linear model Random noise caused by thermal effects 36
37 Jitter Mechanisms Transfer of voltage noise into time domain First order model Periodic noise: switching power, crosstalk, etc 37
38 Jitter Mechanisms Multiple threshold crossing of a signal with high-frequency level noise 38
39 Bandwidth Limitations data pattern 39
40 Bandwidth Limitations data pattern 40
41 Q-Scale Transformation Q-scale is defined such that the Gaussian distribution mapped onto the Q-scale is a straight line Use CDF CDF( x) 1 1 x = + erf 2 2 σ 2 Qx ( ) = 2erf 2 CDFx ( ) 1 = 1 ( ) x σ A Gaussian CDF is a straight line in the Q scale with slope 1/σ. DJ is given by distance d 41
42 Q-Scale Transformation Gaussian RJ σ = 0.5 PDF CDF 42
43 Q-Scale Transformation Gaussian RJ σ = 0.25 PDF CDF 43
44 Q-Scale - Generalization Qx ( ) = 2erf 2 CDFx ( ) 1 = 1 ( ) x σ Mixed Gaussian RJ and PJ σ = 0.1 PDF CDF 44
45 Q-Scale - Generalization Qx ( ) = 2erf 2 CDFx ( ) 1 = 1 ( ) x σ Mixed Gaussian RJ and PJ σ = 0.25 PDF CDF 45
46 Dual Dirac Model Mixed Gaussian RJ and Triangular PJ 46
47 Jitter Classification 47
48 Measuring Jitter 48
49 Eye Diagrams Eye diagrams are a time domain display of digital data triggered on a particular cycle of the clock. Each period is repeated and superimposed. Each possible bit sequence should be generated so that a complete eye diagram can be made
50 Eye Diagram
51 High-Speed Oscilloscope 8-bit flash ADCs provide 256 discrete levels along vertical axis 51
52 Interleaving Architecture 52
53 High-Speed Scope Digitizers SiGe Based Technologies Fastest ADCs run at Gsamples/s Typically 8 16 digitizers CMOS Designs ADCs sample at lower rate 80 digitizers or more 53
54 Timing Diagram 54
55 Sampling Procedure Once waveform samples have been reassembled into a representation of the waveform, they are stored to digital memory The maximum number of samples is the record length Record length are typically in excess of 100 million samples 55
56 Frequency Interleaving 56
57 Nyquist Criterion A signal of bandwidth B that has been sampled at regular intervals T can be exactly recovered if the sampling rate satisfies FN 1 = > T 2* B F N : Nyquist rate T B : sampling interval : bandwidth 57
58 High-Speed Oscilloscopes Oscilloscopes use DSP techniques to: Extend their analog bandwidth Flatten their amplitude Practice has benefits However, limitations should be understood 58
59 Scope Channel Equalization 59
60 Edge Triggering T OFF is recorded with high resolution but is subject to noise 60
61 Trigger Jitter Trigger jitter is the amount of effective timing instability between the trigger path and the signal capture path In eye diagram construction, multiple waveform acquisitions are overlayed. Trigger jitter is then an externally introduced noise that cannot be distinguished from the true jitter Typical value: ~ 1 ps RMS 61
62 Trigger Jitter 62
63 Sample Jitter Much of the timing instability in an oscilloscope is a combination of phase noise in the instrument s time base and aperture jitter in the track-and-hold circuits They exhibit a Gaussian probability distribution Interleaving errors from the digitizers are another large source of errors. They are deterministic and are manifested as deterministic jitter can be calibrated out 63
64 Oscillator Phase Noise 64
65 Sample Jitter Gaussian Errors Phase noise Aperture jitter in track and hold circuits Deterministic Errors Interleaving mismatches Can be calibrated out 65
66 Eye Diagram An eye diagram is a time-folded representation of a signal that carries digital information Eye is horizontally centered on the ideal sampling instant 66
67 Eye Diagram Unit interval (UI) of a bit sequence is typically independent of the waveform sampling interval of the measurement instrument. Waveform sampling interval must be no more than one half the unit interval to avoid aliasing Rule of thumb for eye diagrams is to sample 5 to 10 times the bit rate For 2.5 Gb/s, the sampling rate should be 20 GSamples/s Large eye openings ensure that the receiving device can reliably decide between high and low logic states even when the decision threshold fluctuates or the decision time instant varies. 67
68 Eye Diagram Construction Eye diagram construction in real-time oscilloscope is based on hardware clock recovery and trigger circuitry 68
69 Eye Diagram Construction 69
70 Eye Diagram Construction 1. Capture of the Waveform Record 2. Determine the Edge Times 70
71 Eye Diagram Construction 3. Determine the Bit Labels 71
72 Eye Diagram Construction 4. Clock Recovery 72
73 Eye Diagram Construction 5. Slice Overlay 6. Display 73
74 Eye Diagram Measurements 74
75 Eye Diagram Measurements 75
76 Reference Levels 76
77 Eye Height Eye Height is the measuremnt of the eye height in volts ( 3 ) ( 3 ) PTop PTop PBase PBase Eye Height = μ σ μ + σ μ PTop : mean value of eye top σ PTop μ PBase σ PBase : standard deviation of eye top : mean value of eye base : standard deviation of eye base 77
78 Eye Width Eye Width is the measuremnt of the eye width in seconds Eye Width = μ 3σ μ + 3σ ( ) ( ) TCross2 TCross2 TCross1 TCross1 Crossing percent measurement is the eye crossing point expressed as a percentage of the eye height ( μ μ ) PCross1 PBase Crossing Percent = 100% ( μ μ ) PTop PBase 78
79 Jitter Measurements Jitter peak-to-peak is the peak-to-peak value for the edge jitter in the current horizontal units ( TCross ) ( TCross ) Jitter pp = max 1 min 1 Jitter root mean square is the RMS value of the edge jitter in the current horizontal units Jitter RMS = σ TCross1 Jitter 6σ represents the same measurement reporting the 6σ TCross1 value 79
80 Noise Measurements Noise peak-to-peak is the peak-to-peak value of the noise at the top or base of the signal as specified by the user Noise pp ( ) ( ) max PTop min PTop, or = max ( PBase) min ( PBase) Noise root mean square is the RMS value of the noise at the top or base of the signal Noise RMS = σ σ PTop or PBase 80
81 Noise Measurements Signal-to-noise ratio is the ratio of the signal amplitude to the noise at either the top or the base of the signal S/N Ratio = ( μ μ ) PTop PBase ( σ σ ) PTop PBase Duty cycle distortion is the peak-to-peak time variation of the first eye crossing measured at the mid-voltage reference as a percent of the eye period TDCD DCD = p-p 100% ( μ μ ) TCross2 TCross1 81
82 Eye Quality Factor Quality factor is the ratio of the eye size to noise Quality Factor = ( μ μ ) PTop PBase ( σ + σ ) PTop PBase 82
83 Eye Diagram Specifications PCI Express 2.0 eye diagram specification for full and deemphasized signals 83
84 Margin Testing Eye diagram with low margin 84
85 Eye Pattern Analysis Fiber Pseudorandom sequence generator Data Transmitter Receiver Clk Scope Trig Vert 85
86 Eye Diagram Typical Eye Diagrams
87 Jitter Mixing Problem In tests, we have measured jitter histograms and need to extract the individual jitter components Ideally, we could use deconvolution into components. However without prior knowledge of deterministic jitter, it is not possible Use dual Dirac distribution model which would yield the worst case deterministic jitter 87
88 Random Jitter Extraction Spectrum Analysis Extract random jitter by using the assumption that it has a piecewise linear spectrum Impulses are attributed to DJ Noise floor is due to RJ 88 88
89 Extracting Random Jitter Time domain Statistical domain Spectral domain Total jitter Random jitter 89
90 Jitter Spectrum Time record: 10N Time record: N A longer FFT yields a spectrum with greater frequency resolution and lower noise floor. 90
91 Random Jitter Extraction Tail-Fit Extract random jitter under the assumption that its probability density function follows a Gaussian distribution Make use of the Dual-Dirac Model 91
92 Dual Dirac Model Unknowns - gap between 2 impulses - σ for Gaussian distribution Equal Amplitudes Two unknown variables Linear Problem Explicit solution 92
93 Dual Dirac Model Unknowns - gap between 2 impulses - σ for Gaussian distribution - ratio of 2 impulse amplitudes Unequal Amplitudes Three unknown variables Nonlinear Problem No explicit solution 93
94 Dual Dirac Model Assume Gaussian RJ and Rectangle PJ Obtain convolution of 2 PDFs + m m RJ* PJrect = RJ( t τ ) δ + δ dτ = e + e 2σ 2π ( t m/2 ) ( t+ m/2) σ 2σ Result is the sum of 2 Gaussian distributions with equal RMS value offset by the PJ peak to peak value. It is called the DUAL DIRAC DISTRIBUTION 94
95 DDJ and DC D DDJ and DCD are correlated to the data pattern F R = Gbits/s N=40 bits For N bits, transmitted at rate F R, the jitter components due to DDJ and DCD will appear in the spectrum at multiple of F R /N 95
96 Pattern-Correlation-Based Approaches Most of the DDJ and DCD on a given data edge is caused by prior waveform edges. The number of relevant prior edges is determined by the speed of the system s response. If response to an edge fully settles within M unit intervals, only M preceding edges need to be analyzed to characterize DJ This analysis method is uniquely possible with realtime instruments For M bits, there are 2 M bit patterns 96
97 Pattern Correlation 97
98 Pattern Correlation The phase errors from all occurrences of each M-bit pattern are averaged together to estimate the phase error due to that M-bit pattern 98
99 Extracting DDJ DDJ Dominant DDJ & RJ RJ Dominant Spectral domain Eye 99
100 Periodic Jitter Time domain Statistical domain Spectral domain PJ PJ subcomponent 100
101 Clock Jitter In a computer system, the clock is used to provide timing or synchronization for the system. In a communication system, the clock is used to specify when a data switch or bit transaction should be transmitted and received In a synchronized system, a central global clock is distributed to its subsystem Clock jitter is the single most important degrader of clock performance 101
102 Definition Most of the definitions of data jitter (DJ, Rj, ) apply to clock jitter ISI does not apply to clock jitter 102
103 Clock Jitter Clock jitter analysis is subject to fewer sampling constraints compared to data signal jitter; therefore, more direct and versatile methods are possible for clock jitter analysis. 103
104 Synchronized System - Initial clock pulse causes A to latch data from input and launch it into channel - Second clock causes B to latch the incoming data 104
105 Timing Parameters 105
106 Timing Conditions The minimum conditions are that both setup time and hold time margin should be larger than 0 T T + T + T + T 0 c _ jitt c _ skew d _ pd su T T + T T hd d _ pd c _ skew c _ jitt These give a quantitative description of how clock jitter and clock skew affect the performance of the synchronized system in which a common or global clock for both driver and receiver is used 106
107 Skew Impact T c_jitter =0, T c_skew >0 The minimum clock period increases. The maximum hold time increases hold time condition easier to meet T c_jitter =0, T c_skew <0 The minimum clock period decreases. The maximum hold time decreases hold time condition harder to meet (race condition) 107
108 Jitter Impact T c_skew =0, T c_jitter >0 (longer cycle) The minimum clock period increases. The maximum hold time decreases hold time condition harder to meet T c_skew =0, T c_jitter <0 (shorter cycle) The minimum clock period decreases. The maximum hold time increases hold time condition easier to meet 108
109 System Performance 1. Positive jitter over one clock period makes both clock period and hold time hard to meet 2. A longer cycle does more harm to system performance 3. When both skew and jitter are present, system performance can be any of the four scenarios just discussed 109
110 Asynchronized System The skew of a synchronized system becomes hard to manage when the data rate increases(~1 Gb/s). At multiple Gb/s data rates, an asynchronized system is commonly used. 110
111 Clock Types Synchronized System Global clock is used to update and determine bits Asynchronized System Only data is sent Clock is embedded in data Clock recovery unit (CRU) recovers clock at receiver 111
112 Asysnchronized Link DJ = DJ + DJ clk _ tot clk _ tx clk _ rx σ = σ + σ clk _ tot clk _ tx clk _ rx Low-frequency jitter from the transmitter clock can be tracked or attenuated by the clock recovery function if it has a high enough corner frequency. A low phase noise oscillator within a PLL clock recovery also provides smaller random jitter generations. 112
113 t n Phase Jitter : timing for nth edge for jittery clock T n : timing for nth edge for ideal clock T o : ideal clock period Δ t = t T T n n n n = nt o 113
114 Phase Jitter Phase jitter captures the instance timing deviation from the ideal for each transition. Jitter measured with phase jitter is absolute and accumulates over time. In frequency domain φ n = t n T o 2π 114
115 Period Jitter Period jitter is defined as the period deviation from the ideal period. ( ) Δ t = t t T pn n n 1 o using previous relations Δ =Δ Δ tpn tn tn 1 in terms of phase units φ = Φ Φ ' n n n 1 Period jitter and phase jitter are not independent we can derive one from the other. 115
116 Phase, Period and CTC Jitter 116
117 Phase Jitter in Time Domain If the phase varies, the waveform V(t) shifts back and forth along the time axis and this creates phase jitter 117
118 Phase Jitter in Spectral Domain Phase noise appears as sidebands centered around the carrier frequency 118
119 Phase Jitter Phase noise magnitude is specified relative to the carrier s power on a per-hertz basis P ( ) n f P o Δf Pn ( ) ( f L f = ) PΔf o : phase noise power (in watts) : carrier s power (in watts) : phase noise bandwidth (in hertz) 1 L( f) = SΦ ( f) or 2 S Φ ( f) : PSD of phase noise Φ = 10 L( f) 10log S ( f) 2 119
120 Phase Noise to Phase Jitter Need: convert phase noise measured in the frequency domain to phase jitter for PLLs, clocks and oscillators From the phase noise PSD, random jitter and deterministic jitter can be identified 120
121 Phase Lock Loop Phase noise or jitter is the key metric for evaluating the performance of a PLL system 121
122 Jitter in PLLs External Source Reference clock input Internal Source Voltage controlled oscillator (VCO) 122
123 Time Domain PLL Analysis When PLL is a first order system, it can be modeled by a closed form solution It is not straightforward to model jitter/noise process with loop components in the time domain 123
124 Frequency- Domain PLL Analysis H The error transfer function is: o θo() s KdKoF() s () s = = θ () s s + K K F() s i d o θe() s He() s = = 1 Ho() s θ () s i 124
125 PLL Transfer Function 125
126 PLL Frequency Response Large peaking causes PLL to be unstable Larger 3dB frequency faster PLL tracking Larger peaking jitter amplification bit error For PLL stability, Barkhausen condition must be satisfied KK d o Fs () s = 1 Fs () Arg KdKo = 180 s 126
127 PLL Frequency Response 127
128 Pole and Zero Location 128
129 Tracking Time and Frequencies 129
130 Transmitter Architecture 130
131 Receiver Architecture 131
132 Channel or Medium 132
133 Probe Further Course web site May 09 issue of IEEE Transactions on Advanced Packaging D. Derickson and M. Muller, Digital Communications Test and Measurement, Prentice Hall, M. P. Li, Jitter, Noise and Signal Integrity at High Speed, Prentice Hall,
ECE 546 Lecture 23 Jitter Basics
ECE 546 Lecture 23 Jitter Basics Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Probe Further D. Derickson and M.
More informationStatistical and System Transfer Function Based Method For Jitter and Noise Estimation In Communication Design and Test
Statistical and System Transfer Function Based Method For Jitter and Noise Estimation In Communication Design and Test Mike Li and Jan Wilstrup Wavecrest Purposes Illustrate the shortfalls of simple parametric
More informationMeasuring Deterministic Jitter with a K28.5 Pattern and an Oscilloscope
Application Note: HFAN-4.5.0 Rev1; 04/08 Measuring Deterministic Jitter with a K28.5 Pattern and an Oscilloscope [A version of this application note has been published in the July, 2002 issue of Communications
More informationEE290C Spring Motivation. Lecture 6: Link Performance Analysis. Elad Alon Dept. of EECS. Does eqn. above predict everything? EE290C Lecture 5 2
EE29C Spring 2 Lecture 6: Link Performance Analysis Elad Alon Dept. of EECS Motivation V in, ampl Voff BER = 2 erfc 2σ noise Does eqn. above predict everything? EE29C Lecture 5 2 Traditional Approach Borrowed
More informationJitter Decomposition in Ring Oscillators
Jitter Decomposition in Ring Oscillators Qingqi Dou Jacob A. Abraham Computer Engineering Research Center Computer Engineering Research Center The University of Texas at Austin The University of Texas
More informationEE5713 : Advanced Digital Communications
EE5713 : Advanced Digital Communications Week 12, 13: Inter Symbol Interference (ISI) Nyquist Criteria for ISI Pulse Shaping and Raised-Cosine Filter Eye Pattern Equalization (On Board) 20-May-15 Muhammad
More informationVoltage-Controlled Oscillator (VCO)
Voltage-Controlled Oscillator (VCO) Desirable characteristics: Monotonic f osc vs. V C characteristic with adequate frequency range f max f osc Well-defined K vco f min slope = K vco VC V C in V K F(s)
More informationSerDes_Channel_Impulse_Modeling_with_Rambus
SerDes_Channel_Impulse_Modeling_with_Rambus Author: John Baprawski; John Baprawski Inc. (JB) Email: John.baprawski@gmail.com Web sites: https://www.johnbaprawski.com; https://www.serdesdesign.com Date:
More informationSuccessive Approximation ADCs
Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]
More informationIssues with sampling time and jitter in Annex 93A. Adam Healey IEEE P802.3bj Task Force May 2013
Issues with sampling time and jitter in Annex 93A Adam Healey IEEE P802.3bj Task Force May 2013 Part 1: Jitter (comment #157) 2 Treatment of jitter in COM Draft 2.0 h (0) (t s ) slope h(0) (t s ) 1 UI
More informationLECTURE 3 CMOS PHASE LOCKED LOOPS
Lecture 03 (8/9/18) Page 3-1 LECTURE 3 CMOS PHASE LOCKED LOOPS Topics The acquisition process unlocked state Noise in linear PLLs Organization: Systems Perspective Types of PLLs and PLL Measurements PLL
More informationLecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM
Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?
More informationMotivation for CDR: Deserializer (1)
Motivation for CDR: Deserializer (1) Input data 1:2 DMUX 1:2 DMUX channel 1:2 DMUX Input clock 2 2 If input data were accompanied by a well-synchronized clock, deserialization could be done directly. EECS
More informationA Statistical Study of the Effectiveness of BIST Jitter Measurement Techniques
A Statistical Study of the Effectiveness of BIST Jitter Measurement Techniques David Bordoley, Hieu guyen, Mani Soma Department of Electrical Engineering, University of Washington, Seattle WA {bordoley,
More informationDigital Band-pass Modulation PROF. MICHAEL TSAI 2011/11/10
Digital Band-pass Modulation PROF. MICHAEL TSAI 211/11/1 Band-pass Signal Representation a t g t General form: 2πf c t + φ t g t = a t cos 2πf c t + φ t Envelope Phase Envelope is always non-negative,
More informationOn Modern and Historical Short-Term Frequency Stability Metrics for Frequency Sources
On Modern and Historical Short-Term Frequency Stability Metrics for Frequency Sources Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc. EFTF-IFCS, Besançon, France Session BL-D:
More information14 Gb/s AC Coupled Receiver in 90 nm CMOS. Masum Hossain & Tony Chan Carusone University of Toronto
14 Gb/s AC Coupled Receiver in 90 nm CMOS Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca OUTLINE Chip-to-Chip link overview AC interconnects Link modelling ISI & sensitivity
More informationINFLUENCE OF EVEN ORDER DISPERSION ON SOLITON TRANSMISSION QUALITY WITH COHERENT INTERFERENCE
Progress In Electromagnetics Research B, Vol. 3, 63 72, 2008 INFLUENCE OF EVEN ORDER DISPERSION ON SOLITON TRANSMISSION QUALITY WITH COHERENT INTERFERENCE A. Panajotovic and D. Milovic Faculty of Electronic
More informationPrinciples of Communications
Principles of Communications Chapter V: Representation and Transmission of Baseband Digital Signal Yongchao Wang Email: ychwang@mail.xidian.edu.cn Xidian University State Key Lab. on ISN November 18, 2012
More informationEE4512 Analog and Digital Communications Chapter 4. Chapter 4 Receiver Design
Chapter 4 Receiver Design Chapter 4 Receiver Design Probability of Bit Error Pages 124-149 149 Probability of Bit Error The low pass filtered and sampled PAM signal results in an expression for the probability
More informationEE 230 Lecture 40. Data Converters. Amplitude Quantization. Quantization Noise
EE 230 Lecture 40 Data Converters Amplitude Quantization Quantization Noise Review from Last Time: Time Quantization Typical ADC Environment Review from Last Time: Time Quantization Analog Signal Reconstruction
More informationRevision of Lecture 4
Revision of Lecture 4 We have completed studying digital sources from information theory viewpoint We have learnt all fundamental principles for source coding, provided by information theory Practical
More informationSquare Root Raised Cosine Filter
Wireless Information Transmission System Lab. Square Root Raised Cosine Filter Institute of Communications Engineering National Sun Yat-sen University Introduction We consider the problem of signal design
More informationFundamentals of PLLs (III)
Phase-Locked Loops Fundamentals of PLLs (III) Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering Phase transfer function in linear model i (s) Kd e (s) Open-loop transfer
More informationAccurate Statistical Analysis of High-Speed Links with PAM-4 Modulation
EPEPS IBIS Summit San Jose, California October 8, 05 Accurate Statistical Analsis of High-Speed Links with PAM-4 Modulation Vladimir Dmitriev-Zdorov Mentor Graphics Corp., vladimir_dmitriev-zdorov@mentor.com
More informationTotal Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method. White Paper
Total Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method White Paper DesignCon 25 Marcus Müller, Agilent Technologies [marcus_mueller2@agilent.com, (+49 731) 464-831] Ransom
More informationWeiyao Lin. Shanghai Jiao Tong University. Chapter 5: Digital Transmission through Baseband slchannels Textbook: Ch
Principles of Communications Weiyao Lin Shanghai Jiao Tong University Chapter 5: Digital Transmission through Baseband slchannels Textbook: Ch 10.1-10.5 2009/2010 Meixia Tao @ SJTU 1 Topics to be Covered
More informationTransient Response of Transmission Lines and TDR/TDT
Transient Response of Transmission Lines and TDR/TDT Tzong-Lin Wu, Ph.D. EMC Lab. Department of Electrical Engineering National Sun Yat-sen University Outlines Why do we learn the transient response of
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis
EE115C Winter 2017 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop-
More informationThe Linear-Feedback Shift Register
EECS 141 S02 Timing Project 2: A Random Number Generator R R R S 0 S 1 S 2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 The Linear-Feedback Shift Register 1 Project Goal Design a 4-bit LFSR SPEED, SPEED,
More informationApplication Note AN37. Noise Histogram Analysis. by John Lis
AN37 Application Note Noise Histogram Analysis by John Lis NOISELESS, IDEAL CONVERTER OFFSET ERROR σ RMS NOISE HISTOGRAM OF SAMPLES PROBABILITY DISTRIBUTION FUNCTION X PEAK-TO-PEAK NOISE Crystal Semiconductor
More informationDIGITAL COMMUNICATIONS. IAGlover and P M Grant. Prentice Hall 1997 PROBLEM SOLUTIONS CHAPTER 6
DIGITAL COMMUNICATIONS IAGlover and P M Grant Prentice Hall 997 PROBLEM SOLUTIONS CHAPTER 6 6. P e erf V σ erf. 5 +. 5 0.705 [ erf (. 009)] [ 0. 999 979 ]. 0 0 5 The optimum DC level is zero. For equiprobable
More informationSimilarities of PMD and DMD for 10Gbps Equalization
Similarities of PMD and DMD for 10Gbps Equalization Moe Win Jack Winters win/jhw@research.att.com AT&T Labs-Research (Some viewgraphs and results curtesy of Julien Porrier) Outline Polarization Mode Dispersion
More informationEEO 401 Digital Signal Processing Prof. Mark Fowler
EEO 401 Digital Signal Processing Pro. Mark Fowler Note Set #14 Practical A-to-D Converters and D-to-A Converters Reading Assignment: Sect. 6.3 o Proakis & Manolakis 1/19 The irst step was to see that
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationEECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders
EECS 427 Lecture 14: Timing Readings: 10.1-10.3 EECS 427 F09 Lecture 14 1 Reminders CA assignments Please submit CA6 by tomorrow noon CA7 is due in a week Seminar by Prof. Bora Nikolic SRAM variability
More informationExample: Bipolar NRZ (non-return-to-zero) signaling
Baseand Data Transmission Data are sent without using a carrier signal Example: Bipolar NRZ (non-return-to-zero signaling is represented y is represented y T A -A T : it duration is represented y BT. Passand
More informationDigital Baseband Systems. Reference: Digital Communications John G. Proakis
Digital Baseband Systems Reference: Digital Communications John G. Proais Baseband Pulse Transmission Baseband digital signals - signals whose spectrum extend down to or near zero frequency. Model of the
More informationData Converter Fundamentals
Data Converter Fundamentals David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 33 Introduction Two main types of converters Nyquist-Rate Converters Generate output
More informationECEN 610 Mixed-Signal Interfaces
ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)
More informationStudy on Measurement Method of Clock Jitter
, pp.67-74 http://dx.doi.org/0.4257/astl.204.76.7 Study on Measurement Method of Clock Jitter Feijiang Huang 2, Binxia Du 2, Yong Cao 2, Gun Li 2 Department of Electronic Information and Electrical Engineering,
More informationLecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
More informationDesignCon 2008 EDA365. Modeling a Phase Interpolator as a Delta-Sigma Converter. Andy Martwick
DesignCon 28 Modeling a Phase Interpolator as a Delta-Sigma Converter Andy Martwick andy.martwick@intel.com Abstract This paper provides a model and analysis of the frequency response and key characteristics
More informationPresenters. Time Domain and Statistical Model Development, Simulation and Correlation Methods for High Speed SerDes
JANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER Time Domain and Statistical Model Development, Simulation and Correlation Methods or High Speed SerDes Presenters Xingdong Dai Fangyi Rao Shiva Prasad
More informationDigital Communications
Digital Communications Chapter 9 Digital Communications Through Band-Limited Channels Po-Ning Chen, Professor Institute of Communications Engineering National Chiao-Tung University, Taiwan Digital Communications:
More informationMATHEMATICAL TOOLS FOR DIGITAL TRANSMISSION ANALYSIS
ch03.qxd 1/9/03 09:14 AM Page 35 CHAPTER 3 MATHEMATICAL TOOLS FOR DIGITAL TRANSMISSION ANALYSIS 3.1 INTRODUCTION The study of digital wireless transmission is in large measure the study of (a) the conversion
More informationOptoelectronic Applications. Injection Locked Oscillators. Injection Locked Oscillators. Q 2, ω 2. Q 1, ω 1
Injection Locked Oscillators Injection Locked Oscillators Optoelectronic Applications Q, ω Q, ω E. Shumakher, J. Lasri,, B. Sheinman, G. Eisenstein, D. Ritter Electrical Engineering Dept. TECHNION Haifa
More informationRoundoff Noise in Digital Feedback Control Systems
Chapter 7 Roundoff Noise in Digital Feedback Control Systems Digital control systems are generally feedback systems. Within their feedback loops are parts that are analog and parts that are digital. At
More informationPulse Shaping and ISI (Proakis: chapter 10.1, 10.3) EEE3012 Spring 2018
Pulse Shaping and ISI (Proakis: chapter 10.1, 10.3) EEE3012 Spring 2018 Digital Communication System Introduction Bandlimited channels distort signals the result is smeared pulses intersymol interference
More informationMethod for analytically calculating BER (bit error rate) in presence of non-linearity. Gaurav Malhotra Xilinx
Method for analytically calculating BER (bit error rate) in presence of non-linearity Gaurav Malhotra Xilinx Outline Review existing methodology for calculating BER based on linear system analysis. Link
More informationDirect-Sequence Spread-Spectrum
Chapter 3 Direct-Sequence Spread-Spectrum In this chapter we consider direct-sequence spread-spectrum systems. Unlike frequency-hopping, a direct-sequence signal occupies the entire bandwidth continuously.
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationD/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
More information8.1 Circuit Parameters
8.1 Circuit Parameters definition of decibels using decibels transfer functions impulse response rise time analysis Gaussian amplifier transfer function RC circuit transfer function analog-to-digital conversion
More informationEfficient Algorithms for Pulse Parameter Estimation, Pulse Peak Localization And Pileup Reduction in Gamma Ray Spectroscopy M.W.Raad 1, L.
Efficient Algorithms for Pulse Parameter Estimation, Pulse Peak Localization And Pileup Reduction in Gamma Ray Spectroscopy M.W.Raad 1, L. Cheded 2 1 Computer Engineering Department, 2 Systems Engineering
More informationFigure 1.1 (a) Model of a communication system, and (b) signal processing functions.
. Introduction to Signals and Operations Model of a Communication System [] Figure. (a) Model of a communication system, and (b) signal processing functions. Classification of Signals. Continuous-time
More informationIssues on Timing and Clocking
ECE152B TC 1 Issues on Timing and Clocking X Combinational Logic Z... clock clock clock period ECE152B TC 2 Latch and Flip-Flop L CK CK 1 L1 1 L2 2 CK CK CK ECE152B TC 3 Clocking X Combinational Logic...
More informationDesigning Sequential Logic Circuits
igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was
More informationSummary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined
More informationVarious signal sampling and reconstruction methods
Various signal sampling and reconstruction methods Rolands Shavelis, Modris Greitans 14 Dzerbenes str., Riga LV-1006, Latvia Contents Classical uniform sampling and reconstruction Advanced sampling and
More informationResidual Versus Suppressed-Carrier Coherent Communications
TDA Progress Report -7 November 5, 996 Residual Versus Suppressed-Carrier Coherent Communications M. K. Simon and S. Million Communications and Systems Research Section This article addresses the issue
More informationPCM Reference Chapter 12.1, Communication Systems, Carlson. PCM.1
PCM Reference Chapter 1.1, Communication Systems, Carlson. PCM.1 Pulse-code modulation (PCM) Pulse modulations use discrete time samples of analog signals the transmission is composed of analog information
More informationCorrelator I. Basics. Chapter Introduction. 8.2 Digitization Sampling. D. Anish Roshi
Chapter 8 Correlator I. Basics D. Anish Roshi 8.1 Introduction A radio interferometer measures the mutual coherence function of the electric field due to a given source brightness distribution in the sky.
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive
More informationPrepare for this experiment!
Notes on Experiment #8 Theorems of Linear Networks Prepare for this experiment! If you prepare, you can finish in 90 minutes. If you do not prepare, you will not finish even half of this experiment. So,
More informationLecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory
EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 27: Latches Timing Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday,
More informationω 0 = 2π/T 0 is called the fundamental angular frequency and ω 2 = 2ω 0 is called the
he ime-frequency Concept []. Review of Fourier Series Consider the following set of time functions {3A sin t, A sin t}. We can represent these functions in different ways by plotting the amplitude versus
More informationTracking of Spread Spectrum Signals
Chapter 7 Tracking of Spread Spectrum Signals 7. Introduction As discussed in the last chapter, there are two parts to the synchronization process. The first stage is often termed acquisition and typically
More informationEE241 - Spring 2006 Advanced Digital Integrated Circuits
EE241 - Spring 2006 Advanced Digital Integrated Circuits Lecture 20: Asynchronous & Synchronization Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal
More informationPolarization division multiplexing system quality in the presence of polarization effects
Opt Quant Electron (2009) 41:997 1006 DOI 10.1007/s11082-010-9412-0 Polarization division multiplexing system quality in the presence of polarization effects Krzysztof Perlicki Received: 6 January 2010
More informationLECTURE 5 Noise and ISI
MIT 6.02 DRAFT Lecture Notes Spring 2010 (Last update: February 22, 2010) Comments, questions or bug reports? Please contact 6.02-staff@mit.edu LECTURE 5 Noise and ISI Sometimes theory tells you: Stop
More information(A) (B) (D) (C) 1.5. Amplitude (volts) 1.5. Amplitude (volts) Time (seconds) Time (seconds)
Reminder: Lab #1 : Limitations of A/D conversion Lab #2 : Thermocouple, static and dynamic calibration Lab #3 : Conversion of work into heat Lab #4 : Pressure transducer, static and dynamic calibration
More informationXarxes de distribució del senyal de. interferència electromagnètica, consum, soroll de conmutació.
Xarxes de distribució del senyal de rellotge. Clock skew, jitter, interferència electromagnètica, consum, soroll de conmutació. (transparències generades a partir de la presentació de Jan M. Rabaey, Anantha
More informationEE303: Communication Systems
EE303: Communication Systems Professor A. Manikas Chair of Communications and Array Processing Imperial College London Introductory Concepts Prof. A. Manikas (Imperial College) EE303: Introductory Concepts
More informationEE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 25: Synchronization Timing Announcements Homework 5 due on 4/26 Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1 Project
More informationLOPE3202: Communication Systems 10/18/2017 2
By Lecturer Ahmed Wael Academic Year 2017-2018 LOPE3202: Communication Systems 10/18/2017 We need tools to build any communication system. Mathematics is our premium tool to do work with signals and systems.
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2
More informationEE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures Large number of different circuits have been proposed for building data converters
More informationPrinciples of Communications Lecture 8: Baseband Communication Systems. Chih-Wei Liu 劉志尉 National Chiao Tung University
Principles of Communications Lecture 8: Baseband Communication Systems Chih-Wei Liu 劉志尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Outlines Introduction Line codes Effects of filtering Pulse
More informationDDR4 Board Design and Signal Integrity Verification Challenges
DDR4 Board Design and Signal Integrity Verification Challenges Outline Enabling DDR4 Pseudo Open Drain Driver - Benefit POD SI effects VrefDQ Calculation Data Eye Simulating SSN New Drive Standards Difference
More informationNonlinearity Equalization Techniques for DML- Transmission Impairments
Nonlinearity Equalization Techniques for DML- Transmission Impairments Johannes von Hoyningen-Huene jhh@tf.uni-kiel.de Christian-Albrechts-Universität zu Kiel Workshop on Optical Communication Systems
More informationLab Fourier Analysis Do prelab before lab starts. PHSX 262 Spring 2011 Lecture 5 Page 1. Based with permission on lectures by John Getty
Today /5/ Lecture 5 Fourier Series Time-Frequency Decomposition/Superposition Fourier Components (Ex. Square wave) Filtering Spectrum Analysis Windowing Fast Fourier Transform Sweep Frequency Analyzer
More informationSignal integrity in deep-sub-micron integrated circuits
Signal integrity in deep-sub-micron integrated circuits Alessandro Bogliolo abogliolo@ing.unife.it Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: pecial Topics in High-peed Links Circuits and ystems pring 01 Lecture 3: Time-Domain Reflectometry & -Parameter Channel Models am Palermo Analog & Mixed-ignal Center Texas A&M University Announcements
More informationFrequency Detection of CDRs (1)
Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =
More informationA Family of Nyquist Filters Based on Generalized Raised-Cosine Spectra
Proc. Biennial Symp. Commun. (Kingston, Ont.), pp. 3-35, June 99 A Family of Nyquist Filters Based on Generalized Raised-Cosine Spectra Nader Sheikholeslami Peter Kabal Department of Electrical Engineering
More informationCommunication Engineering Prof. Surendra Prasad Department of Electrical Engineering Indian Institute of Technology, Delhi
Communication Engineering Prof. Surendra Prasad Department of Electrical Engineering Indian Institute of Technology, Delhi Lecture - 41 Pulse Code Modulation (PCM) So, if you remember we have been talking
More informationThe first printing of this book was produced with a few minor printing errors. We apologize for any confusion this might cause you.
The first printing of this book was produced with a few minor printing errors. We apologize for any confusion this might cause you. Page Correction Sentence added before Figure 2.3: "R 6 out is typically
More informationACCUMULATED JITTER MEASUREMENT OF STANDARD CLOCK OSCILLATORS
METROLOGY AND MEASUREMENT SYSTEMS Index 330930, ISSN 0860-89 www.metrology.pg.gda.pl ACCUMULATED JITTER MEASUREMENT OF STANDARD CLOCK OSCILLATORS Marek Zieliński, Marcin Kowalski, Robert Frankowski, Dariusz
More informationSelf-Phase Modulation in Optical Fiber Communications: Good or Bad?
1/100 Self-Phase Modulation in Optical Fiber Communications: Good or Bad? Govind P. Agrawal Institute of Optics University of Rochester Rochester, NY 14627 c 2007 G. P. Agrawal Outline Historical Introduction
More informationChapter 7. Digital Control Systems
Chapter 7 Digital Control Systems 1 1 Introduction In this chapter, we introduce analysis and design of stability, steady-state error, and transient response for computer-controlled systems. Transfer functions,
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More information1. SINGULARITY FUNCTIONS
1. SINGULARITY FUNCTIONS 1.0 INTRODUCTION Singularity functions are discontinuous functions or their derivatives are discontinuous. A singularity is a point at which a function does not possess a derivative.
More informationLecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters
Lecture 6, ATIK Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters What did we do last time? Switched capacitor circuits The basics Charge-redistribution analysis Nonidealties
More informationSistemas de Aquisição de Dados. Mestrado Integrado em Eng. Física Tecnológica 2016/17 Aula 3, 3rd September
Sistemas de Aquisição de Dados Mestrado Integrado em Eng. Física Tecnológica 2016/17 Aula 3, 3rd September The Data Converter Interface Analog Media and Transducers Signal Conditioning Signal Conditioning
More informationPerformance of Coherent Binary Phase-Shift Keying (BPSK) with Costas-Loop Tracking in the Presence of Interference
TMO Progress Report 4-139 November 15, 1999 Performance of Coherent Binary Phase-Shift Keying (BPSK) with Costas-Loop Tracking in the Presence of Interference M. K. Simon 1 The bit-error probability performance
More informationTiming Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationEE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 7 Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling . Review from last lecture. MatLab comparison: 512 Samples
More information