CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

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1 CHAPTER 9 MULTIPLEERS DECODERS AND PROGRAMMABLE LOGIC DEVICES

2 Contents 9. Introution 9.2 Multiplexers 9.3 Three-Stte Buffers 9.4 Deoers n Enoers 9.5 Re-Only Memories 9.6 Progrmmle Logi Devies 9.7 Complex Progrmmle Logi Devies 9.8 Fiel Progrmmle Gte Arrys

3 Ojetives. Explin the funtion of multiplexer. Implement multiplexer using gtes. 2. Explin the opertion of three-stte uffers. Determine the resulting output when three-stte uffers outputs re onnete together. Use three-stte uffers to multiplex signls onto us. 3. Explin the opertion of eoer n enoer. Use eoer with e gtes to implement set of logi funtions. Implement eoer or priority enoer using gtes. 4. Explin the opertion of re-only memory (ROM). Use ROM to implement set of logi funtions. 5. Explin the opertion of progrmmle logi rry (PLA). Use PLA to implement set of logi funtions. Given PLA tle or n internl onnetion igrm for PLA etermine the logi funtions relize. 6. Explin the opertion of progrmmle rry logi evie (PAL). Determine the progrmming pttern require to relize set of logi funtion with PAL. 7. Explin the opertion of omplex progrmmle logi evie (CPLD) n fiel progrmmle gte rry (FPGA). 8. Use Shnnon s expnsion theorem to eompose swithing funtion.

4 9. Introution Multiplexer Deoer enoer. Three-stte Buffer ROMs PLD PLA CPLD FPGA

5 9.2 Multiplexers Fig to- Multiplexer n Swith Anlog logi eqution for the 2 - to -MU Z A I AI

6 9.2 Multiplexers Fig 9-2. Multiplexer () logi eqution for the 4 - to -MU Z A B I I A BI AB 2 ABI 3

7 9.2 Multiplexers Fig 9-2. Multiplexer (2) logi eqution for the 8 - to -MU Z A B C I AB C I 4 A B CI AB CI A BC I 5 2 ABC I 6 A BCI ABCI 3 7

8 9.2 Multiplexers Fig 9-2. Multiplexer (3) logi eqution for the 2 n - to - MU Z n 2 k m k I k

9 9.2 Multiplexers Fig 9-3. Logi Digrm for 8-to- MU

10 9.2 Multiplexers Fig 9-4. Qu Multiplexer Use to Selet Dt

11 9.2 Multiplexers Fig 9-5. Qu Multiplexer with Bus Inputs n Output

12 9.3 Three-Stte Buffers Fig 9-6. Gte Ciruit with Ae Buffer

13 Fig 9-7. Three-Stte Buffer 9.3 Three-Stte Buffers

14 9.3 Three-Stte Buffers Fig 9-8. Four Kins of Three-Stte Buffers B A C B A C B A C B A C Z Z Z Z Z Z Z Z () () () () We use the Symol Z to represent high-impene stte

15 9.3 Three-Stte Buffers Fig 9-9. Dt Seletion Using Three-Stte Buffers

16 9.3 Three-Stte Buffers Fig 9-. Ciruit with Two Three-Stte Buffers S2 S Z Z Z Unknown

17 9.3 Three-Stte Buffers Fig Bit Aer with Four Soures for One Opern

18 9.3 Three-Stte Buffers Fig 9-2. Integrte Ciruit with Bi-Diretionl Input/Output Pin

19 9.4 Deoers n Enoers Fig to-8 Line Deoer y y y 2 y 3 y 4 y 5 y 6 y 7

20 9.4 Deoers n Enoers Fig 9-4. A 4-to- Line Deoer ()

21 9.4 Deoers n Enoers Fig 9-4. A 4-to- Line Deoer (2) 7 8 Deiml Output BCD Input A B C D () Truth Tle

22 9.4 Deoers n Enoers Fig 9-5. Reliztion of Multiple-Output Ciruit Using Deoer (inverte outputs) 2 to (noninverte outputs) 2 to n i i i n i i i M m y or i m y ) ( ) ( m m m m m m f ) ( ) ( m m m m m m f

23 9.4 Deoers n Enoers Fig to-3 Priority Enoer y 3 y 4 y 5 y 6 y 7 y y 2 y

24 9.5 Re-Only Memories Fig 9-7. An 8-Wor x 4-Bit ROM F C F F 2 F 3 B A () Blok igrm () Truth tle for ROM typil t store in ROM (2 3 wors of 4its eh)

25 9.5 Re-Only Memories Fig 9-8. Re-Only Memory with n Inputs n m Outputs n input Vriles m output Vriles typil t rry store in ROM (2 n wors of m its eh)

26 Fig 9-9. Bsi ROM Struture 9.5 Re-Only Memories

27 9.5 Re-Only Memories Fig 9-2. An 8-Wor x 4-Bit ROM F F F F 2 3 m(46) A B AC m(23467) B AC m(26) A B BC m(23567) AC B

28 9.5 Re-Only Memories Fig 9-2. Equivlent OR Gte for F F m(46) A B AC

29 9.5 Re-Only Memories Fig Hexeiml to ASCII Coe Converter ASCII Coe for Hex Digit Input A B C D E F A 6 A 5 A 4 A 3 A 2 A Hex Digit A Z Y W

30 9.5 Re-Only Memories Fig ROM Reliztion of Coe Converter

31 9.6 Progrmmle Logi Devies Fig Progrmmle Logi Arry Struture

32 9.6 Progrmmle Logi Devies Fig PLA with Three Inputs Five Prout Terms n Four Outputs

33 9.6 Progrmmle Logi Devies Fig AND-OR Arry Equivlent to Figure 9-25

34 9.6 Progrmmle Logi Devies Tle 9-. PLA Tle for Figure 9-25 Prout Term A B AC B BC AC A - - Inputs B - - C - - Outputs F F F 2 F 3 F F F F 2 3 A B AC AC B A B BC B AC

35 9.6 Progrmmle Logi Devies Fig PLA Reliztion of Equtions (7-23) f f 2 f () PLA tle

36 9.6 Progrmmle Logi Devies Progrmmle Arry Logi The symol of Figure 9-28() logilly equl

37 9.6 Progrmmle Logi Devies Progrmmle Arry Logi Connetions to the AND gte inputs in PAL

38 9.6 Progrmmle Logi Devies Fig PAL Segment

39 9.6 Progrmmle Logi Devies Fig Implementtion of Full Aer Using PAL Y C YC Y C YC in in in in C in YC in Y

40 9.7 Complex Progrmmle Logi Devies Fig 9-3. Arhiteture of ilinx CR364L CPLD (Figure se on figures n text owne y ilinx In. Courtesy of ilinx In. ilinx In All rights reserve.)

41 9.7 Complex Progrmmle Logi Devies Fig 9-3. CPLD Funtion Blok n Mroell (A Simplifie Version of CR364L)

42 9.8 Fiel Progrmmle Gte Arrys Fig Equivlent OR Gte for F

43 9.8 Fiel Progrmmle Gte Arrys Fig Simplifie Configurle Logi Blok (CLB)

44 9.8 Fiel Progrmmle Gte Arrys Fig Implementtion of Lookup Tle (LUT) f F

45 9.8 Fiel Progrmmle Gte Arrys Deomposition if swithing Funtions ) ( ) ( ) ( f f f f f ) ( ) ( ) ( ) ( ) ( f f f i i i n i i i n i i i n i i i f x f x x x x x x f x x x x x x f x x x x x x x f ) ( ) ( ) (

46 9.8 Fiel Progrmmle Gte Arrys Deomposition if swithing Funtions ) ( ) ( ) ( f f e f e f e f ) ( ) ( ) ( ) ( ) ( ) ( ) ( G G f e G f e G G G G f e G f e G G G G f e G f e G f e G ) ( G G G G f e G

47 9.8 Fiel Progrmmle Gte Arrys Fig Funtion Expnsion Using Krnugh Mp

48 9.8 Fiel Progrmmle Gte Arrys Fig Reliztion of Five- n Six-Vrile Funtions with Funtion Genertors

Programmable Logic Devices

Programmable Logic Devices Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable