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1 2.4 Logic Minimiztion nd Krnugh Mps As we found ove, given truth tle, it is lwys possile to write down correct logic expression simply y forming n OR of the ANDs of ll input vriles for which the output is true (Q = 1). However, for n ritrry truth tle such procedure could produce very lengthy nd cumersome expression which might e needlessly inecient to implement with gtes. There re severl methods for simpliction of Boolen logic expressions. The process is usully clled \logic minimiztion", nd the gol is to form result which is ecient. Two methods we will discuss re lgeric minimiztion nd Krnugh mps. For very complicted prolems the former method cn e done using specil softwre nlysis progrms. Krnugh mps re lso limited to prolems with up to 4 inry inputs. Let's strt with simple exmple. The tle elow gives n ritrry truth tle involving 2 logic inputs. Tle 1: Exmple of simple ritrry truth tle. A B Q There re two overll sttegies: 1. Write down n expression directly from the truth tle. Use Boolen lger, if desired, to simplify. 2. Use Krnugh mpping (\K-mp"). This is only pplicle if there re 4 inputs. In our exmple ove, we cnusetwo dierent wys of writin down result directly from the truth tle. We cn write down ll TRUE terms nd OR the result. This gives Q = A B + AB + AB While correct, without further simpliction this expression would involve 3 2-input AND gtes, 2 inverters, nd 1 3-input OR gte. Alterntively, one cn write down n expression for ll of the FALE sttes of the truth tle. This is simpler in this cse: Q = A B! Q = A B = A + B where the lst step results from Eqn. 3. Presumly, the two expressions cn e found to e equivlent with some lger. Certinly, the 2nd is simpler, nd involves only n inverter nd one 2-input OR gte. 8

2 Finlly, one cn try K-mp solution. The rst step is to write out the truth tle in the form elow, with the input sttes the hedings of rows nd columns of tle, nd the corresponding outputs within, s shown elow. Tle 2: K-mp of truth tle. AnB The steps/rules re s follows: 1. Form the 2-dimensionl tle s ove. Comine 2 inputs in \gry code"wy {see 2nd exmple elow. 2. Form groups of 1's nd circle them; the groups re rectngulr nd must hve sides of length 2 n 2 m, where n nd m re integers 0; 1; 2;:::. 3. The groups cn overlp. 4. Write down n expression of the inputs for ech group. 5. OR together these expressions. Tht's it. 6. Groups cn wrp cross tle edges. 7. As efore, one cn lterntively form groups of 0's to give solution for Q. 8. The igger the groups one cn form, the etter (simpler) the result. 9. There re usully mny lterntive solutions, ll equivlent, some etter thn others depending upon wht one is trying to optimize. AnB 0 1 Here is one wy of doing it: The two groupswehve drwn re A nd B. o the solution (s efore) is: K-mp Exmple 2 Q = A + B Let's use this to determine which 3-it numers re prime. (This is homework prolem.) We ssume tht 0; 1; 2re not prime. We will let our input numer hve digits Here is the truth tle: Here is the corresponding K-mp nd solution. Note tht where two inputsrecomined in row or column tht their progression follows gry code, tht is only one it chnges t time. The solution shown ove is: Q = = 0 ( ) 9

3 Tle 3: 3-digit prime nder. Deciml Q Tle 4: K-mp of truth tle. 2 n

4 2.4.2 K-mp Exmple 3: Full Adder In this exmple we will outline how to uild digitl full dder. It is clled \full" ecuse it will include \crry-in" it nd \crry-out" it. The crry its will llow succession of 1-it full dders to e used to dd inry numers of ritrry length. (A hlf dder includes only one crry it.) i i i i i Figure 7: Block schemtic of full dder. (We nme our dder the \ chip"). The scheme for the full dder is outlined in Fig. 7. Imgine tht we re dding two n-it inry numers. Let the inputs i nd i e the i-th its of the two numers. The crry in it i represents ny crry from the sum of the neighoring less signicnt its t position i, 1. Tht is, i =1if i,1 = i,1 = 1, nd is 0 otherwise. The sum i t position i is therefore the sum of i, i,nd i. (Note tht this is n rithmetic sum, not Boolen OR.) A crry for this sum sets the crry out it, i =1,which then cn e pplied to the sum of the i + 1 its. The truth tle is given elow. i i i i i With i =0,we see tht the output sum i is just given y the XOR opertion, i i. And with i = 1, then i = i i.perhps the simplest wy to express this reltionship is the following: i = i ( i i ) To determine reltively simple expression for i,we will use K-mp: i n i i

5 This yields i = i i + i i + i i = i i + i ( i + i ) which in hrdwre would e 2 2-input OR gtes nd 2 2-input AND gtes. As stted ove, the crry its llow our dder to e expnded to dd ny numer of its. As n exmple, 4-it dder circuit is depicted in Fig. 8. The sum cn e 5 its, where the MB is formed y the nl crry out. (ometimes this is referred to s n \overow" it.) Figure 8: Expnsion of 1-it full dder to mke 4-it dder Mking Multiplier from n Adder In clss we will discuss how to use our full dder (the \ chip") to mke multiplier. 2.5 Multiplexing Amultiplexer (MUX) is device which selects one of mny inputs to single output. The selection is done y using n input ddress. Hence, MUX cn tke mny dt its nd put them, one t time, on single output dt line in prticulr sequence. This is n exmple of trnsforming prllel dt to seril dt. A demultiplexer (DEMUX) performs the inverse opertion, tking one input nd sending it to one of mny possile outputs. Agin the output line is selected using n ddress. A MUX-DEMUX pir cn e used to convert dt to seril form for trnsmission, thus reducing the numer of required trnsmission lines. The ddress its re shred y the MUX nd DEMUX t ech end. If n dt its re to e trnsmitted, then fter multiplexing, the numer of seprte lines required is log 2 n + 1, compred to n without the conversion to seril. Hence for lrge n the sving cn e sustntil. In L 2, you will uild such system. Multiplexers consist of two functionlly seprte components, decoder nd some switches or gtes. The decoder interprets the input ddress to select single dt it. We use the exmple of 4-it MUX in the following section to illustrte how this works A 4-it MUX Design We wish to design 4-it multiplexer. The lock digrm is given in Fig. 9. There re 4 input dt its D 0 {D 3, 2 input ddress its A 0 nd A 1, one seril output dt it Q, nd 12

6 n (optionl) enle it E which is used for expnsion (discussed lter). First we will design the decoder. E MUX D3 D2 D1 D 0 GATE /WITCHE C 3 C C C Q A 1 A 0 DECODER Figure 9: Block digrm of 4-it MUX. We need m ddress its to specify 2 m dt its. o in our exmple, we hve 2 ddress its. The truth tle for our decoder is strightforwrd: A 1 A 0 C 0 C 1 C 2 C The implementtion of the truth tle with stndrd gtes is lso strightforwrd, s given in Fig. 10. C 3 C C C A 1 A 0 Figure 10: Decoder for the 4-it MUX. For the \gtes/switches" prt of the MUX, the design depends upon whether the input dt lines crry digitl or nlog signls. We will discuss the nlog possiility lter. The digitl cse is the usul nd simplest cse. Here, the dt routing cn e ccomplished 13

7 simply y forming 2-input ANDs of the decoder outputs with the corresponding dt input, nd then forming n OR of these terms. Explicitly, Q = C 0 D 0 + C 1 D 1 + C 2 D 2 + C 3 D 3 Finlly, if n ENABLE line E is included, it is simply ANDed with the righthnd side of this expression. This cn e used to switch the entire MUX IC o/on, nd is useful for expnsion to more its. s we shll see. 14

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