EE 108A Lecture 2 (c) W. J. Dally and P. Levis 2

Transcription

1 EE08A Leture 2: Comintionl Logi Design EE 08A Leture 2 () W. J. Dlly n P. Levis Announements Prof. Levis will hve no offie hours on Friy, Jn 8. Ls n setions hve een ssigne - see the we pge Register for eelss Ls strt this week - no prel for L 0 Hnouts Leture notes Homework 2 L EE 08A Leture 2 () W. J. Dlly n P. Levis 2

2 Review Leture The worl is igitl Anlog t the eges, hrwre for emning prolems, 00x per ee Digitl signls Enoe isrete sttes in ontinuous signl Rejet noise Representtions Binry, set, ontinuous, ompoun Boolen Alger (0,,, ) Axioms, properties, ulity Logi equtions express inry funtions Comintionl logi Output is funtion only of urrent input Verilog Defines hrwre moules, ssign, se EE 08A Leture 2 () W. J. Dlly n P. Levis 3 Toy How to implement omintionl logi y hn Given esription of logi funtion Generte gte-level iruit tht relizes tht funtion Everyone nees to o this one To unerstn how its one Demystifies wht the synthesis tools o Better unerstning of wht synthesis tools n n n t o Mkes you etter t helping synthesis tool o goo jo In prtie you will rrely hve to o this y hn Generl prtie is: Design using Verilog Simulte with test ses Generte gtes with synthesis progrm EE 08A Leture 2 () W. J. Dlly n P. Levis 4 2

3 English lnguge esription of omintionl logi funtion F(,,,) is true if input,,, is prime EE 08A Leture 2 () W. J. Dlly n P. Levis 5 Truth Tle F(,,,) is true if input,,, is prime No q EE 08A Leture 2 () W. J. Dlly n P. Levis 6 3

4 Eqution F(,,,) is true if input,,, is prime! f = m(,2,3,5,7,,3) No q EE 08A Leture 2 () W. J. Dlly n P. Levis 7 Shemti Logi Digrm Shemti Logi Digrm: Eqution:! f = m(,2,3,5,7,,3) 2 3 5! f 7 3 EE 08A Leture 2 () W. J. Dlly n P. Levis 8 4

5 Cue representtion (3-it prime) f = m(,2,3,5,7 ) XX0 X0 00 0X 0 X00 XX XX 0 X 00 0X0 X0 0X X0 00X XX X0X X 0X X 0 XX EE 08A Leture 2 () W. J. Dlly n P. Levis 9 4-D Hyperue (4-it prime)! f = m(,2,3,5,7,,3) EE 08A Leture 2 () W. J. Dlly n P. Levis 0 5

6 4-it Prime Numer Funtion (ont) xx 00x x0 x f = ( ) V ( ) V ( ) V ( ) V V V V V V V EE 08A Leture 2 () W. J. Dlly n P. Levis Krnugh Mp of 4-it Prime EE 08A Leture 2 () W. J. Dlly n P. Levis 2 6

7 Krnugh Mp of 4-it Prime: Minterms Position of minterms on 4-it Krnugh mp EE 08A Leture 2 () W. J. Dlly n P. Levis 3 Krnugh Mp of 4-it Prime: Implints Ajent minterms iffer in extly one it Every positive minterm is n implint EE 08A Leture 2 () W. J. Dlly n P. Levis 4 7

8 Krnugh Mp of 4-it Prime: Lrger Implints X X Cn omine jent minterms into implints EE 08A Leture 2 () W. J. Dlly n P. Levis 5 Krnugh Mp of 4-it Prime: Ajeny X X X0 00 Cn omine jent minterms into implints Note eges wrp roun EE 08A Leture 2 () W. J. Dlly n P. Levis 6 8

9 Krnugh Mp of 4-it Prime: A lrger implint EE 08A Leture 2 () W. J. Dlly n P. Levis Why mke implints overlp? Two resons:. Lrger implints hve fewer gtes. 2. Hzrs. More on them lter X X0 X0 9

10 0xx 00x x0 x X X0 X0 00X X0 X0 f In prtie, CMOS gtes re lwys inverting, so the rel iruit might look like this f Deiml prime numer funtion inlues on t res f =! m(,2,3,5,7) + D(0,,2,3,4,5) x x x x 0 0 x x EE 08A Leture 2 () W. J. Dlly n P. Levis 20 0

11 Deiml prime numer funtion K-Mp XX x x x x 0 0 x x X0X XX EE 08A Leture 2 () W. J. Dlly n P. Levis 2 Deiml prime numer funtion iruit Cover: X0X X0X f = ( ) V ( ) V V x x x x x x f X0X EE 08A Leture 2 () W. J. Dlly n P. Levis 22

12 Revisiting some efinitions (n some new ones) Minterm: prout term tht inlues eh input of iruit or its omplement. Implint: prout term tht if true implies the funtion is true. Prime Implint: is n implint tht nnot e me ny lrger n still e n implint. Essentil Prime Implint: the only prime implint tht ontins prtiulr minterm of the funtion. Distinguishe One: is minterm tht is ontine in only one implint EE 08A Leture 2 () W. J. Dlly n P. Levis 23 Prout-of-Sums Implementtion Sum-of-Prouts iruit: fous on inputs sttes where truth tle is. Prout-of-Sums: fous on input sttes where truth tle is 0. Bsi pproh: esign for the omplement, pply DeMorgn s We en up with prout of sums, not sum of prouts f =! M( 0,2) EE 08A Leture 2 () W. J. Dlly n P. Levis 24 2

13 Prout-of-Sums Implementtion f =! M(0,2) ( ) DeMorgn EE 08A Leture 2 () W. J. Dlly n P. Levis 25 Prout-of-Sums Exmple: Deiml Prime x x x x x x f =! M ( 6,7,9,,5) + D(0,,2,3,4,5) EE 08A Leture 2 () W. J. Dlly n P. Levis 26 3

14 Hzrs v v 3 N e f N Stti- hzr e f EE 08A Leture 2 () W. J. Dlly n P. Levis 27 Cover trnsitions to eliminte hzrs v v v 3 N f EE 08A Leture 2 () W. J. Dlly n P. Levis 28 4

15 Reminer: 4-it Prime Numer Funtion X X0 X0 00X X0 X0 f 0xx 00x x0 x0 f EE 08A Leture 2 () W. J. Dlly n P. Levis 29 4-it Prime Numer Funtion in Verilog Coe Using se moule prime(in, isprime) ; input [3:0] in ; // 4-it input output isprime ; // true if input is prime reg isprime ; egin se(in),2,3,5,7,,3: isprime = ' ; efult: isprime = '0 ; ense en enmoule EE 08A Leture 2 () W. J. Dlly n P. Levis 30 5

16 4-it Prime Numer Funtion in Verilog Coe Using sex moule prime(in, isprime) ; input [3:0] in ; // 4-it input output isprime ; // true if input is prime reg isprime ; egin sex(in) 4'0xx: isprime = ; 4'00x: isprime = ; 4'x0: isprime = ; 4'x0: isprime = ; efult: isprime = 0 ; ense en enmoule EE 08A Leture 2 () W. J. Dlly n P. Levis 3 4-it Prime Numer Funtion in Verilog Coe Using ssign moule prime(in, isprime) ; input [3:0] in ; // 4-it input output isprime ; // true if input is prime wire isprime = (in[0] & ~in[3]) (in[] & ~in[2] & ~in[3]) (in[0] & ~in[] & in[2]) (in[0] & in[] & ~in[2]) ; enmoule EE 08A Leture 2 () W. J. Dlly n P. Levis 32 6

17 Whih is etter esription? Why? Using se Using sex Using ssign moule prime(in, isprime) ; input [3:0] in ; output isprime ; reg isprime ; egin se(in),2,3,5,7,,3: isprime = ' ; efult: isprime = '0 ; ense en enmoule moule prime(in, isprime) ; input [3:0] in ; output isprime ; wire isprime = (in[0] & ~in[3]) (in[] & ~in[2] & ~in[3]) (in[0] & ~in[] & in[2]) (in[0] & in[] & ~in[2]) ; enmoule moule prime(in, isprime) ; input [3:0] in ; output isprime ; reg isprime ; egin sex(in) 4'0xx: isprime = ; 4'00x: isprime = ; 4'x0: isprime = ; 4'x0: isprime = ; efult: isprime = 0 ; ense en enmoule Mke your oe esy to re, unerstn, n reson out. EE 08A Leture 2 () W. J. Dlly n P. Levis 33 4-it Prime Numer Funtion in Verilog Coe Result of synthesizing esription using se moule prime ( in, isprime ); input [3:0] in; output isprime; wire n, n2, n3, n4; OAI3 U (.A(n2),.B(n),.B2(in[2]),.B3(in[3]),.Y(isprime) ); INV U2 (.A(in[]),.Y(n) ); INV U3 (.A(in[3]),.Y(n3) ); XOR2 U4 (.A(in[2]),.B(in[]),.Y(n4) ); OAI2 U5 (.A(in[0]),.B(n3),.B2(n4),.Y(n2) ); enmoule in[0] in[3] in[2] in[] U4 U3 n4 U2 n3 X0X X0X U5 X0 X0 n EE 08A Leture 2 () W. J. Dlly n P. Levis 34 n2 00X U isprime 7

18 Synthesis Reports **************************************** Report : re Design : prime Version: Dte : St Ot 4 :38: **************************************** Lirry(s) Use: GS30KA_W_25_.35_CORE. (File: /home/imgine/from_ti/gs30k_.3/sun5/synop sys/li/gs30ka_w_25_.35_core.) Numer of ports: 5 Numer of nets: 9 Numer of ells: 5 Numer of referenes: 4 Comintionl re: Nonomintionl re: Net Interonnet re: unefine (Wire lo hs zero net re) Totl ell re: Totl re: unefine **************************************** Report : timing -pth full -ely mx -mx_pths Design : prime Version: Dte : St Ot 4 :38: **************************************** Operting Conitions: Wire Lo Moel Moe: enlose Strtpoint: in[2] (input port) Enpoint: isprime (output port) Pth Group: (none) Pth Type: mx Des/Clust/Port Wire Lo Moel Lirry prime 2K_5LM GS30KA_W_25_.35_CORE. Point Inr Pth input externl ely r in[2] (in) r U4/Y (EX20) f U5/Y (BF05) r U/Y (BF052) f isprime (out) f t rrivl time (Pth is unonstrine) EE 08A Leture 2 () W. J. Dlly n P. Levis 35 Constrint File rete_lok "lk" -nme lk -perio 2 -wveform {0.7} set_lok_unertinty 0.2 lk set_fix_hol ll_loks() set_lo -pin_lo 5 {isprime} set_input_ely 0.5 -lok lk {in} set_output_ely -mx 0.8 -lok lk {isprime} EE 08A Leture 2 () W. J. Dlly n P. Levis 36 8

19 Test enh moule test_prime ; reg [3:0] in ; wire isprime ; // instntite moule to test prime p0(in, isprime) ; initil egin in = 0 ; repet (6) egin #00 $isply("in = %2 isprime = %",in,isprime) ; in = in+ ; en en enmoule EE 08A Leture 2 () W. J. Dlly n P. Levis 37 Test enhes use very ifferent style of verilog Initil sttements $isply Repet n other looping onstruts #ely Don t use these onstruts in synthesizle moules EE 08A Leture 2 () W. J. Dlly n P. Levis 38 9

20 Testing Result # in = 0 isprime = 0 # in = isprime = # in = 2 isprime = # in = 3 isprime = # in = 4 isprime = 0 # in = 5 isprime = # in = 6 isprime = 0 # in = 7 isprime = # in = 8 isprime = 0 # in = 9 isprime = 0 # in = 0 isprime = 0 # in = isprime = # in = 2 isprime = 0 # in = 3 isprime = # in = 4 isprime = 0 # in = 5 isprime = 0 EE 08A Leture 2 () W. J. Dlly n P. Levis 39 Wve output EE 08A Leture 2 () W. J. Dlly n P. Levis 40 20

21 moule prime_e(in, isprime) ; input [3:0] in ; // 4-it input output isprime ; // true if input is prime reg isprime ; egin sex(in) 0,4,6,8,9: isprime = 0 ;,2,3,5,7: isprime = ; efult: isprime = x ; ense en enmoule Summry To minimize logi Write K-mp Fin ll prime implints Pik miniml set of prime implints tht overs the funtion Hzrs (output glithes) n e eliminte y overing trnsitions Verilog Cn represent with se, sex, ssign, or struturlly Use representtion tht is rele n mintinle se for truth tles ssign for equtions Don t try to o the logi esign yourself Synthesis tool will o the optimiztion Test enhes hek tht implementtion meets its speifition Test enhes use ifferent style of Verilog EE 08A Leture 2 () W. J. Dlly n P. Levis 42 2