Lecture 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. PMOS Transistors in Series/Parallel Connection

Transcription

1 NMOS Trnsistors in Series/Prllel onnetion Leture 6 MOS Stti & ynmi Logi Gtes Trnsistors n e thought s swith ontrolled y its gte signl NMOS swith loses when swith ontrol input is high Peter heung eprtment of Eletril & Eletroni Engineering Imperil ollege London X Y Y = X if nd Reding: Weste & Rey pp189-10, -34 X Y Y = X if OR URL: E-mil: p.heung@i..uk NMOS Trnsistors pss strong 0 ut wek 1 Leture 6-1 Leture 6 - PMOS Trnsistors in Series/Prllel onnetion PMOS swith loses when swith ontrol input is low Stti MOS iruit si MOS omintionl iruits onsist of: omplementry pull-up (p-type) nd pull-down (n-type) X Y Y = X if N = + X Y Y = X if OR = PMOS Trnsistors pss strong 1 ut wek 0 Leture 6-3 Leture 6-4

2 Stti MOS Emple Gte: NN Leture 6-5 Leture 6-6 Emple Gte: NOR omple Gte We n form omple omintionl iruit funtion in omplementry tree. The proedure to onstrut omplementry tree is s follow:- Epress the oolen epression in n inverted form or the n-trnsistor tree, working from the innermost rket to the outer-most term, onnet the OR term trnsistors in prllel, nd the N term trnsistors in series or the p-trnsistor tree, working from the innermost rket to the outer-most term, onnet the OR term trnsistors in series, nd the N term trnsistors in prllel Leture 6-7 Leture 6-8

3 Emple Gte: OMPLEX MOS GTE Properties of omplementry MOS Gtes OUT = + (+) 1) High noise mrgins : V OH nd V OL re t nd, respetively. ) No stti power onsumption : There never eists diret pth etween nd () in stedy-stte mode. 3) omprle rise nd fll times: (under the pproprite sling onditions) Leture 6-9 Leture 6-10 Trnsistor Sizing Propgtion ely nlysis - The Swith Model for symmetril response (d, ) for performne = R ON Input ependent ous on worst-se ssume µ n =3* µ p (i.e. n-hnnel trnsistors hs 3 times the trnsondutne s tht of p- hnnel.) V R R p R p R p p R R p n R n L R n R n R n () Inverter () -input NN () -input NOR t p = 0.69 R on (ssuming tht domintes!) Leture 6-11 Leture 6-1

4 Wht is the Vlue of R on? Numeril Emples of Resistnes for 1.µm MOS or this proess, Wp = 3*Wn for the sme resistne Leture 6-13 Leture 6-14 nlysis of Propgtion ely esign for Worst se R p R p R n R n -input NN 1. ssume R n =R p = resistne of minimum sized NMOS inverter. etermine Worst se Input trnsition (ely depends on input vlues) 3. Emple: t plh for input NN - Worst se when only ONE PMOS Pulls up the output node - or PMOS devies in prllel, the resistne is lower t plh = 0.69R p 4. Emple: t phl for input NN - Worst se : TWO NMOS in series t phl = 0.69(R n ) Here it is ssumed tht R p = R n Leture 6-15 Leture 6-16

5 st omple Gte - esign Tehniques Trnsistor Sizing: s long s n-out pitne domintes st omple Gte - esign Tehniques () Trnsistor Ordering Progressive Sizing: ritil pth ritil pth In N MN M3 M1 M1 > M > M3 > MN M3 3 istriuted R-line In M In M In M M1 1 n Redue ely with more thn 30%! M1 1 () M3 3 () Leture 6-17 Leture 6-18 st omple Gte - esign Tehniques (3) Improved Logi esign st omple Gte - esign Tehniques (4) uffering: Isolte n-in from n-out Leture 6-19 Leture 6-0

6 Emple: ull dder Revised dder iruit X o S "0"-Propgte "1"-Propgte Kill o Generte S o = + (+) 8 trnsistors 4 trnsistors Leture 6-1 Leture 6 - Rtioed Logi Rtioed Logi Resistive Lod In R L epletion Lod In V T < 0 PMOS Lod In Resistive Lod R L N trnsistors + Lod V OH = V OL = R PN R PN + R L () resistive lod () depletion lod NMOS () pseudo-nmos In ssymetril response Stti power onsumption Gol: to redue the numer of devies over omplementry MOS t pl = 0.69 R L Leture 6-3 Leture 6-4

7 tive Lods Psuedo NMOS epletion Lod V T < 0 PMOS Lod isdvntges of previous iruit : lmost twie s mny trnsistors s equivlent NMOS implementtion. If there re too mny series trnsistors in the tree, swithing speed is redued. Try pseudo NMOS iruit:- In In depletion lod NMOS pseudo-nmos The pull-up p-hnnel trnsistor is lwys onduting. isdvntges: high d.. dissiption & slow rise time. Leture 6-5 Leture 6-6 Pseudo-NMOS NN Gte Improved Lods (1) M1 M 1 ul sode Voltge Swith Logi (VSL) Leture 6-7 Leture 6-8

8 Emple ynmi Logi There is nother lss of logi gtes whih relies on the use of lok signl. This lss of iruit is known s dynmi iruits. The lok signl is used to divide the gte opertion into two hlves. In the first hlf, the output node is pre-hrged to high or low logi stte. In the seond hlf of lok yle, the iruit evlutes the orret output stte. When Ø is low, Z is hrged to high. When Ø is high, n logi lok evlutes input, nd onditionlly dishrges Z. This iruit dds series resistne to the pull-down n-hnnel trnsistor, therefore the fll time is inresed slightly. This iruit is dynmi euse during evlution, the output high level t Z is mintined y the stry pitne t the output node. If Ø stys high (i.e. evlution period) for long time, Z my eventully dishrge to low logi level. XOR-NXOR gte Leture 6-9 Leture 6-30 Prolem with sding ynmi Logi MOS omino Logi Prolem with sding suh s iruit:- Inputs n only e hnged when Ø is low nd must e stle when Ø is high. When Ø is low, oth P1 nd P re prehrged to high voltge. However when Ø is high, dely through on the output P1 my erroneously dishrge P. Solution to the ove prolem:- dd n inverter to ensure tht the output is low during prehrge, nd prevent the net stge from evluting, until the urrent stge hs finished evlution. This ensures tht eh stge (t the output of the inverter) will mke t most single trnsition from 0 -> 1. When mny stges re sded, evlution proeeds from one stge to the net - similr to dominos flling one fter nother. isdvntges of domino logi:- Only non-inverting logi is possile, i.e. output lso high tive Eh gte needs n inverter; hene more trnsistors Suffer from hrge shring effet (onsidered lter) Leture 6-31 Leture 6-3

9 lternting dynmi logi (1) lternting dynmi logi () nother possile sheme is to use lternte n nd p logi loks s shown elow. In this sheme, eh lternte stge is pre-hrged high nd low. Eh stge uses lternte n nd p trnsistors to implement the gte funtion. Stge 1 mkes t most one high to low trnsition, while stge mkes t most one low to high trnsition for eh evlution. Sine the p logi lok will only hnge stte if input is low, this iruit ehves like the domino logi. slight vrition of this iruit is show elow, where n inverter is dded per stge to inrese fleiility. Here eh stge n drive either n or p loks nd oth low tive nd high tive logi n e implemented. Leture 6-33 Leture 6-34 Mking ynmi Gte stti Pss Trnsistor Logi inlly, y dding feedk pullup, we n mke the iruit stti. This iruit turns the originlly dynmi gte into stti gte euse the feedk trnsistor n mintin logi high level t the node Z for n indefinite length of time. Without this feedk trnsistor, the hrge stored t the node Z will eventully lek wy. n lterntive design style is to use pss trnsistors. The following is n emple of multipleer. omplementry trnsmission gtes re used here euse n-hnnel pss trnsistors will pss 0 logi level well ut, 1 logi level poorly. This is euse in order for the n-trnsistor to e ON, V gs must e greter thn V th. Therefore eh series n trnsistor will degrde the 1 logi level y V th. The opposite is true with p-hnnel pss trnsistors: 0 logi level is pssed poorly. Leture 6-35 Leture 6-36

10 Pss Trnsistor Logi with feedk Pss Trnsistor XOR gte This iruit uses only n trnsistors, therefore it is eonomil on trnsistor ount. In order to ensure tht the 1 logi level is pssed properly, p pull-up trnsistor is dded. This restores the 1 logi level t the input of the inverter. Pss trnsistor logi n sometimes e very eonomil in implementing logi funtions. or emple, n XOR gte n e implemented with just two trnsmission gtes:- Leture 6-37 Leture input NN Gte Stndrd ell Lyout Methodology Vdd In In 4 metl1 Well In In 4 In1 In In3 In4 signls Routing hnnel polysilion Leture 6-39 Leture 6-40

11 Two Versions of (+). Logi Grph PUN j i () Input order { } () Input order { } i j Leture 6-41 Leture 6-4 onsistent Euler Pth Emple: = +d i d d () Logi grphs for (+d) () Euler Pths { d} j { } d () stik digrm for ordering { d} Leture 6-43 Leture 6-44