Outline Last time: Deriving the State Diagram & Datapath (Cont.) Mapping the Datapath onto Control

Transcription

1 Outline Lst time: Deriving the Stte Digrm & Dtpth (Cont.) Mpping the Dtpth onto Control This lecture: Comintionl Testility nd Test-pttern Genertion Fults in digitl circuits Wht is test? : Controllility & Oservility Redundncy & testility Test coverge & simple PODEM ATPG Sequentil Test: Wht re sequentil fults? SCAN Design Outline Bckground: Role of Don't-Cres in Logic Synthesis Controllility & Oservility Optimlity, Redundncy & Testility The Sequentil Test Prolem Synthesis-Directed Sequentil Test Two Approches to Full Testility Effectiveness nd Limittions so fr.... Role of Don't-Cres in Logic Synthesis Role of Don't-Cres in Logic Synthesis Comintionl Logic f Comintionl Logic f f = cnnot e reduced further in isoltion cn never hppen Don't-Cre Set: D = ' ( + ) + ' ' Minimize f with respect to D Role of Don't-Cres in Logic Synthesis f = Fult Ecittion stuck-t

2 Fult Models Input or output pin (not entire net!) stuck t logic 0 or stuck t logic. Open circuit Cn mke comintionl circuit sequentil! Short circuit.. 0 Fult Propgtion stuck-t-0 The test is cue, not minterm...8 Optimlity & Redundncy in Comintionl Logic c d Circuit with redundnt fult: stuck-t-0 f = (.).(c+d).c' = (..c +..d).c' =..c.c' +..d.c' =..d.c' f c d Circuit with = 0 f = (.).c'.d f Pth-Oriented DEcision Mking [Goel, 98] () Assign ll (PI) to the vlue "don't cre" ( ). () Given n output signl nd desired vlue for the output, trce pth to the PIs to otin PI ssignment. (3) Simulte the PI vector to see if it sets up the desired vlue on the output. If so, terminte. (4) If the opposite vlue is set, ssign n opposite vlue to the PI nd re-simulte. If desired vlue is set, terminte. (5) If the output remins unspecified, repet the pth trcing to set nother PI, s necessry. Procedure continues until either: A successful PI ssignment hs een found (circuits not equivlent). All possile PI ssignments hve een ehusted c d Cover Etrction w ON cd OFF cd 0 0 d= d=0 c= c=0 =0 = =0 = Covers cn e generted with s mny "don't cres" in the present stte prt s possile. Testility nd Logic Synthesis Importnt Issue: Generting tests for circuits with redundncies is very difficult. Must use lgorithms which decrese the numer of redundncies or eliminte them completely during synthesis.....

3 Test Genertion for Finite-Stte Mchines Irredundnt comintionl logic does not imply 00% sequentil testility Sequentil Fults: Fults my not e ecited ("controlled") y primry inputs; fults my not e propgted to primry outputs ("oserved"). (PIs) Finite-Stte Mchines Comintionl Net-Stte Logic Ltches Comintionl Output Logic (POs) Moore Mchine (PIs) Finite-Stte Mchines Comintionl Net-Stte Logic Ltches (POs) Mely Mchine Emple Finite-Stte Mchine: Stte Trnsition Digrm / A 0/ /0 0/0 0/ B /0 0/ /0 E / C D 0/ Emple Finite-Stte Mchine: Encoded Sttes / / /0 0/0 0/ 00 0/0 /0 0/ / / 0 0 Stte Assignment Find inry encoding of sttes which minimizes the eventul re (or dely) of the FSM fter comintionl logic optimiztion of nd OL. FSM ENCODE OPTIMIZE Need to predict nd model the optimiztion Stte ssignment hs mjor effect on testility.....8

4 Emple Finite-Stte Mchine: Net-Stte Logic Mely Mchine t Time tn in ps(3)' ps()' ps() ns() ns() ns(3) PIn L(Sn ) PO n ps()' out in' ps() Sn is stte of ltches t time tn Finite-Stte Mchine s Iterted Arry Idel Iterted Arry PI PO PI PO PI n PO n PI PO PI PO PI n PO n L(S 0 ) L(S ) L(S ) L(S n ) L(S 0 ) n L(S ) L(S ) L(S n ) Fult is present in ll copies of Fult my msk ecittion or propgtion More likely, fult my cuse net-stte N to e invlid stte Nf. In n idel sitution, the would e optimized seprtely for ech possile stte trnsition! Ech lock would e mde prime nd irredundnt seprtely..... PIs Sequentil Circuits: Controllility & Oservility Comintionl Net-Stte Logic Ltches POs A test: 00 : 00 : 00 0:0 : 0 0: Scn Design Mke ll flip-flops scn (i.e. direct red nd write ccess) All inputs to the comintionl logic cn e set nd ll outputs cn e red. The sequentil testing prolem ecomes comintionl testing prolem. "Overkill" in virtully ll cses. Are nd time penlty; often longer testing time. But scn cn e inserted utomticlly

5 Synthesis Procedure for Fully-Testle Non-Scn Finite-Stte Mchine (Devds, et.l. 988) (PIs) N Ltches Output Logic (POs) Prtition into single-cone circuits Single stuck-fult correct & incorrect net-stte differ y ectly one it. Perform stte ssignment such tht ll sttes differing in one it ssert different outputs one-step propgtion Synthesis Procedure for Fully-Testle Non-Scn Finite-Stte Mchines Given stte-trnsition grph (STG) of FSM, 00%-testle logic-level implementtion of the mchine is produced No scnnle ltches required Uses prtitioned logic pproch nd constrined stte ssignment Smll penlty Cscded Finite-Stte Mchines Coupled Finite-Stte Mchines PIs POs e.g. controller Is it possile to synthesize cscde of FSM's such tht ll emedded fults re detectle non-scn from the eternl inputs only? Wht is the penlty in rel cses? PIs e.g. dt pth POs....8 Nme sse tk plnet scf Emple FSMs Sttes Edges Nme sse tk plnet Constrined Stte Assignment (single cones) Fult Gtes Cover (%) Optimized only TPG time 0s s 04s 33s Optimized nd Testle Fult Gtes Cover (%) scf m Output logic lock contined comintionl redundncies TPG time 5s 4s s 4s s

6 Nme sse tk plnet scf Constrined Stte Assignment (single cones) Optimized only Normlized Gtes Are Optimized nd Testle Normlized Gtes Are Effect of Gte Dupliction in Stndrd-Cell Lyout logic gtes routing trcks Dupliction of gtes reduces routing congestion nd my sve routing trck. The re of routing trck is usully >> the re of gte. Reducing mimum gte fnout my improve performnce...3 Emple Finite-Stte Mchine with Fult d in ps(3)' ps()' ps() ps()' in' ps() stuck-t-0 ns() ns() ns(3) out Emple Finite-Stte Mchine Effect of Fult d / / /0 0/0 0/ 00 0/0 /0 0/ / / N f N, where N f is vlid stte Emple Finite-Stte Mchine with Fult g in ps(3)' ps()' ps() ps()' in' ps() γstuck-t- ns() ns() ns(3) out Emple Finite-Stte Mchine Effect of Fult g / / 0/0 0/ /0 0/ 00 /0 0/ 0/0 /0 / / N f N, where N f is invlid stte (stte splitting hs occurred)

7 Use of Etended Don't-Cre Set to Gurntee Testility (Devds & Keutzer, '90) Etrct the Stte Grph Anlyze the Stte Equivlences Generte the Etended Don't-Cre Set Informtion Optimize for Prime nd Irredundnt Network Under the Don't-Cre Set Chnged? Fully Testle Nme e e s key Emple FSMs 8 6 Sttes Edges Results of Synthesis Procedure Results Using Etended Don't-Cre Sets During Synthesis Nme e Ltches 3 Gtes 3 Fult Cover (%) 9.9 OptimizeTPGidentify remove redund. redund. 0.5s.0s.s.0s Nme e Stte Enum. 0.5s Optimize Time 0.5s TPG.s Logic Optimize Fult Cover (%) 00.0 e s 4s 6.s.8m e 6.5s.4s 4s 00.0 s s 303s 4.0s 303s s.0s 6.s 98s s 33s 4s >h 0.s 5.5s 4s key s m.m >h key 4.6s.8s m 00.0 %-5% smller designs thn without don't-cre sets Test Procedure: Scn Test Procedure: Non-Scn Npi Npo Npi Npo Nl Nl+Npi input its per test One tester clock tick per it Nl Npi input its per test One tester clock tick per Npi its..4..4

8 Wht Aout Testing Time? (Ghosh et. l. 989) Numer of Test Bits Nme Scn S for T e 4,03 3,8 e 9,696,50 e3 55,680 34,90 des 868,86 key,856 5,968 viteri 5,68 4,950 Viteri Chip Prt of system for rel-time continuous speech recognition developed y Prof's. Broderson & Rey t Berkeley. Lrgest chip in the chip-set for the system. Implements the Viteri lgorithm for mpping n oservtion (some speech) into the most likely sequence of sttes in the speech model eing used. Chip Sttistics: 5,000 trnsistors 6 inputs, 44 outputs. 0.5 mm die size Wht Aout Testing Time? A Revolution in Test in the Lte 990s? Tester Cycles Test Bits Nme Scn S for T Scn S for T e 4, ,03 3,8 e 9, ,696,50 e3 55,680,033 55,680 34,90 des 8, ,86 key,856 03,856 5,968 viteri 5,68,045 5,68 4,950 Cn Synthesize Gurnteed Fully-Testle, Non-Scn Implementtion of Any Collection of FSMs. Almost lwys requires fewer gtes or less re thn full scn. Almost lwys requires shorter tester times (in mny cses y one or two orders of mgnitude) thn full scn. Cn hndle fults in emedded mchines, mchines with feedck, etc. - ny topology of interconnected mchines. Test ptterns generted s y-product of the synthesis, so synthesis time represents sving of ATPG time Synthesis-Directed Sequentil Test Entire-chip full-scn-sed design-for-test will e osolete y the end of the 990s Will e used for some very-specific on-chip structures (e.g. ROM, RAM, mye Dtpth) nd for some chip oundries. Circuit-structure-specific nd BILBO-like test styles will continue to e used for go-nogo tests. Architecturl memory structures will continue to e ccessile directly for the pins. Synthesis-Directed Sequentil Test Test will e incorported directly into the synthesis process Gurnteed fully-testle non-scn or prtilscn designs will e produced y the synthesis process. A complete set of test ptterns will e yproduct of the process