Algorithms for MIS Vector Generation and Pruning

Transcription

1 Algorithms for MS Vetor Genertion nd Pruning Kenneth S. Stevens Eletril nd Computer Engineering University of Uth Slt Lke City, Uth ABSTRACT Florentin Drtu Synopsys, n. Advned Tehnology Group Hillsoro, OR 97 gnoring the effet of simultneous swithing for logi gtes uses silion filures for high performne miroproessor designs. The min reson to omit this effet is the run time penlty nd potentil overonservtism. Run times re diretly proportionl to the vetor sizes. Effiient lgorithms re presented tht prune the multiple input swithing (MS) vetor set to worstse overing using oolen logi strtion of the gte. This nonphysil representtion redues the vetor size to pproximtely n vetors for n ninput gte. This is effetively the sme vetor set size s the optiml single input swithing vetor set. There re no errors for 88% the simultions using MontyCrlo overge on 9nm stti lirry, nd the mgnitude of the errors re less thn % on verge. go i /.... Slk (FO). Figure : MS Mximum Dely Pushout Effet. NTRODUCTON Aurtely modeling silion my seem fesile onsidering the progress mde in omputtionl power nd timing nlysis models nd lgorithms. Unfortuntely, exponentilly lrger iruits re eing uilt in silion tehnologies tht inresingly emphsize unwnted effets suh s short hnnel, pitive oupling, indutne, proess vritions, et. As result, ll timing nlysis tools still hve to trde ury for run time. Multiple input swithing (MS) is very good exmple of n importnt effet tht n sustntilly modify timing, ut is ommonly ignored in stti timing tools. This dely vrition n e mesured in ll gtes with more thn one input, s demonstrted in Figure. f in swithes long efore inl, the dely from inl to the output remins onstnt. However, s the seprtion etween inl nd in pprohes zero, the dely from inl to the output n inrese sustntilly. Figure presents the mximum dely s perentge of the single input swithing (SS) dely of inl. Oserve tht when the inputs swith onurrently (sme % point) the dely pushout is lrger thn %. t is not diffiult to find ses where the dely vrition from SS to MS is s high s 78%. Given suh signifint MS dely vrition, it is diffiult to lim tht stti timing nlysis lwys omputes n upper dely ound. ndeed, MS dely pushout hs een onfirmed s soure of filure in high performne miroproessor silion. MS hs lso een shown to signifintly hnge the performne properties of ertin iruit onfigurtions[]. The series/prllel reltionship etween trnsistors is the primry use of dely vrition due to simultneous swithing. Seond order effets inlude trnsistor sizing nd ordering, hrge shring, voltges on nonswithing trnsistors, legging, internl node voltges, nd prsiti pitne due to lyout onfigurtions. The urrent stte of the rt is to prune multiple input swithing vetors sed on the physil lyout nd topology of the gte [,,,, ]. This pper presents signifintly different pproh in tht no expliit topologil informtion is used to rete vetors. The topology of trnsistors in gte is inexorly relted to the logi funtion of the gte: AND'ed literls require series trnsistors nd OR'ed literls must e in prllel devies. Hene, given oolen eqution for gte, one n esily extrt the most signifint topologil reltionship of trnsistors tht use MS dely vrition. This pper tkes the novel pproh of pplying pure logi to rete vetors sed on the implied topologil reltionships. This purely logil pproh, if suessful, hs numer of dvntges. The lgorithms re very effiient nd hve een pplied to the MS hrteriztion of lrge miroproessor design using trnsistor level stti timing nlysis (STA). Sine vetors re generted diretly from logi definition, the lyout nd shemtis re not needed in ellsed design (CBD) methodologies. The vetor genertion lgorithms re very flexile nd orretly generte vetors for stti gtes, domino logi, sense mps, nd other lsses of gtes. Finlly, if more ury is required, this pproh n rpidly rete initil vetor sets for further pruning sed on more om Permission to mke digitl or hrd opies of ll or prt of this work for personl or lssroom use is grnted without fee provided tht opies re not mde or distriuted for profit or ommeril dvntge nd tht opies er this notie nd the full ittion on the first pge. To opy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior speifi permission nd/or fee. CCAD', Novemer 9,, Sn Jose, CA Copyright ACM 9989//... $.. 8

2 . First Order Affets plited topologil serhes tking into ount trnsistor sizes, prsitis, internl node voltges, et. Certin topologil reltionships re not exposed in the logil domin, suh s trnsistor sizing nd ordering, legging, et. This n result in overge errors in the vetor set. Therefore ommeril 9nm stti lirry ws evluted to determine the qulity of the vetor set produed y these lgorithms. There re two spets of vetor pruning: logil (funtionl) onstrints nd topologil onstrints. The omplete vetor set n is sustntilly pruned y the simple funtionl requirement tht eh input vetor must toggle n output. The ' stle vetors re not useful for ny gte nd re deleted. The remining, ' vetors re evluted sed on the logi funtion of the gte, nd vetors tht don't swith n output re lso removed. Topologil onstrints nnot e used to redue the vlid single input swithing vetors remining from the nn ndidtes. These vetors require physil informtion, suh s trnsistor ordering, legging, devie sizing, prsiti hrge shring, et. However, when multiple signls swith, topologil reltionships lrgely determine if the gte will speed up, slow down, or e reltively unffeted y MS in omprison to single input swithing on one of the input pins. Dely vrition in gte due to simultneous swithing is primrily ffeted y the topologil seril nd prllel nture of gte. Tke the NAND gte of Figure. f the two inputs fll onurrently the iruit will speed up onsiderly. This ours euse the two PMOS trnsistors re in prllel nd effetively doule the drive of the gte. f the inputs rise onurrently then the output will e delyed. This is due the inresed miller nd ody effet in the series pulldown stk. This llows us to mke firstorder pruning of the the MS vetor set sed on logil informtion. The lgorithms in this pper pply to ny single diffusion onneted network (DCN) suh s stti nd rtioed CMOS gtes. Cells with pss gtes s inputs re not dmitted. Cells with multiple DCNs re not llowed exept for few speil ses: when seond DCN is prt of feedk yle, or it is n inverter tht is on n output. While these lgorithms ould e pplied to some ells with multiple DCNs (some XOR implementtions), the disprity etween topology nd logi ould introdue signifint error. These two restritions do not seem to represent mjor limittion for mny stndrd gte lirries. The lgorithms presented here support full MS vetor genertion from to n inputs swithing for n ninput gte. Additionl flexiility is provided euse the lgorithms ept n upper ound on the numer of inputs tht re llowed to swith t the sme time. This dds flexiility in the run time/ury trde off in lgorithms tht pply these vetors to stti timing nlysis. As expeted, the more inputs tht re llowed to swith simultneously, the lrger the numer of potentil MS vetors ut the smller the proility of suh se tully ourring in the iruit. For lrity, we hve set this prmeter to limit multiple input swithing to signls in the reported results. Vetor genertion proeeds through three steps:. Crete redued superset of vetors.. Prune sed on gte funtionlity.. Prune to the worstse overing.. VECTOR SETS AND RUN TME Stti timing nlysis trdes off some ury through pplying worstse swithing onditions for onsiderle improvement in run time. The run time for lirry hrteriztion is sensitive to two prmeters: the numer of vetors nd the numer of simultions required for every vetor. Exhustive simultion to hrterize ny ninput gte requires 'kp simultions (kp simultions per vetor for eh of the n vetors), where p is the numer of simultion prmeters for k simultion points per prmeter. Exhustive SS simultion requires n'kp simultions. This lloons to ( nr ) kp simultions for MS, where p will likely e lrger thn for SS hrteriztion. To redue the run time nd CBD tle size, model order redution is pplied to lirry hrteriztion reduing p to two prmeters: input slope nd the output lod modeled s effetive pitne Ceff. The numer of simultion points k for eh prmeter is hosen suh tht tle with simple interpoltion etween these points gives suffiient ury ross the eletrilly vlid slope nd Ceff rnge. Five simultion points re usully suffiient (est, worst, nominl nd the two points in etween), resulting in kp simultions per vetor. Under MS hrteriztion, eh input n hve n independent slope nd dely offset from the ltest rriving signl. f oth of these dditionl prmeters re modeled for three swithing signls, then p n + 7, requiring 78, simultions per vetor nd sustntilly lrger interpoltion tle. New model order redution tehniques n e developed to redue the numer of MS prmeters nd required simultions. However, run time remins highly sensitive to vetor sizes. Trnsistor level STA does not need ny prehrteriztion. The tul slopes, lods, nd signl seprtions re used for simultion. However, ll pplile worstse vetors must e simulted on every gte in the design. The minimum numer of SS vetors required to simulte n ninput gte is n with eh input pin rising nd flling. Our lgorithm omputes, for stti ell lirry, n verge of pproximtely n MS vetors per gte. DEFNTON. A simultion vetor v onsists of pir of oolen nues where eh literl vlue is memer of the set {, }. Thhis pir is represented s single trnsition vetor where eh literl in the nue is memer of the set {,, r,f}. f the literl is unhnged in oth vetors it retins its vlue of or. f the vlue in the first ue is nd the seond is, then the literl vlue in the trnsition ue is r (rising), otherwise it is f ( flling literl).. LOGCAL GATE REPRESENTATON A gte representtion is reted using oolen logi with the struture D {,, B, L, o, s, r} where is set of input literls, the output literls, B the feedk nodes, nd L the inputs to the DCN where L C U B. Boolen funtions s nd r operte over the literls in L nd produe output o(v) C {,, *} V outputs o C. The lgorithms rete vetor set v C V mpping eh literl in L to the set The exhustive n vetors n e roken down into three lsses: nn SS vetors, (n n )n MS vetors, nd n stle vetors. The nn SS vetor set for two input gte is {Or, lr, Of, lf, ro, rl, fo, f }, while the (n n )n MS vetor set is {rr,fr,rf,ff}. The n stle vetors re {,,, }. 9

3 {,, r, f, }, where '' is don't re vlue nd 'r' nd 'f ' re rising nd flling trnsitions respetively. This model ssumes CMOS proess. All pssive devies re strted into either onduting terminls or open iruits with nodes eing the ondutive onnetions etween terminls of the trnsistors. The model uses gtes tht n e extrted from design s single DCNs where ll soure nd drin terminls re ll onneted through the soure nd drins to power nd ground. A feedk node is DCN input tht n e tred k to n output of this DCN through t most one other DCN. Feedks re of two types: diret feedks, suh s re found in sense mps, or keeper feedks s re found in domino gtes. These signls hve speil ehvior in our lgorithms euse they re oth inputs nd outputs to the DCN nd hene nnot e freely given stte ssignments like unonstrined inputs due to their output dependeny. v C r L Figure : Stti Gte o ( + ) to mke worst se vetor overings for mxdely (pushout) nd mindely (pullin).. Remove Conflit nd "tristte" Cues A superset of the vlid vetor set is reted from the minterms in the s or r funtions fter removing the onflit ues z, nd keeper ues. Keeper ues re ll minterms tht ontin the output s literl. Suh ues only retin the previous stte, so they re not used for vetor genertion. Keeper ues re removed from s nd r y pplying the Shnnon oftor on output o C ) to the oolen funtions, s so nd r,. This leves the ues whih n tively swith the output up or down. The onflit ues re removed through set sutrtion, giving simplified rising output funtion s' s z, nd the flling funtion r r z. This gives set of minterms ross whih we n iterte to generte the superset of SS nd MS vetors. These vetor sets re pruned nd refined in Setion using the full logi funtion to rete the finl vlid vetor set. The funtions s nd r re oolen representtions of the trnsistor network etween n output nd the power ril, nd the output nd ground respetively. The definition for s nd r supports rtioed gtes nd keeper feedks y strting the pullup nd pulldown pths s demonstrted in Eqution. A week pullup trnsistor will e ignored if it is turned on t the sme time s strong pulldown. J pullup <K pulldown t pullup pulldown pullup > pulldown DEFNTON. The set funtion s is Vo C {, *}, { : s(x) } sserts when the output is high or unknown (*). The reset funtion r is Vo C {O, *}, {x : r(x) } sserts when the output is low or unknown. The onflit set z, is {snr} sserts when oth s nd r re sserted nd the output is unknown. The ternry funtion for o is fully overed y s U r. f. Creting Complete SS Vetor Superset () This lgorithm itertes ross every minterm in either the nonil SOP s (when output ot rises) or r. The superset of SS vetors is reted y setting eh literl in every ue to rise or fll. The preondition of trnsition vetor *v is the strting oolen ue generted y mpping r to nd f to. The postondition v retes the destintion ue swpping nd in the preondition. There re mny wys to struturlly onnet the gtes, nd there re mny oolen representtions. However, in this work we only use the nonil sum of produts (SOP) nd produt of sums (POS) or onjuntive norml form. Thus we get single logil representtion tht overs different topologies. Both ellsed nd trnsistor level flows re supported. For CBD, the funtions s nd r must e defined, nd the signls sets,, B, nd L re either provided or reted. Our ode utomtilly retes D from lyout or shemtis for the trnsistor level flow. The desription of the trnsistor level ode is omitted for revity. if ot then f ss z else f r z V C f V li C L if li C A li, B U rete v: r j i A [i] V o A ot f j i A [i] O V j o A ol v [j] j i8 A j C A [j] O j i A [j C A [j] A j 7y o p j This proedure pplies Shnnon deomposition to remove the keeper, nd sutrts onflit minterms. A superset of SS vetors re generted for every remining minterm ue C f. A new vetor is reted for eh literl in the ue tht is not n output or feedk. The vetor is the size of the rdinlity of the input to the DCN L. For eh vetor, the literl li in v is set to rising if the literl is sserted in the ue, else it is set to fll. f the output o is n element of the vetor, then it is set to rise (fll) when using funtion s (r). For ll other literls lj, the vlue of v[j] is set to or if the literl lj is in the ue sed on the literl's vlue.. CREATNG POTENTAL VECTORS This setion desries the genertion of set of potentil vetors using logil nd topologil informtion provided y the logil ehvior of the gte. Some gte topology is enoded in the nonil SOP formt. Eh minterm enodes the series reltions etween trnsistors. Prllelism exists etween literls in different minterms. The lgorithms use these topologil implitions

4 f the literl lj is not in the ue then its vlue in the vetor is don't re. Refer to the gte in Figure. The reset funtion r {, }, the onflit nd feedk sets z, nd B re empty, the output set {o}, nd the input literls re L {,,}. This produes the three vetors {r,r,lr} with vetor signl order of "". V C C f ll e(v,,,, ) if i else v[i] jh i]. Complete MS Vetor Superset [i] MUv e(v,, i +,k, n) if k < n A li C v[i] {r [i] The MS vetor superset set is generted from the SS vetors. All possile vetors re reted y llowing don't re nd ontrolling vlues to rise or fll s permitted y their minterm ues. MS vetors n hve nywhere from to n literls in the set L swithing where < n < L. These lgorithms tke prmeter n to limit the mximum numer of signls tht n swith onurrently. This limit is set to in the results of this pper without loss of generlity. The MS vetor set M (initilized ) is lulted with the reursive funtion g(v, i, k, n) where v is SS vetor, i is the literl index, nd k is the urrent swithing ount, n is the mx swithing eiling: f[i] e(v,,i+,k+,n) This lgorithm retes trnsition ues y first removing keeper nd feedk ues with Shnnon deomposition nd sutrting the onflit set from either the rising or flling outputs. The funtion e is then lled for eh minterm ue. At the end of the reursive itertion, the vetor is dded to the set only if it hs t lest two trnsitioning literls. The vetor index is set to don't re if its orresponding literl is not in the ue. Otherwise it is set to high or low sed on the literl's vlue, nd reursive ll is mde inrementing the literl index. When the MS eiling hs not een rehed, the urrent literl is set to rising or flling, sed on the vlue of the literl in the ue. A reursive ll is then mde inrementing the literl index nd trnsition ount. Using the reset funtion r {, } from Figure, the mx dely MS vetor set {rr} is reted. For ll vetors v in SS vetor set, ll g(v,,, ): if i else L then when k >, M L then when k >, M M U v g(v, i +, k, n) if v[i], {r,f} A k < n if v[i] 7& g(v v[i] r,i+,k+ i,n) if v[i] 7? g(v v[i] f,i+,k+ i,n). Minimum Dely MS Vetor Superset To the first order, the minimum dely ours when multiple pths to power or ground re onurrently enled. The minterms in POS formt rete ll prllel isetions in the gte topology. The lgorithm for lulting mximum pushout in Setion. n e used when slightly modified to rete the mximum pullin. Following the Shnnon deomposition on funtions s nd r the funtion f is trnslted into POS formt f The reursive funtion e is slightly modified into funtion e whih reples the initil vetor ssignment with its dul s shown in Eqution ; if the literl is sserted (unsserted) in the ue it is unsserted (sserted) in the vetor. This ensures tht the minterm is only enled y rising or flling literls. For eh SS vetor v, reursive ll is mde using the next literl i. When we hve iterted ross ll literls in the vetor, we dd the MS vetor to our vetor set if it hs t lest two signls swithing. f the urrent literl is not rising or flling nd the swithing eiling hs not een rehed, then we reursively ll this funtion on the next literl up to two times, inrementing the MS ount k. f the vlue of the urrent literl in the SS vetor is not zero, we set the urrent vlue in the MS vetor to rising nd reurse. f the vlue of the literl is not one, we set the literl to flling nd reurse. The omplete MS pulldown vetor set for the iruit of Figure is {rr, rf, rr, rf, f lr, frl, rr}. This ws reted from the three SS vetors in the exmple from Setion.. v[i]. Mximum Dely MS Vetor Superset To the first order, the mximum dely for DCN operting under MS ours when trnsistors in series stk re swithing. The topologil informtion in the SOP formt is used to rete set of vetors overing ll omintions of series trnsistors tht n simultneously swith. The funtion e(v,, i, k, n) is lled reting trnsition vetor v for the set or reset funtion. The funtion produes the MS vetor set M (initilized ) using minterm ue, literl index i, trnsition ount k, nd MS onurreny eiling of n. ( h li fc [i] [i] () The POS formt for the pulldown of Figure is r {, }, equivlent to the CNF form ( + )( + ). The mximum dely vetors for this funtion re {rr, rr}.. PRUNNG POTENTAL VECTORS Four ndidte vetor supersets were generted in Setion. Eh vetor set is pruned for funtionl vlidity using the s nd r funtions. Further optimiztions or unique onstrints for mximum or minimum dely effets re pplied when pplile. Pruning n e lled onurrently with vetor genertion to inrese effiieny in n implementtion. ot f (8(oUB) n SB) z, else f (r(oub) n rb) z if

5 . Funtionl Vetor Pruning funtion Every vetor in vetor set must meet the following three funtionl orretness onstrints. While these ensure funtionlly orret trnsition, they do not require the trnsition to e glithfree or stle t intermedite vetor vlues.. orret initil voltge: if ot then f (v) e d + d +d + + d + d + d ( + )( + d) d + e + de + de + de +de +de ( + )(d + e) else f (v). vetor ends in onduting stte: f ot then ve C so z else ve C r z,. feedks not ontrolling: when li C B then vl[i] *v[i] else vl[i] v[i] A if ot then f(vi) else f(v/) This requires tht rising vetor must strt low, end high, nd nnot e ontrolled y the feedks. This will prune the exmple SS set generted in Setion. to the finl flling set {ro, ro, Or, Olr}. Don't re vetors re fully instntited for simultion, so this gives in five pulldown (ot) vetors.. Funtionl MS Vetor Pruning Funtionl pruning is suffiient for the omplete SS nd MS vetor sets when evluting stti gtes. An dditionl ondition must hold when evluting dynmi gtes with feedk through seprte DCN. The uxiliry DCNs must lso e funtionlly orret suh tht the pre nd postonditions generte the pproprite logi levels. This is not neessry if the keeper gte is n inverter, ut is neessry for more omplited keeper logi. ( + )( + d) (e + f) + def All vetors Averge. Mximum Dely Vetor Pruning input pins Full Full SS MS sets sets MS mxdel OT ol 8 MS mindel oj ot Tle : Vetor results for 9nm stti ell lirry. The funtion of the ell is listed with input pin ount, the omplete single input swithing (SS) nd multiple input swithing (MS) vetor set sizes for rising nd flling outputs sets, the worst se mxdely vetors for rising outputs ot nd for flling outputs ol, nd the worst se mindely vetors for outputs tht fll nd rise. MS vetor dely is mximized when ll swithing trnsistors re topologilly onneted in series. Sine the potentil vetor set ws generted sed on single minterm, it is possile tht multiple minterms n e onurrently enled, speeding up the gte. An dditionl onstrint is therefore dded to ensure multiple minterms re not sserted. The funtion g(v, f) is true when only one minterm in funtion f is sserted for the vetor v. A seond pruning ondition ensures tht the vetor nnot enle the output until ll rising or flling signls hve swithed. This holds if the vetor trnsitions properly when ll ut one of the rising or flling literls re set to don't re in the preondition of the vetor.. mximl drive: if ot f s else f r v[i] then fii C fl, V fi f f if v[i] fi, C fi V fi fi, Z V v[i] if then This prunes the four possile vetors for our exmple to the finl set {rrl, rlr}. single sserted minterm: if ot g(v, s) else g(v, r,). RESULTS. stle until output: f ot f r z, else f s z. f(.v/) : V v[i] C {r,f}: (V v[j] i 7 j A v [j] e {r, f} then vl[j] ) The vetor genertion nd pruning lgorithms were run on different ells onsisting of different logi funtions. There were two different input NAND nd NOR For Figure only vetor {Orr} holds for flling outputs. topologies.. Minimum Dely Vetor Pruning. Vetor Set Anlysis Eh vetor is set to deliver mximum urrent to the output to minimize the dely. Eh potentil minimum dely vetor from Setion. is expnded to fully instntite don't res. The vetor is kept if for eh vetor literl tht is, the funtion is positive unte (ft. C fi,) or not negtive unte for tht literl. Likewise, for eh vetor literl tht is, the funtion must e negtive unte (fi C fii) or not positive unte for tht literl. Tle summrizes the size of the vetor sets for eh of the ell fmilies. The logi funtion of the gtes re shown in the first olumn. The gtes rnged from two to six input pins, s shown in the seond olumn. The third nd fourth olumns show the size of the omplete set of single input swithing nd multiple input swithing vetors tht toggle the gte's output. The full set sizes were the sme for rising nd flling outputs. The next two olumns show the set

6 Clss Full SS Full MS mxdely mindely Vetors for flling output ot MS Pushout Coverge roo rol rlo Orl Olr rro rrl rfo ror rof rlr Orr Tle : Pruned worstse vetors for iruit of Figure Vetor lss optiml SS mxdely mindely Full set se / rel % Orr rrl rlr Redued set se / rel Redued Perent 8% 9% 9% C U 9% E 9% 8% Tle : Vetor Set Sizes from Tle. Comprison of totl vetor set sizes etween the minimum SS vetor set seline nd the worst se MS vetor sets. Full sets nd SS set multiplied y two for omined rise nd fll omprison. Minimum SS set size ssumed to e equl to # input pins. g Perent Error Figure : Grph of mxdely (pushout) errors. MS Pullin Coverge 7 sizes for worst se mxdely pushout vetors for flling nd rising outputs. The lst two olumns show the set sizes for worst se mindely pullin for flling nd rising outputs. The finl two rows shows the totl vetors nd the verge per gte. The minimum SS vetor set size is equl to the numer of input pins for ll ses (min nd mx rise nd fll dely), sine t lest eh input pin must swith. Note tht some of the MS pruned vetor sets ontin no entries suh s the rising mxdely for the NAND gte in the first row. n suh ses the pruning lgorithm hs determined there re no MS vetors tht will dely the output euse there re no trnsistors in series. The omplete set of vetors for the flling output for the exmple gte of Figure re shown in Tle. This gte ( + ) is in row of Tle. The vetor sizes diretly impt the lirry hrteriztion for stti CBD timing nd runtime for trnsistor level timing. Tle shows the verge numer of vetors for these gtes. This ssumes the minimum SS vetor set needing single vetor per input pin n e found tht suffiiently overs the worst se dely for ll slopes nd lods. Note tht the MS worst se mindely vetor ount is smller thn the SS vetor size. The mx dely MS vetor size is out % lrger thn n optiml SS vetor set. The optiml SS vetor set hs n 8% redution in vetor size from the full vetor set. The worst se MS min nd mx dely vetor sets show 9% nd 9% redution from the full vetor set respetively. T > ffl m % 9% ), * E LL 9% N m mm.% n ) 8%.7%.%.% Error s perent of yle time Figure : Grph of mindely (pullin) errors. erge. The worst se dely nd its vetor were reorded for the omplete vetor set nd the pruned vetor sets for eh of the simultion runs. This loop ws iterted, times for pproximtely million simultions. The result for the full set ws ompred ginst the pruned set to determine if the worst se ws overed. f not, the size of the error ws lulted. The dt for these runs is plotted in Figures nd. The error for the mxdely pushout is reported s perentge differene from the tul worst se. For mindely, the vlue is normlized y dividing the error y n ggressive lok frequeny for this tehnology node. This shows tht the lrgest mx or min delys were ontined in the redued vetor set in pproximtely 88% of the simultions. n pproximtely 9% of the ses the error ws zero or reltively insignifint (within %). This shows tht the utomti pruning lgorithm did good jo of overing the worst se. Simultion Results A simultion study of the gtes ws performed to determine the qulity of the redued MS vetor set. The fully extrted prsitis for eh ell were used in the simultions. Eh ell hd rnge of sizes to support vrious output lods. Monte Crlo nlysis ws performed y rndomly piking one of the ell types, vlid output lod nd n ssoited ell size, nd n independent input slope for eh swithing input. The % trnsition point for ll inputs were ligned. A omplete simultion run for rndom prmeters ws performed on the ell for the full rising nd flling MS vetor sets x 79.8 simultions per ell on v vetors. The vetor tht reted the worst se delys for eh rndom slope nd lod omintion were reorded. Just s in the SS se, single vetor is not suffiient to over the worst se delys in gte for ll vlid slope nd lod omintions. Tle shows the verge numer of MS simultion vetors required to orretly over the worst se ondition. An verge of two vetors per ell is required to over worst se onditions for flling trnsitions; slightly less for

7 size s the minimum singleinput swithing vetor sets. Eh set n e hrterized nd used independently. The ury of the redued vetor set ws evluted ginst the omplete MS vetor set using Monte Crlo simultion. Rndom input slopes, output lods, nd ell sizes were seleted. The redued set showed stisftory ury, s 88% of the simultion sets were error free, nd in 9% of the ses the error ws deemed insignifint. The mximum error ws less thn %. Exmintion of the erroneous vetors indites tht the errors ll pper to e used y seond order effets suh inresed short iruit urrent from glithing ues. The ptterns of the error vetors from this study indite tht it my e possile to improve the error hrteriztion of the redued within the logi frmework y dding n dditionl smll set of vetors. n mny ells two or more vetors exhiited the worstse delys for different rise time nd lod. However, this still only inluded frtion of the worstse vetor sets s only % were needed to model the worstse delys. This leves signifint room to improve this redued vetor set using either logil or struturl methods, or omintion of oth, if one is only serhing for the worst se min or mx dely for ell. )} d Figure : Gte f + d + + d rising. Only onethird to onefourth of the redued MS vetors generted y this lgorithm were needed to over the worst se onditions. This implies tht other mens, suh s some struturl pruning following the logil pruning, my e useful mens of further reduing vetor sets. Eight of the ells ontined one or more slope, lod, nd sizing ondition where the worst se required vetor outside the pruned set. All errors ourred on the rising outputs; none on flling outputs. One gte ontined only single vetor with n error of less thn.%. Two ells ontined errors in ll of their rising outputs. Of the erroneous mxdely simultion sets, ll ut one were from vetors with oth rising nd flling literls. The lgorithm for pruning MS vetors did not onsider these vetors s ndidtes, nd therefore they were not inluded in the pruned set. The mehnism tht ppers to hve resulted in these filures is demonstrted with the iruit of Figure, with the set funtion s { + d} nd the reset funtion r { + d + + d}. One worst se vetor is lrf. Note tht ue is initilly pulling the gte low, nd the other reset ues re off. Cue desserts nd ue d is sserted to pull the gte high. However, during this trnsition, reset ue hs signl rising nd flling. This retes glith on the output of this ue s this term prtilly sserts during the trnsition, souring urrent tht fights the pullup ue d. This ondition is exerted with strong NMOS devies ompred to the PMOS, prtiulrly with slow trnsition times. 8. ACKNOWLEDGMENTS The ulk of the work nd ll of the results presented here were otined while the uthors were with ntel Corp., Strtegi CAD Ls, Hillsoro Oregon. 9. REFERENCES [] V. Chndrmouli nd K. A. Skllh. Modeling the [] [] 7. SUMMARY An lgorithm ws desried tht uses logi to represent iruit topology nd utomtilly rete full nd worstse multiple input swithing vetor sets. This lgorithm ws tested on modern stti ell lirry t 9nm design node. The lgorithms presented here generte the full set of vetors tht will flip the output under oth single nd multiple input swithing onditions. This set is then utomtilly pruned to generte the worstse rising nd flling min nd mxdely vetor sets with redution of 99% over the full vetor set. The redued set sizes re pproximtely the sme used mxdely mindely ot.. used o.. used/ set size % 9% used/ set size % '. 9% / [] [] [] Tle : Atul worstse vetors from simultion versus pruned set Effets of Temporl Proximity of nput Trnsitions on Gte Propgtion Dely nd Trnsition Time. n rd Design Automtion Conferene Proeedings 99, pges 7, June 99. L.C. Chen, S. K. Gupt, nd M. A. Breuer. A New Gte Dely Model for Simultneous Swithing nd its Applitions. n Design Automtion Conferene Proeedings, pges 899, June. Y.H. Jun, K. Jun, nd S.B. Prk. An Aurte nd Effiient Dely Time Modeling for MOS Logi Ciruits Using Polynomil Approximtion. EEE Trnstions on ComputerAided Design of ntegrted Ciruits nd Systems, 8(9):7, Sept L. MMurhie nd C. Sehen. WTA: WveformBsed Timing Anlysis for Deep Sumiron Ciruits. n nterntionl Conferene on ComputerAided Design (CCAD'), pges, Novemer. C. E. Molnr,. W. Jones, W. S. Cotes, J. K. Lexu, S. M. Firnks, nd. E. Sutherlnd. Two FFO Ring Performne Experiments. Proeedings of the EEE, 87():977, Ferury 999. K. T. Tng nd E. G. Friedmn. Dely Unertinty Due To OnChip Simultneous Swithing Noise in High Performne CMOS ntegrted iruits. n EEE Workshop on Signl Proessing Systems, pges. EEE, Ot..