Test Generation from Timed Input Output Automata

Transcription

1 Chpter 8 Test Genertion from Timed Input Output Automt The purpose of this hpter is to introdue tehniques for the genertion of test dt from models of softwre sed on vrints of timed utomt. The tests generted re intended to detet fults relted to timing onstrints, trnsitions mong sttes, nd opertion errors long trnsitions Introdution The purpose of this hpter is to introdue tehniques for generting test ses for testing softwre in emedded systems so s to revel errors in timing nd ommunition. While there exist vriety of nlysis tehniques useful in deteting suh errors prior to testing, our fous in this hpter is on dynmi tehniques tht tully test the softwre, often in its intended environment, to ensure tht indeed the softwre ehves orretly s per its timing nd ommunitions requirements. In prtie, tests derived using tehniques desried in this hpter would e ugmented with tests derived using tehniques disussed elsewhere in this ook. Rel-time systems re often required to dhere to vrious forms of timing nd resoure, onstrints, e.g. memory. Hrd rel-time systems re onsidered to hve filed if, for exmple, tsk dedline is missed. Soft rel-time systems re tolernt of missed dedlines. Of ourse this distintion etween hrd nd soft rel-time systems is lurred in fult-tolernt systems. Even in suh systems, hrd rel-time system often triggers n error reovery proedure when dedline is missed while soft rel-time system my tolerte few osionlly missed dedlines. The emergeny ontroller used in trin ollision voidne system is n exmple of hrd rel-time system. The routing mehnism for pkets in multimedi system is soft rel-time system. Missing dedline in hrd rel-time system might led to disster, suh 309

2 310 Foundtions of Softwre Testing 8.2. Overview of the test methodology s deths of ivilins, while missing dedline in soft rel-time system might use some inonveniene or might even go unnotied. Regrdless of wht kind of rel-time system tester dels with, the gol of high qulity will ditte tht the timing requirements e tested nd ny errors reported to the mngement. Rel-time systems re often emedded systems. Exmples inlude the engine ontroller in n utomoile nd the ontrol unit inside hert pemker. Suh emedded systems inlude sensors to periodilly smple environmentl onditions, e.g. oxygen in the tlyti onvertor of n utomoile or environment temperture outside of n irrft. The sensors smple, nd perhps proess, dt nd send it to nother proessor whih is often some hrdwre suh s miroontroller where it is proessed nd used in determining some ontrol tion, e.g. to ontrol the pulse width of the fuel injetor. Suh intertion etween vrious hrdwre devies within n emedded system often leds to softwre tht onsists of onurrent nd ommuniting proesses. In ddition to the timing errors mentioned erlier, these ommuniting proesses must lso e tested for ommunition nd other errors tht my led to re onditions nd dedloks. While finite stte nd sttehrt models re quite ommon in modeling ommunition protools nd other rel-time systems, they re often not well suited to the tsk of testing n IUT for timing errors nd errors tht result due to inorret implementtion of onurreny. Models sed on vrints of timed utomt nd Petri net re generlly well epted mongst prtitioners to model timing, resoure, nd onurreny requirements of rel-time system. In this hpter we introdue tehnique for generting tests from vrint of timed utomt known s timed input output utomt, or simply TIOA. Interestingly, severl tehniques proposed for generting tests from TIOA, nd other vrints of the timed utomt, re dpttions of tehniques for the genertion of tests from finite stte models disussed in Chpter 6. Hene these test genertion tehniques n lso e lssified s utomt theoreti nlogous to the ones introdued in Chpter 6. We egin our exposition with n overview of the test methodology for the testing of reltime system for onformne with the timing onstrints required to e met. This is followed y gentle introdution to timed utomt, lso referred to s TA. This introdution leds to the definition of vrint of TA known s timed input/output utomt, lso known s TIOA. Following this introdution we introdue the generlized Wp method to generte tests from TIOA. Exmples re used to illustrte test genertion nd the detetion of fults Overview of the test methodology In this hpter we desrie proedure for generting tests from forml speifition of timing onstrints in rel-time system. The test genertion proedure is sed on the timed Wp method nd n e utomted. The tests re generted from forml speifition expressed s timed input/output utomton, lso referred to s TIOA. Though timed Wp is lk ox method in tht it uses only the TIOA speifition to generte tests, the testing proedure itself does need ess to the ode. Hene the overll test methodology is onsidered s grey ox. The entire test methodology is illustrted in Figure 8.1. Given the informlly expressed Adity P. Mthur. Author s written permission is required to mke opies of ny prt of this ook. Ltest revision of this hpter: August 5, 2006

3 311 Foundtions of Softwre Testing Chpter 8. Test Genertion: Timed I/O Automt Figure 8.1: Steps in the genertion of tests for timing onstrints using the timed Wp method. set of requirements, one extrts the timing onstrints nd expresses them in the form of TIOA. This tsk is likely to e ompleted mnully y design or test experts. The TIOA is then trnsformed into grid utomton. A nondeterministi timed finite stte mhine, lso referred to s NTFSM, is onstruted from the TIOA. The tests, eh eing sequene of delys nd input events, re generted using the timed Wp method. For exmple, here is smple timed 1 test: send. 1 4.send. 1 4, where 1 4 is time dely nd send is n input ommnd tht serves s n input event for the implementtion. Exept for the onstrution of the TIOA, ll steps in this proess n e utomted using the lgorithms desried in this hpter. The timed tests re ville to the test hrness. The hrness, onstruted mnully, ontrols the implementtion during the test. The implementtion is derived, most likely mnully, sed on the ville requirements. The gol of the tests generted using the method desried is to sertin whether or not the implementtion stisfies the timing onstrints imposed y the requirements. The implementtion my need to e modified for the purpose of providing the hrness with informtion on its urrent stte nd the tion performed. Hene the proposed test methodology flls under the grey ox testing tegory. The hrness genertes the input events for the implementtion to proess. The input events re delyed in wys to test whether or not the implementtion meets the timing onstrints relted to the input nd output. The TIOA model ssumes n synhronous proessing of the input events y the implementtion. However, y suitly modifying the test hrness, synhronous proessing n lso e hndled. For exmple, n pplition might require tht inputs must rrive t speifi time intervls to e proessed. An input tht does not rrive t its next expeted time is ignored. Adity P. Mthur. Author s written permission is required to mke opies of ny prt of this ook. Ltest revision of this hpter: August 5, 2006

4 312 Foundtions of Softwre Testing 8.3. Timed utomt With the help of timers, the hrness n e used to generte input events to our periodilly. As nother exmple, n pplition might not impose ny onstrint on the rrivl time of the input event ut is required to ensure tht the input is proessed within given time intervl following its rrivl. Agin, with the help of timers, the hrness n determine whether or not the pplition meets the response time requirement Timed utomt Informl introdution A timed utomt is n extension of finite stte utomt using loks. We illustrte suh n extension with respet to the trnsition digrms in Figure 8.2. In this figure, M1 is n FSM ( Moore mhine) with input lphet X = {,, }, set of sttes Q = {, q 2 }, n initil stte whih lso serves s n epting stte. M1 strts in stte q 0 nd returns to its initil stte fter proessing n input string in the set ( ). Thus, for exmple, the empty string,,, nd will ll ring M1 to its initil, nd epting, stte. The lnguge reognized y M1 is preisely the regulr set ( ). Note tht the empty string lso elongs to the lnguge epted y M1. Figure 8.2: M1: A simple finite stte model. M2: Finite stte model M1 modified y the ddition of loks x nd y nd time onstrints x < 1 nd y 2. Mhine M2 hs the sme input lphet, set of sttes, the initil stte nd the finl sttes s M1. However, the trnsitions in M2 hve een leled with loks x nd y, onstrints on loks, nd the reset opertion. x nd y re ssumed to e rel-vlued loks nd inrement with the pssge of time. Both loks re initilized to 0 when M2 is first strted in stte. A lok inrements until it is reset y reset opertion speified long trnsition. Following reset(x), lok x inrements strting t 0. The reset(x) opertion is equivlent to the ssignment x := 0. We ssume tht gurd long trnsition Tr is evluted efore performing ny reset opertion ssoited with Tr. Thus, for exmple, the gurd x < 1 long the (, q 2 ) trnsition in Figure 8.2 is evluted prior to resetting lok x. While the ehvior of n FSM is independent of the time of rrivl of the next input, rrivl of inputs in M2 must e ssoited with time. Assoition of time with n input is neessry Adity P. Mthur. Author s written permission is required to mke opies of ny prt of this ook. Ltest revision of this hpter: August 5, 2006

5 313 Foundtions of Softwre Testing Chpter 8. Test Genertion: Timed I/O Automt to determine the response of M2 to n input. Inputs to M2 re lso known s events. Thus the following two sttements re equivlent: Input rrives t time 0.3 nd ours t time 0.3. An input sequene with rrivl times speified, is lso known s timed input sequene. It is ssumed tht trnsitions in M1 nd M2 our instntneously, i.e. require zero time. Thus while M2 might remin in stte for n infinite mount of time, when it moves to its next stte it does so in zero time. The next exmple illustrtes the ehvior of M2 for severl timed input sequenes. EXAMPLE 8.1. Suppose tht the event sequene E 1 = rrives t M2 in the following time sequene The nottion Time of rrivl q i t q j denotes the trnsition of stte mhine from stte q i to q j upon the rrivl of event t time t; q i nd q j might e the sme stte. The ehvior of M2 in response to E 1 is shown elow in terms of the stte trnsitions. q 2 q x y It is ssumed tht time strts t 0 when M2 is first initilized. The seond nd third rows in the tle ove list the vlues of loks x nd y, respetively. Both loks strt t 0 when M2 is initilized to stte. The loks move forwrd with the pssge of time until they re reset to 0. Upon the return of M2 to stte, lok x is t 0.9 while lok y is t 0 euse it is reset during the previous trnsition from stte q 2 to. The time elpsed sine the strt of the mhine is determined from the top row of the tle ove. For exmple, totl of 0.9 time units hve elpsed upon the seond entry into stte q 2. Also, totl of 1.7 time units hve elpsed when M2 returns to stte. Next, onsider the rrivl times of the event sequene E 2 = whih hs the sequene E 1 s its prefix Time of rrivl Adity P. Mthur. Author s written permission is required to mke opies of ny prt of this ook. Ltest revision of this hpter: August 5, 2006

6 314 Foundtions of Softwre Testing 8.3. Timed utomt The response of M2 to E 2 is shown in the tle elow. q 2 q q x y Next, onsider E 3 = E 2 = ut with the following rrivl times Time of rrivl The response of M2, shown elow, is now different euse the rrivl of the seond is too lte nd does not stisfy the lok onstrint x < 1. Hene it is ignored nd M2 gets stuk in stte. In n implementtion of M2, the seond ourrene of event my e signled s n error ondition using the violtion of timing onstrint on lok x. Any susequent event is lso ignored s x > 1 nd there is no reset opertion in. q 2 q x y Lstly, onsider E 4 = ut with the following rrivl times Time of rrivl In this se M2 is stuk in stte q 2 euse, s shown elow, event rrives lte nd does not stisfy the onstrint y < 2. q 2 q q q 2 x y Sequenes E 3 nd E 4 illustrte how the rrivl times of events n use M2 to ehve differently for the sme event sequene. Adity P. Mthur. Author s written permission is required to mke opies of ny prt of this ook. Ltest revision of this hpter: August 5, 2006