Hardware Verification 2IMF20

Transcription

1 Hrdwre Verifition 2IMF20 Julien Shmltz Leture 02: Boolen Funtions, ST, CEC

2 Course ontent - Forml tools Temporl Logis (LTL, CTL) Domin Properties System Verilog ssertions demi & Industrils Proessors Networks Che oherene Sum-of-Produts (SoP) Conjuntive Norml Form (CNF) Binry Deision Digrms (BDDs) nd-inverter Grphs (IGs) Forml Tools RTL Code Forml Model OK! NOK! Witness nd ounter-exmples 2

3 Gol: Reson out hrdwre» Given two iruits: do they ompute the sme funtion?» Equivlene heking» Comintoril nd Sequentil (next leture)» Notion of Miter (XOR etween outputs)» Given property nd iruit: prove tht the iruit stisfies the property» Forml Property Verifition (FPV) (some letures from now)» In ll se, mthemtil representtion of the iruit is needed. 3

4 Importnt onepts» The need to represent Boolen funtions effiiently» Different representtions hve different pros nd ons» Get to know the min representtions used in prtie» SoP» DNF nd CNF» DG» IG» BDD» Hve feeling out how good/d they re» Know how they re used in Comintoril Equivlene Cheking» Bsi priniple of ST solvers» Note: representing Boolen funtions is tive reserh» Cyli Boolen Ciruits y Riedel nd Bruk, Disrete pplied Mthemtis (2012) 4

5 Progrm for tody» Boolen funtions» Boolen Stisfiility» Comintoril Equivlene Cheking 5

6 Hrdwre to Forml Representtion» The first step efore pplying ny forml nlysis tehnique is to otin forml representtion of the design.» from 4 vlued logi to Boolens» Symoli Boolen expressions of the wires.» Different representtions of these expressions» Direted yli Grphs (DG)» Sum-of-Produts (SoP)» Conjuntive Norml Form (CNF)» Disjuntive Norml Form» Binry Deision Digrms (BDD s)» nd-inverter Grphs (IG s) 6

7 Boolen funtions Mthes most digitl hrdwre, other hrdwre n e trnslted into Boolen funtions. For exmple, Verilog HDL hs 0, 1, nd lso: X (unknown / error) Z (not driven, open wire) To trnslte, simply use two its, or Boolen vlues: (Flse,Flse): 0 (Flse,True): X (True,Flse): Z (True,True): 1 (ny other hoie will lso do) 7

8 Why Boolen funtions For this leture, we ssume two vlued logi without X or Z s Boolen vlue, we write: 0 for Flse, nd 1 for True We tlk out & for nd, for or,! for not, et. We n ssume we re tlking out the logil funtions: 1 & 1 = 1, x & 0 = 0, 0 & x = = 0, x 1 = 1, 1 x = 1!0 = 1,!1 = 0 8

9 Expressing Boolen funtions: Dt struture should e: Effiient to onstrut Esy to reson out 9

10 How ompt n we store funtion? Truth tle: for Boolen funtion on N inputs 2 N possile input ssignments So, 2 N rows in the truth tle s most Boolen funtions re not ny Boolen funtion : we n hve smller representtions, most of the time. For instne, only represent rows for whih n output is 1 10

11 Direted yli grph (DG) direted yli grph is wy to represent Boolen funtion, it is often used s synonym for iruit. More ompt thn the funtion written out! d e ND d&e OR (d&e) ND d&e& OR ND (d&e&) ((d&e) )&((d&e&) ) 11

12 Direted yli grph (DG) DG is list of gtes. gte t position i hs: Boolen funtion ssigned to it Eh Boolen funtion gets list of pointers to other gtes, from whih it gets its input vlues Eh of those numers need to point kwrds Vriles re represented s gtes without inputs d e ND OR ND OR ND 12

13 Direted yli grph (DG) 0: vrile 1: vrile 2: vrile 3: vrile d 4: vrile e 5: nd [3,4] 6: or [5,2] 7: nd [5,1] 8: or [7,0] 9: nd [6,8] d e ND 5 6 OR ND 7 OR 8 9 ND 13

14 Direted yli grph (DG) DG is esy to onstrut (follows hrdwre diretly) Lrge mount of different gtes: mkes it hrd to write nd mintin progrms tht reson with DGs lterntive: nd-inverter Grph (IG) Uses just two gtes: ND nd NOT 14

15 nd-inverter Grph (IG) Every gte n e onverted into fixed mount of IG gtes ND OR XOR 15

16 IG Every gte n e onverted into fixed mount of IG gtes OR OR XOR OR d ND XOR 16

17 IG Every gte n e onverted into fixed mount of IG gtes OR XOR OR d ND XOR 17

18 IG Cnnot put two inverters etween two gtes XOR OR d ND XOR 18

19 IG Sometimes, ND gtes re the sme OR d ND 19

20 IG We my shre ND gtes tht hve the sme input OR d ND 20

21 IG Two inverters in row re removed (not not is identity) d 21

22 IG Coneptully, inverters elong with the next gte d 22

23 IG IG storge is relly ompt: ll nodes get even numers First node, 0, stnds for Flse To negte node, use its numer +1 23

24 IG d 26 output !&! d

25 dvntges of IG Liner size ompred to DG Useful s intermedite struture for synthesis: NND gte hs 4 trnsistors in CMOS NOT hs 2 IG Struture gives good re nd lok-speed estimtes Exmple tool tht uses IGs: BC, System for Sequentil Synthesis nd Verifition Berkeley Logi Synthesis nd Verifition Group 25

26 Dt strutures, so fr: DG IG (Is roughly the sme, ut with few onditions) Next: onjuntive norml form d

27 Conjuntive norml form (CNF) Simple grmmr: CNF = (Disjuntion) & CNF CNF = (Disjuntion) CNF = True Disjuntion = Term Disjuntion Disjuntion = Term Disjuntion = Flse Term = Vrile Term =! Vrile Exmple: (x y) & (!z x!y) & (z -x) Rules: ll vriles within n disjuntion must e unique. Inluding x nd!x: they do not our in the sme disjuntion 27

28 Creting CNF Nive wy: Proedure for ND nd NOT, trnslte from IG ND is trivil: ND of [( )&(d e f)&(i j)] [(g h)&(i j)] eomes: [( )&(d e f)&(g h)&(i j)] or even [( )&(d e f)&(i j)&(g h)&(i j)] NOT is prolemti: goes from CNF to DNF k to CNF [( )&(d e f)&(i j)] eomes: [ (- -d -i)&(- -d -j)&(- -e -i)&(- -e -j)&(- -f -i)&(- -f -j) &(- -d -i)&(- -d -j)&(- -e -i)&(- -e -j)&(- -f -i)&(- -f -j) &(- -d -i)&(- -d -j)&(- -e -i)&(- -e -j)&(- -f -i)&(- -f -j)] This is not going to sle! 28

29 nother wy to rete CNF - ND» Consider C = ND(,B)» Gol: rete CNF formul f suh tht f(,,) == (C = &B)» if is flse, then C is flse»! implies!c, logilly equivlent to the luse!c» similrly for B: B!C» If nd B re true, then C is true» & B implies C, logilly we get!! B C» Finlly, the enoding for n ND-gte is:» (!C) & (B!C) & (!!B C)» Liner expnsion: 3 luses for eh ND-gte 29

30 nother exmple: XOR» Consider C = XOR(,B)» Gol: rete CNF formul f suh tht f(,,) == (C = XOR B)» if nd B re flse, then C is flse»! nd!b implies!c, logilly equivlent to B!C» If is true nd B is flse, then C is true» &!B implies C, logilly we get! B C» Symmetri se:!b C» If nd B re true, then C is flse» &B implies!c, logilly we get!! B!C» Finlly, the enoding for n XOR-gte is:» ( B!C) & (! B C) & (!B C) & (!! B!C) 30

31 CNF Like IG, CNF is liner in the size of the originl DG, ut only if we dd helper vriles. CNF is used s the internl struture of most ST solvers, inluding MiniST CNF is the input formt in the ST ompetition, nd in mny of its vritions Some optimistions re esier on IGs, so tools uilt on ST solvers sometimes trnslte Boolen primitives to IG to CNF, for exmple: Booletor. Other tools trnslte Boolen primitives to CNF diretly, suh s Yies 31

32 CNF: typil optimistions Never hve disjuntions with one vrile: ( v10) & (- -v10) & (- -v10) & (- - v12) & ( -v12) & ( -v12) & (- -d v14) & ( -v14) & (d -v14) & (v10 v12 v16) & (-v10 -v16) & (-v12 -v16) & (-v10) -v10 is neessrily True, so v10 is Flse (-) & (-) & (- - v12) & ( -v12) & ( -v12) & (- -d v14) & ( -v14) & (d -v14) & (v12 v16) & (-v12 -v16) New single vrile disjuntions: nd re Flse (-v12) & (-v12) & (- -d v14) & ( -v14) & (d -v14) & (v12 v16) & (-v12 -v16) New single vrile disjuntions: v12 is Flse (- -d v14) & ( -v14) & (d -v14) & (v16) New single vrile disjuntions: v16 is True 32

33 CNF: typil optimistions (2) Remove stritly lrger disjuntions: ( ) implies ( ), so ( ) is redundnt. Reple ( ) & ( ) y ( ). If vrile only ours positively/negtively, remove it: (- -d v14) & ( -v14) eomes: ( -v14) y ssigning d to Flse, whih then eomes: True y ssigning to True (or v14 to Flse) If vrile ours twie, positively in one luse, nd negtively in nother luse, we n merge these luses: (- -d v14) & ( ) eomes ( -d v14) (if does not our elsewhere!) Rell the rule: Never hve -x nd x in one disjuntion (it is lwys True) 33

34 CNF: summry Cn e onstruted in liner size if we llow for dditionl vriles Esy to reson with Common file formt for mny purposes 34

35 Dt strutures, so fr: DG IG CNF Next: inry deision digrm d

36 Binry Deision Digrm (BDD) Cnonil form exists: two strutures re equivlent if they re equl. Drwk: usully very lrge strutures 36

37 Binry Deision Digrm (BDD) DG with the following nodes Constnt 0 Constnt 1 If-then-else with vrile s ondition Rules for Ordered-BDD: Vriles re ordered, gtes must our in tht order: if >>>d>e>f, then the if then.. else.. gte n ontin gtes with nd, ut not with d, e nd f. Rules for Redued-BDD: ll gtes must e different (no two gtes with the sme vriles nd inputs, e.g. if x then y else z ) gte nnot hve the sme then nd else luse Theorem: if BDD is Redued ND Ordered, it is nonil. 37

38 Binry Deision Digrm (BDD) IG node 10: IG node 12: d

39 Binry Deision Digrm (BDD) IG node 11: IG node 13: d IG node 16:

40 Binry Deision Digrm (BDD) IG node 14: d IG node 15: d d IG node 17:

41 Binry Deision Digrm (BDD) IG node 18: d IG node 15: IG node 17: d

42 Binry Deision Digrm (BDD) IG node 18: d 1 d IG node 15: IG node 17: d

43 Binry Deision Digrm (BDD) Cnonil form: ROBDD ND of two BDDs introdues lowup Used in model hekers Usully ST-sed (CNF/IG) model heking is fster Not lwys We will ome k with more detils out BDD s lter when we will tlk out Symoli Model Cheking 43

44 Dt strutures, so fr: DG IG CNF BDD Up next: Sum of produts d

45 Sum of produts lot like CNF, ut opertions re hosen suh tht SOP is nonil. Most ommon hoie of opertions: ND (produt) + XOR (sum) ND is innermost, XOR is outermost opertion d

46 Sum of produts not : True XOR ND of {} ND of {} (True XOR ) & (True XOR ) = True & True XOR True & XOR & True XOR & = True XOR XOR XOR & d

47 Sum of produts (SOP) Unlike CNF, do not introdue helper vriles Negtion of x is simply x XOR 1 SOP is nonil, if ND- nd XOR- luses re onsidered s sets: Sort vriles within ND luse, no duplites Sort vrile-sets within XOR luse, no duplites ND of two SOPs introdues lowup d

48 Sum of produts (SOP) 10: True XOR XOR XOR & 12: & 11: XOR XOR & 13: True XOR & 16: True& XOR True& XOR True&& XOR && XOR && XOR &&& = XOR XOR & XOR & XOR & XOR & = XOR 17: True XOR XOR 14: &d 15: True XOR &d 18: True XOR XOR XOR &d XOR &d& XOR &d& d

49 Dtstrutures, so fr: DG IG CNF BDD SOP Up next: IG (gin!) d

50 IGs vs. SoP x1 x2 x3 x4 x5 y x1 x2 x3 x4 y x5 50

51 IGs vs. BDDs» IGs lwys size proportionl to input» BDDs lwys exponentil size for some ses (e.g. multiplier iruits) 51

52 ST solving» One we hve Boolen funtions, we n do ST solving.» This is n NP-Hrd prolem, ut effiient in prtie» t the sis of lmost ll modern FV methods.» t the next leture, we will go through the si lgorithm for ST solving. 52

53 CEC with SoP» SoP is norml form» CEC otined y normlising expressions to SoP» Then hek for syntti equlity 53

54 CEC with BDDs» ROBDDs is norml form.» Compute the two ROBDDs.» Chek for syntti equlity. 54

55 CEC with ST nd CNF» Tke two iruits» Crete CNF representtion of eh one of them» XOR ll outputs pirwise» ssert one XOR output is 1» Look t ode skeleton for ssignment 1 55

56 CEC with IGs» Step 1: rndom simultion» Step 2: uild IG» Step 3: ST sweeping (slides tken from Sen Wever, see ourse wepge) 56

57 Equivlene Cheking x y 57

58 nother exmple (1) y 58

59 nother exmple (2) y 1 nnd-gte to strt 59

60 nother exmple (3) y 1 or gte 60

61 nother exmple (3) y 1 nnd gte 61

62 nother exmple y finlly 1 or gte with negted inputs 62

63 IGs» Pros simple to uild nd mnipulte unifying mong synthesis, verifition, tehnology mpping ompt representtion» Cons struturlly not effiient (see FRIG) non nonil 63

64 Equivlene Cheking O 1 O

65 Rndom Simultion (1) Equivlene lsses 1,4,7,8 5 O 1 O 2 8 0,2,3,5,6 3 Rndom Vetor: ssign T to ll inputs. = = = T 65

66 Rndom Simultion (2) Equivlene lsses 1,4 5 7,8 O 1 O 2 8 2,3,5,6 3 Rndom Vetor: ssign F to ll inputs. = = = F 66

67 Rndom Simultion (3) Equivlene lsses 1,4 5 7,8 O 1 O 2 8 2,6 3,5 3 Rndom Vetor: = = F nd = T 67

68 Rndom Simultion (4) Equivlene lsses 5 7,8 O 1 O 2 8 2,6 3,5 3 Rndom Vetor: = = T nd = F 68

69 IG (1) O 1 O

70 IG (2)

71 IG (3)

72 IG (4)

73 IG (4)

74 IG (5)

75 ST Sweeping (1) Equivlene lsses 1 2 7,8 2,6 8 3,5 3 ST solver: 3 = 5 ( ^ ) ^ = (( ^ ) ^ ) ^ 75

76 ST Sweeping (2) Equivlene lsses ,8 2,6 8 3,5 3 ST solver: 3 = 5 Merge nodes 3 nd 5 76

77 ST Sweeping (3) Equivlene lsses 1 2 7,8 2,6 8 3,5 3 ST solver: 2 = 6 77

78 ST Sweeping (4) Equivlene lsses ,8 2,6 8 3,5 3 ST solver: 2 = 6 Merge nodes 2 nd 6 78

79 ST Sweeping (5) Equivlene lsses ,8 2,6 8 3,5 3 7 struturlly hshes to 8 So, iruits re equivlent 79

80 FRIGS» Insted of ST sweeping» On-the-fly uild Funtionlly Redued IG» Struturl hshing, one or two-levels» Simultion with test-vetors» Cll ST for possily equivlent nodes» Keep funtionl equivlent nodes, ut re-use just one of them 80

81 Simple exerises to prtie» See reder (Chpter 2) on the wesite 81