EE 560 INTRODUCTION. Kenneth R. Laker, University of Pennsylvania

Transcription

1 1 EE 560 ITROUTIO Kenneth R. Lker, University of ennsylvni

2 ORERIG OF TOIS 2 MOS Friction MOS Trnsistor Model Two Trnsistor ircuits (Inverters) Logic ircuits, Gtes, Ltches Regulr Structures ROMs, RMs, Ls µs, ustom Logic VLSI Su-systems System-Relted Issues, Reliility, Mnufcturility, Testility Kenneth R. Lker, University of ennsylvni

3 IFORMTIO SERVIE IUSTRY TRES Minfrme omputers onsumer Electronics t ommuniction ersonl omputers Video on emnd Speech rocessing/recognition Wireless/ellulr t ommuniction Multimedi pplictions ortle omputers etwork omputers

4 4 WHY MOOLITHI ITEGRTIO OF LRGE UMER OF FUTIOS O SIGLE HI? Less die re, compctness Less power consumption Less testing requirements t the system level Higher reliility, due to high qulity on chip interconnect Higher speed, due to reduced interconnect length Significnt cost svings

5 MIMIMUM FETURE SIZE (µm) µm 2000 YER

6 LSSIFITIO OF IGITL IRUIT TYES 6 IGITL IRUITS STTI IRUITS YMI IRUITS LSSIL MOS TRSMISSIO GTE MOS VSL IRUITS OMIO LOGI IRUITS OR LOGI IRUITS TS LOGI IRUITS Kenneth R. Lker, University of ennsylvni

7 MOS TRSISTORS 7 G G S S G G S S S G G S p+ p+ n+ n+ n-well p -sustrte Kenneth R. Lker, University of ennsylvni

8 8 G G S S G G S S S G G S p+ p+ n+ n+ p-well n -sustrte Kenneth R. Lker, University of ennsylvni

9 nmos nd pmos SWITH SYMOLS IEL HRTERISTIS 9 - SWITH s SYMOLS s SWITH HRTERISTIS Input Output 0 Srong 0 s = 0 1 Wek 1 s = 1 - SWITH s s s = 0 Input Output 0 Wek 0 Kenneth R. Lker, University of ennsylvni s = 1 1 Strong 1

10 10 OUTUT LOGI LEVELS OF - - SWITHES LEVEL SYMOL SWITH OITIO Strong 1 1 -SWITH gte = 0, source = V Wek 1 1 -SWITH gte = 1, source = V Strong 0 0 -SWITH gte = 1, source = V SS Wek 0 0 -SWITH gte = 0, source = V SS High Impednce Z -SWITH gte = 0 or -SWITH gte = 1 Kenneth R. Lker, University of ennsylvni

11 11 OMLEMETRY MOS SWITH SYMOLS -s SWITH HRTERISTIS s -s s -s Input Output 0 Srong 0 1 Strong 1 s s Kenneth R. Lker, University of ennsylvni

12 12 IVERTER TRUTH TLE IUT OUTUT (V ) input output input output input output 0 (V ) SS Kenneth R. Lker, University of ennsylvni

13 13 1 (V ) input output 0 (V ) SS RESOLUTIO OF GTE OUTUT LEVELS ull-own ull-up omined Output Output Output 0 Z 0 Z 1 1 Z Z Z 0 1 ROSSRRE Kenneth R. Lker, University of ennsylvni

14 OETIO & EHVIOR OF SERIES - - SWITHES 14 s1 s2 s1 = 0 s2 = 0 s1 = 0 s2 = 1 s1 = 1 s2 = 0 s1 = 1 s2 = 1 F s off off s2 1 off on s1 s2 s1 = 0 s2 = 0 s1 = 0 s2 = 1 s1 = 1 s2 = 0 s1 = 1 s2 = 1 F s on off s2 1 off off Kenneth R. Lker, University of ennsylvni

15 OETIO & EHVIOR OF RLLEL - - SWITHES 15 s1 s2 s1 = 0 s2 = 0 s1 = 0 s2 = 1 s1 = 1 s2 = 0 s1 = 1 s2 = 1 F s off on s2 1 on on s1 s2 s1 = 0 s2 = 0 s1 = 0 s2 = 1 s1 = 1 s2 = 0 s1 = 1 s2 = 1 F s on on s2 1 on off Kenneth R. Lker, University of ennsylvni

16 1 2-IUT MOS GTE 16 ( + ) out OR output ( ) IUT MOS GTE TRUTH TLE output OUTUT -IUT U U -IUT 0 1 Z Z 1 Z U U Z 0 Kenneth R. Lker, University of ennsylvni

17 17 2-IUT MOS OR GTE 1 OUT 1 output ( ) 0 out OR ( + ) Kenneth R. Lker, University of ennsylvni

18 OMOU GTES 18 F = (( ) + ( )) - Hlf F = (( ) + ( )) - Hlf F = ((+) (+)) Kenneth R. Lker, University of ennsylvni

19 19 F = (( ) + ( )) 1 F 0 Kenneth R. Lker, University of ennsylvni

20 2-IUT MULTILEXER 20 -s s -s output s -s output 0 1 s s output s -s output x () x () 0 x () 1 x () output =.s +.s Key components in MOS memory elements nd dt mnipultion structures. Kenneth R. Lker, University of ennsylvni

21 IRUIT SYSTEM RERESETTIOS OMLEX IGITL SYSTEM cn e SUESSIVELY SU-IVIE in HIERRHIL mnner. Highly utomted techniques exist for converting HIGH LEVEL ESRITIOS OF SYSTEM EHVIOR to detiled implementtion prescription to fricte HI. 21 To do this, set of STRTIOS hve een developed to descrie integrted electronic systems. esigns re represented in THREE distinct OMIS: 1. ehviorl: wht does the system do? 2. Structurl: how re the elements connected together? 3. hysicl: how is the structure to e uilt? Ech ESIG OMI cn e specified t vriety of LEVELS of STRTIO - rchitecturl - lgorithmic - Module or Functionl lock - Logicl - Switch - ircuit Kenneth R. Lker, University of ennsylvni Higher Level Lower Level

22 ehviorl omin pplictions Operting Systems rogrms Structurl omin RIS rocesor 22 Suroutines dder, gtes, registers ircuit strction Level Instructions Trnsistors Trnsistors Logic strction Level ells rcitecturl Level Modules hysicl omin hips, ords, oxes Kenneth R. Lker, University of ennsylvni

23 EHVIORL RERESTTIO 23 ehvior my e specified y: 1. oolen expressions 2. Tles of input/output vlues 3. lgoritythms written in high level computer lnguges 4. lgoritythms written in Hrwre escription Lnguges (HLs) e.g. VHL, Verilog highest level lowest level lgorithym -> Registers nd communictions ->... -> oolen expressions GOL OF MOER ESIG SYSTEMS: onvert spec t HIGHEST LEVEL possile into system design in MIIMUM TIME nd with MXIMUM LIKLIHOO tht the design will ERFORM S ESIRE. Kenneth R. Lker, University of ennsylvni

24 24 Exmple 1-1: pp 10 esign one-it inry dder circuit using 1 µm n-well MOS technology. The specificions re: 1. ropogtion ely Times of SUM & RRY_OUT signls: < 1.2 ns 2. Trnsition ely Times of SUM & RRY_OUT signls: < 1.2 ns 3. ircuit ie re: < 1500 µm 2 4. ynmic ower issiption (@ V = 5 V nd f mx = 20 MHz): < 1 mw Kenneth R. Lker, University of ennsylvni

25 System Requirements 25 rchitecture efinition nd Logic esign Logic igrm/escription VLSI esign nd Lyout Technology esign Rules evice Models FIL esign Verifiction SS Msk Genertion esign Rule heck ircuit Sim (SIE) Silicon rocessing Wfer Testing, ckging, Reliility Qulifiction Kenneth R. Lker, University of ennsylvni

26 STRT: oolen description of inry dder circuit: 26 FULL ER sum_out crry_out EFIE: Input Vriles: ddends:, crry-in: Output Vriles: sum_out, crry_out sum_out crry_out OOLE FUTIO: sum_out = + + = crry_out = + + Kenneth R. Lker, University of ennsylvni

27 OOLE FUTIO: 27 SUM_OUT = + + = RRY_OUT = + + crry_out sum_out SUM_OUT= + ( + + ) RRY_OUT (use of crry_out to relize sum_out reduces circuit complexity nd chip re) GTE LEVEL SHEMTI OF OE-IT FULL ER IRUIT Kenneth R. Lker, University of ennsylvni

28 crry_out 28 sum_out V crry_out V sum _out TRSISTOR LEVEL SHEMTI Kenneth R. Lker, University of ennsylvni

29 V 29 crry_out V sum_out OLOR LEGE n-well p-well V V n + oly S_O _O p + Gte Oxide Field Oxide Metl 1 Metl 2 Metl 3 ontct/vi Kenneth R. Lker, University of ennsylvni G G

30 V 30 crry_out V sum_out terntive schemtic with nmos nd pmos nets symmetricl crry_out V V sum_out Lyout with W/L = 2 µm/0.8 µm re 21 µm x 54 µm = 1134 µm 2

31 31 Lyout with W/L = 2 µm/0.8 µm Voltge (V) = 0, = SUM (crry_in) t LH t LH < 5 ns 3.0 t LH = 2 ns > 1.2 ns 1.0 t HL Modified Lyout Required 1. Increse W/L's of trnsistors 2. onsider more compct plcement of trnsistors nd reduce interconnect in critcl pths Kenneth R. Lker, University of ennsylvni

32 System Requirements 32 rchitecture efinition nd Logic esign Logic igrm/escription VLSI esign nd Lyout Technology esign Rules evice Models FIL esign Verifiction SS Msk Genertion esign Rule heck ircuit Sim (SIE) Silicon rocessing Wfer Testing, ckging, Reliility Qulifiction Kenneth R. Lker, University of ennsylvni