8 Bit RISC Processor Using Verilog HDL

Transcription

1 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- RESEARCH ARTICLE OPEN ACCESS 8 Bit RISC Prcer Uing Verilg HDL Ramaneep Kaur, Anuj VLSI Expert, Cetpa Inftech Pvt. Lt Trainee, Cetpa Inftech Pvt. Lt Abtract RISC i a eign philphy t reuce the cmplexity f intructin et that in turn reuce the amunt f pace, cycle time, ct an ther parameter taken int accunt uring the implementatin f the eign. The avent f FPGA ha enable the cmplex lgical ytem t be implemente n FPGA. The intent f thi paper i t eign an implement 8 bit RISC prcer uing FPGA Spartan E tl. Thi prcer eign epen upn eign pecificatin, analyi an imulatin. It take int cnieratin very imple intructin et. The mmentu cmpnent inclue Cntrl unit, ALU, hift regiter an accumulatr regiter. Keywr: RISC, cntrl unit, prcer. I. Intructin Nw ay, Cmputer are maintream in qutiian activitie. RISC Prcer i a CPU eign trategy that ue implifie intructin fr higher perfrmance with fater executin f intructin. It al reuce the elay in executin. It ue general intructin rather than pecialize intructin. They are le ctly t eign, tet an manufacture. Thi ha helpe in implementatin f RISC in technlgical fiel. It range f applicatin inclue ignal prceing, cnvlutin applicatin, upercmputer uch a K cmputer an wier bae fr mart phne. In thi wrk, an 8 bit RISC prcer i preente with higher perfrmance an efficiency being the main aim. Thi prcer cmprie f Cntrl unit, general purpe regiter, Arithmetic an lgical unit, hift regiter. Cntrl unit fllw intructin cycle f tage fetch, ece an execute cycle. Accring t the intructin t the fetch tage, cntrl unit generate ignal t ece the intructin. The architecture upprt intructin fr arithmetic, lgical, hifting an rtatinal peratin. The whle paper i ivie int the fllwing ectin. Sectin I ecribe the architecture f the prcer. Sectin II explain the variu mule f the prcer. Reult ha been preente in the ectin III. II. Architecture The architecture f 8 bit RISC prcer ha been hwn in the figure. It cmprie f Cntrl unit, general purpe regiter, ALU, Barrel hifter, univeral hift regiter an accumulatr. The cntrl unit cnit f tw regiter i.e intructin regiter an intructin ecer. Intructin an ata are fetche equentially in rer t reuce the latency in the machine cycle. Pipeline tructure ha been incrprate that further utilize three executin cycle fetch, ece an execute. Thi pipeline tructure help in enhancing the pee f peratin. In fetch cycle, intructin an relevant ata are inferre frm the memry while in ece cycle, intructin an ata rawn frm the memry are bifurcate t activate cmpnent an ata path fr executin an in the executin cycle intructin i execute, ata i manipulate an reult i tre in the accumulatr. Figure.Architecture f 8 bit RISC prcer The cntrl unit accept the pce an generate the ignal that trigger the cmpnent an P a g e

2 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- ata path t wrk accringly an perfrm the eire functin. The cntrl unit ha tw intructin ecer. Thee tw ecer ece the intructin bit an irect the ignal t either int ALU, univeral hift regiter r barrel hift rtatr. The peran are receive frm regiter A r regiter B. Upn receiving the peran frm regiter an the ece intructin bit arithmetic an lgical unit perfrm arithmetic an lgical functin. Univeral hift regiter an barrel hift rtatr receive the input frm regiter A an epening upn the ece infrmatin perfrm the eire peratin f either hifting r rtatin an the reult i tre in the accumulatr regiter. ecer perfrm arithmetic an lgical functin an the ecn ecer perfrm hifting an rtating peratin. The tp blck f cntrl unit i hwn in the figure. Figure.Cntrl Unit tp blck Figure.State iagram III. Mule in the eign f 8 bit RISC Prcer Mule are the builing blck f a Prcer. Thi egment eal with the mule f 8 bit RISC prcer. Cntrl Unit, ALU, general purpe regiter, univeral hift regiter, barrel hift rtatr an accumulatr are main mule f the prcer.. Cntrl Unit : The cntrl unit i bae n tate iagram a epicte in the figure. The tate machine perfrm the functin f arithmetic, lgical, hifting an rtating functin. If bit intructin i then OR peratin i perfrme a n a next intructin i receive then apprpriate peratin i perfrme. The cntrl unit cnit f tw ecer. The firt. ALU Arithmetic an lgical unit i a igital circuit that perfrm arithmetic an lgical peratin. The prpe eign perfrm even lgical functin an tw arithmetic functin. The lgical peratin t be execute are AND, NAND, OR, NOR, XOR, XNOR an NOT while tw lgical peratin are perfrme Aitin an Subtractin. ALU will receive intructin bit frm cntrl unit an will execute the eire peratin. Fr example, if input t cntrl unit i, the ece bit will be an after receiving the intructin bit frm the ecer AND peratin i perfrme by ALU accring t the peran frm regiter A an regiter B. The tp blck i hwn in the figure. 8 P a g e

3 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- Select line Decer Output Functin Perfrme Operatin AND NAND OR NOR XOR XNOR Subtracti n Aitin Nt Figure. ALU Simulatin Reult. Barrel Shifter: Barrel hifter i hwn in the figure. It i a igital circuit that hift the number f bit by pecifie time. It will receive the ece intructin bit frm the ecn intructin ecer inie the cntrl unit an perfrm the eire peratin epening upn peran frm regiter A an elect line. Table. Operatin f ALU Figure. ALU Tp Blck Figure. Barrel hifter Tp blck 9 P a g e

4 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- Select line Decer utput Functin perfrme S S S Table. Operatin f Barrel hifter. Univeral Shift Regiter The achitecture i hwn in the figure. Thi architecture perfrm fur main functin a fllw laing the value, left hift an right hift an n change. If an bth are lw while z i equal t the value i lae. If i lw an i high with ece utput z a left hift peratin i perfrme. Operati n er pratin bit left rtate bit left rtate bit right rtate bit left rtate Figure. Univeral Shift regiter Tp blck Sele ct line Decer utput Functin perfrme Operatin La Left hift Right hift er peratin Table. Operatin f Univeral hift regiter Figure 8.Univeral hift regiter imulatin reult. General Purpe Regiter General purpe regiter tre the 8 bit ata. There are ttal 8 D flip flp. Tw general purpe regiter are A an B. If reet i high then regiter i clear, n the ther han if reet i lw, r i taken t be high an clck i high ata i tre in the regiter. It i hwn in the figure 9. Input Output Cl k ree t r A A A A A A A A P P P P P P P P x X X X X X X X X Table.Operatin f General purpe regiter P a g e

5 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- Figure 9.General purpe regiter Tp Blck Figure.General purpe regiter Simulatin reult. Accumulatr Regiter: Accumulatr regiter tp blck i hwn in the figure.the reult frm ALU r univeral hift regiter r barrel rtatr i tre in the accumulatr regiter. If reet i et t high then accumulatr regiter i cleare therwie 8 bit reult i tre in the accumulatr regiter. Figure.Accumulatr imulatin reult IV. RESULT The perfrmance f 8 bit RISC prcer ha been crutinize uing Xilinx Spartan E technlgy. The eign meet the requirement f high pee, extremely lw ct an cnumer riente eign. The verall eign ha been hwn in the figure. The ata i receive frm tw 8 bit regiter A an B. Signal READ(r) i a memry interface ignal. Thi ignal aumbrate the memry lcatin t be rea an ata t be put int the ata bu. The ynchrnizatin i ne utilizing clk ignal. Deign f prcer ha been accmplihe uing tw cntrl ignal namely r an reet. If reet i high, prcer will nt perfrm any peratin an cntinue t remain in ile tate. If reet i lw an r i high ata i lae int regiter. Depening upn the pce frm cntrl unit the prcer perfrm the peratin. Thi 8 bit RISC prcer wrk n ne clck cycle. clk i the external clck ignal an trigger the input an reult in the utput. r trigger the tate f regiter A an B. t pecifie the pce t enable the peratin. If pce i then OR peratin i perfrme. V. CONCLUSION An 8 bit RISC prcer with intructin et ha been eigne. Every intructin ha been execute in ne clck cycle with tage pipelining. Verificatin ha been eneavre by exhautive imulatin. The prcer can be ue fr mathematical cmputatin in prtable calculatr a well a in gaming tl kit. Figure.Accumulatr regiter tp blck REFERENCES [] B. Rajeh Kumar, Raviaketh an Santha Kumar,, Implementatin f A -bit RISC Prcer fr Cnvlutin Applicatin, Reearch Inia publicatin, pp -. [] Aneeh, R.; Jiju, K. "Deign f FPGA bae 8-bit RISC cntrller IP cre uing P a g e

6 Anuj et al Int. Jurnal f Engineering Reearch an Applicatin ISSN : 8-9, Vl., Iue ( Verin ), March, pp.- VHDL", Inia Cnference (INDICON), Annual IEEE, On page(): - [] Feru, T. "Deign an FPGA-bae implementatin f a high perfrmance - bit DSP prcer", Cmputer an Infrmatin Technlgy (ICCIT), th Internatinal Cnference, n page(): 8 89 [] R Uma, Deign an perfrmance analyi f 8 bit RISC prcer uing Xilinx tl, March-April,, Internatinal Jurnal f Engineering Reearch an Applicatin (IJERA), pp -8. [] MD.Shabeena Begum, M.Kihre Kumar, FPGA bae implementatin f bit ric prcer, Internatinal Jurnal f Engineering Reearch an Applicatin (IJERA), pp 8- [] Mr. Sagar P. Ritpurkar, Prf. Mangeh N. Thakare, Prf. Girih D. Kre, Review n -bit MIPS RISC Prcer uing VHDL, IOSR Jurnal f Electrical an Electrnic Engineering (IOSR-JEEE), PP - [] Anjana R & Krunal Ganhi, VHDL Implementatin f a MIPS RISC Prcer, Augut, Internatinal Jurnal f Avance Reearch in Cmputer Science an Sftware Engineering, pp P a g e