Concurrent Error Detection for Reliable SHA-3 Design
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1 5/18/ Cncurrent Errr Detectin fr Reliable SHA-3 Design Pei LUO 1 Cheng LI 2 Yunsi FEI 1 1. Nrtheastern Universit Energ-Efficient and Secure Sstems Lab Electrical & Cmputer Engineering Department Nrtheastern Universit 2. Intel Labs
2 5/18/ Outline Mtivatin Preliminar f SHA-3 Prtectin f peratins in SHA-3 Fault injectin attacks simulatin results Cnclusin
3 5/18/ Mtivatin Widel use f Keccak SHA-3 has been standardied b NIST [1] Keccak based candidates enter the 2 nd rund f CAESAR cmpetitin cmpetitin fr authenticated encrptin Fault injectin attacks n SHA-3 Single-bit faults injected at the penultimate rund input can be used t cnquer SHA-3 [2] Our wrk shws that attackers need nl 17 single-bte faults t cnquer SHA-3 Technlg scales dwn transient faults increase - reliabilit [1] Dwrkin Mrris J. "SHA-3 Standard: Permutatin-Based Hash and Etendable-Output Functins." Federal Inf. Prcess. Stds. NIST FIPS-202 August [2] Bagheri Nasur Navid Ghaedi and Smitra Kumar Sanadha. "Differential Fault Analsis f SHA-3." Prgress in Crptlg INDOCRYPT Springer Internatinal Publishing
4 5/18/ Mtivatin Hw t prtect SHA-3 against randm errrs and fault injectin attacks? Intrduce redundanc int the sstem Imprve reliabilit but nt against fault injectins Make use f rund rtatin invariance prpert [1] [2] Intrduce high redundanc f either area r time cnsumptin f ROT 1 f ROT Intrduce errr detectin cdes Parit checking cde is efficient and widel used Ke pint: hw t make use f the features f Keccak [1] Baat-Sarmadi et al. "Efficient and cncurrent reliable realiatin f the secure crptgraphic SHA-3 algrithm." Cmputer-Aided Design f Integrated Circuits and Sstems IEEE Transactins n : [2] Lu Pei et al. "An Imprvement f Bth Securit and Reliabilit fr Keccak Implementatins n Smart Card."
5 5/18/ Outline Mtivatin Preliminar f SHA-3 Prtectin f each peratin in SHA-3 Fault injectin attacks simulatin results Cnclusin
6 5/18/ Preliminar f SHA-3
7 5/18/ Preliminar f SHA-3 24 runds 5 peratins in each rund
8 Preliminar f SHA i 4 0 i 4 0 i + θ θ θ θ 5/18/2016 8
9 5/18/ Preliminar f SHA-3 ρ changes the psitins f bits alng each lane
10 5/18/ Preliminar f SHA-3 changes π the psitins f bits inside each slice
11 Preliminar f SHA invlves nnlinear peratins : i i i + + χ χ χ χ χ 5/18/
12 5/18/ Outline Mtivatin Preliminar f SHA-3 Prtectin f peratins in SHA-3 Fault injectin attacks simulatin results Cnclusin
13 5/18/ Prtectin structure θ θ Prtectr ρ' ρ' Prtectr χ ι χ' Prtectr
14 θ Prtectin f 1 i θ θ Which can be simplified as: 5/18/
15 θ Prtectin f ] [ ] [ i i P P θ θ θ θ [0...63] 1 ] [ ] [ i + P P θ θ 5/18/ Parit checking f peratin θ is ver efficient
16 5/18/ Prtectin f ρ and π Bth ρ and π are bit rtatin peratins withut changing the value Bth ρ and π are implemented using wire in hardware n registers intrduced Faults in ρ will prpagate directl int π Prtectin f ρ and π: Can be mitted fr higher efficienc Can be cmbined tgether
17 pitfall a - f Prtectin χ b a e e a e d d e d c c d c b b c b a a a e e d d c c b b a e d c b a peratin as the input f ne rw f Dente e d c b a χ 5/18/ If a flips with a 50% prbabilit the errr ma nt change the parit
18 χ Prtectin f 2 1 in which ] [ 2 ] [ ] [ ] [ i i and and i i P P P P χ χ χ χ χ χ χ 5/18/ Avid t cmpress bits in each rw Invlves nl AND and XOR peratins
19 5/18/ Outline Mtivatin Preliminar f SHA-3 Prtectin f each peratin in SHA-3 Fault injectin attacks simulatin results Cnclusin
20 5/18/ Fault injectin attacks simulatin Mdeled in VHDL [1] 45 nm Opencell librar Snthesied in Cadence Encunter RTL Cmpiler Placed and ruted using Cadence Encunter Overhead estimated using Cncurrent Surces 1.1 V 25 Celsius degree Faults injected at gate level Randml inject stuck-at-0 and stuck-at-1 faults int up t ten gates [1]
21 5/18/ Simulatin results Prpsed: cmbine prtectin f χ and ι ρ and π unprtected Design 2: prtect χ and ι separatel ρ and π unprtected Design 3: cmbine prtectin f χ and ι prtect ρ and π tgether um 2 Area Timing Pwer Nrmalied % ns Nrmalied % mw Nrmalied % Errr Cverage Original % Prpsed % Design % Design %
22 5/18/ Simulatin results Prpsed: cmbine prtectin f χ and ι leave ρ and π unprtected Design 2: prtect χ and ι separatel leave ρ and π unprtected Design 3: cmbine prtectin f χ and ι prtect ρ and π tgether um 2 Area Timing Pwer Nrmalied % ns Nrmalied % mw Nrmalied % Errr Cverage Original % Prpsed % Design % Design %
23 5/18/ Simulatin results Prpsed: cmbine prtectin f χ and ι leave ρ and π unprtected Design 2: prtect χ and ι separatel leave ρ and π unprtected Design 3: cmbine prtectin f χ and ι prtect ρ and π tgether um 2 Area Timing Pwer Nrmalied % ns Nrmalied % mw Nrmalied % Errr Cverage Original % Prpsed % Design % Design %
24 5/18/ Simulatin results The prpsed scheme has lw verhead and high errr cverage Prtectin f χ and ι can be cmbined fr lwer verhead Prtectin f ρ and π can be saved fr hardware implementatins Prtectin f ρ and π shuld be implemented fr pipelined design
25 5/18/ Outline Mtivatin Preliminar f SHA-3 Prtectin f each peratin in SHA-3 Fault injectin attacks simulatin results Cnclusin
26 5/18/ Cnclusin SHA-3 shuld be prtected against randm errrs r fault injectin attacks Our wrk Eplit the features f SHA-3 fr efficient errr detectin design Overhead is small while the errr detectin rate is high Future wrk is t eplre mre efficient errr detectin methds fr SHA-3
27 5/18/ Acknwledgment The authrs wuld like t thank Dr. Re Xiafei Gu at Intel fr his help This wrk was supprted in part b Natinal Science Fundatin under grants SaTC and MRI
28 5/18/ Thanks!
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