ELEVATOR CONTROL CIRCUIT. Project No: PRJ045 Presented by; Masila Jane Mwelu. Supervisor: Prof. Mwangi Examiner: Dr. Mang oli

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1 ELEVATOR CONTROL CIRCUIT Project No: PRJ045 Presented by; Masila Jane Mwelu Supervisor: Prof. Mwangi Examiner: Dr. Mang oli

2 Presentation Outline Project objectives Design approach Implementation Results Conclusion Recommendation

3 Objective To design and simulate a controller for an elevator that serves three floors, using small scale integration(ssi) and medium scale integration(msi) logic modules as a sequential logic circuit.

4 Design approach Algorithmic state machine(asm) methodology has been employed in the design. The method describes the problem statement in a flow chart and allows the circuit to be divided into two parts a; Data processor part Controller part ASM method is used due to the presence of large number of inputs.

5 Implementation Design specification The controller responds to request from each floor. When the elevator lands on a given floor, signals are generated from the sensor switches. The control logic generates signals to move the elevator up or down, and to open or close the door. Display logic indicates the current floor number.

6 Block diagram of the elevator D2/X2 Control logic Display logic 7- segment floor display Inputs UP1/X1 UP0/X0 OPEN CLOSE Outputs

7 ASM chart of the Controller The flow chart is composed of: State box Represents the state in which the system is in.

8 Decision box Describes the effect of an input on the control sudsystem.

9 Conditional box Within the box are one or two register operations which take place during the next raising clock edge.

10 State GRD CLOSE=1; counter is cleared and the door is closed OPEN=1; counter continues to count while the door is open UP0 or X0=1; system remains in State GRD UP1 or D1 or X1=1; System goes to state FIR D2 or X2=1; system goes to state SEC

11 State FIR CLOSE=1; counter is cleared and the door is closed OPEN=1; counter continues to count while the door is open UP0 or X0=1; system goes to State GRD UP1 or D1 or X1=1; System remains in state FIR D2 or X2=1; system goes to state SEC

12 State SEC CLOSE=1; counter is cleared and the door is closed OPEN=1; counter continues to count while the door is open UP0 or X0=1; system goes to State GRD UP1 or D1 or X1=1; System goes to state FIR D2 or X2=1; system remains in state SEC

13 Timing Sequence Timing in all the flip-flops in the controller is controlled by a clock. Each block in the ASM chart describes the state of the system during one clock pulse interval. Change from one state to the next is performed in the control logic.

14 ASM chart for the Controller

15 Datapath Performs the data processing operation. The requirements for the design of the Datapath are specified inside the; State boxes Conditional boxes The Datapath consists of; A pulser Counters Gates

17 State table for the controller Present State Ysf Yff Ygf Inputs CLOSE UP0 X0 UP1 DI X1 D2 X2 Next State Ysf Yff Ygf Outputs SEC FIR GRD X X X X 0 0 X X X X X X

18 Control logic By inspecting the state table, the next states are equal to the inputs. Thus the input equations are taken directly from the state table. D flip-flops were used in the design due to ease in formulating the design equations. Display logic A decoder was used to produce the outputs to a 7-segment display.

19 Control logic diagram

21 Results and Discussion The simulation software used was Circuit maker pro which has most of SSI and MSI components. Push buttons were simulated as logic switches and the output indicators used were; Logic displays Seven-segment display

22 Present State Q3 Q2 Q1 Tabulated results for the controller Inputs X0,UP0,X1,UP1,D1,X2,D2 Outputs Q3 Q2 Q X0 or UP X1 or UP1 or D Details Elevator remains on ground floor Elevator is raised to immediate floor up X2 or D Elevator jumps one floor up X1 or UP1 or D Elevator remains on first floor X1 or UP Immediate floor down X2 or UP Immediate floor up X0 or UP X1 or UP1 or D X2 or UP Elevator jumps one floor down Elevator goes to immediate floor down Elevator remains on second floor

23 Display logic response Outputs Q3 Q2 Q1 Display Details Display a Display a Display a 2

25 Conclusion Adopting the ASM procedure simplified the design. Design with D flip-flop proved simple and clear. The results obtained from simulation agreed with the theoretical expectation.

26 Recommendations for further work. The proposed controller can be extended as part of future study into; Implementation of the hardware. Implementing special dispatching strategies such as bypassing floor calls when the elevator is full. The elevator controller design can solved by use of micro-processor based controller.

27 THANK YOU

Design at the Register Transfer Level

Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic