ENEL Digital Circuit Design. Final Examination

Size: px

Start display at page:

Download "ENEL Digital Circuit Design. Final Examination"

Cory Perry
5 years ago
Views:

1 ELECTRICAL AND COMPUTER ENGINEERING ENEL Digital Circuit Design Final Examination Friday, December 17, 1999 Red Gymnasium, 3:30PM - 6:30 PM Instructions: Time allowed is 3 hours. The examination is closed-book. Calculators are permitted. The maximum number of marks is 100, as indicated. Please attempt all questions. Please use a pen or heavy pencil to ensure legibility. If you use more than one examination booklet, please make sure that your name and ID number are on both. Where appropriate, marks will be awarded for proper and well-reasoned explanations.

2 ENEL 353 Final Examination 2 1 Positional Number Systems (15 marks) For questions (1.1)-(1.5) below, please show your work to receive full marks. 1.1 Convert to decimal. [3 marks.] 1.2 Convert BAD.8 16 to base 6. [3 marks.] 1.3 Multiply the unsigned binary numbers and using binary arithmetic. Express your answer as another unsigned binary number. [3 marks.] 1.4 Determine the radix r such that the following relationship is satisfied. [3 marks.] 211 r = (1) 1.5 Consider the numbers X = 3D 16 and Y = CE 16 that are hexadecimal representations of 8-bit sign-magnitude binary numbers. Compute X + Y using two s-complement binary arithmetic, then convert your answer back to signmagnitude binary form. [3 marks.] 2 Switching Algebra (15 marks) 2.1 Using the method of your choice, prove the Consensus Theorem, which is stated as follows. [3 marks.] xy + x z + yz = xy + x z (2) 2.2 Express the following as a canonical sum-of-products and a canonical productof-sums. [3 marks.] F = C(A + B) + BCD + A D (3) 2.3 Simplify the following expression algebraically. [3 marks.] F = y(vwx(x u+w ov)+ou+ouwx )+g((g +x+y) +(o +t ) )+ix t+ixt (4) 2.4 Without using a truth table, use the theorems of switching algebra to determine the canonical sum-of-products for the following. [3 marks.] F = A B C (5) 2.5 Find the complement (i.e., F ) of the following expression. [3 marks.] F = AB(C D + CD ) + A B (C + D)(C + D ) (6)

3 ENEL 353 Final Examination 3 3 Combinational Circuits (35 marks) 3.1 Consider the multi-level AND-OR diagram shown in Fig. 1. (a) Write the expression for the output F of this circuit. [3 marks.] (b) Modify this circuit so that it uses only NAND gates and inverters. [5 marks.] [8 marks total.] Fig. 1. An AND-OR logic diagram 3.2 Design a combinational circuit that takes a 4-bit binary-coded decimal (BCD) integer P QRS as input, and produces a 4-bit output W XY Z that is the nine s complement of P QRS. P is the most-significant bit (MSB) of the input and W is the MSB of the output. Your circuit should be minimal in complexity and use only NAND gates and inverters. You may assume that non-bcd numbers are never input to the circuit. [9 marks.] 3.3 The logic symbol for a 74x138 3-to-8 line decoder is shown in Fig. 2. Fig. 2. A 74x138 decoder Implement the nine s-complement converter in question (3.2) using decoders of this type and NAND gates. The MSB of the select lines is C. [6 marks.]

4 ENEL 353 Final Examination Design a combinational circuit that takes a 4-bit BCD number and appropriately illuminates segment F in the seven-segment display shown in Fig. 3. The segment is illuminated for BCD digits 0, 4, 5, 6, 8, and 9, when a logic-1 is applied to the segments input. Your circuit should be minimal in complexity and the only gates available to you are NOR gates (that is, no inverters are available). You may assume that non-bcd numbers are never input to the circuit. [6 marks.] Fig. 3. A seven-segment display 3.5 Using Karnaugh maps, obtain both a minimal sum-of-products and product-ofsums expression for the function F = y z + wxy + wxz + w x z (7) For your choice of groupings, carefully indicate the distinguished one- and zerocells and the essential prime implicants/implicates. [6 marks.] 4 Sequential Circuits (35 marks) 4.1 The state/output table for a particular clocked synchronous circuit is shown in Fig. 4. The circuit has a single input, X, and a single output, Z. Fig. 4 A state/output table (a) Draw the state diagram for this circuit. [3 marks.]

5 ENEL 353 Final Examination 5 (b) Briefly describe the operation of this circuit; that is, what particular pattern of input X causes the output Z to be become asserted. [2 marks,] (c) Design the circuit based on D-type flip-flops (DFFs) using the minimal cost approach for the unused states. For your design, assign the states Q2Q1Q0 = 000 (INIT), 001 (S1), 011 (S2), 010 (S3), 110 (S4), and 111 (S5). Please provide the following design components: [6 marks.] The transition/excitation/output table. The minimized excitation equations and output equation. The logic diagram using NAND gates, inverters, and DFFs. [11 marks total.] 4.2 Analyze the clocked synchronous circuit given in Fig. 5. Write the excitation equations, the excitation/transition table, and the state/output table (use state names S0-S3 for Q1Q0 = 00, 01, 10, 11). [6 marks.] Fig. 5. A clocked synchronous circuit for analysis 4.3 Design a clocked synchronous circuit based on DFFs that produces a dual outof-order counting sequence. It has a single input, X, and the outputs are the system state variables Q2Q1Q0. When the input is X = 1, the circuit produces the repeating output sequence ; that is, when X = 1, the state variables count through the sequence Q2Q1Q0 = Similarly, when the input is X = 0, the circuit produces the alternate repeating output sequence of Use the minimal cost approach for the unused states in your design. For your design, please provide the following design components. The state diagram. Show all transitions.

6 ENEL 353 Final Examination 6 The state/output table. The transition/excitation/output table. The minimized excitation equations. It is not necessary to draw the logic diagram for the circuit. [10 marks.] 4.4 Suppose that Krusty Enterprises has approached you to design a vending machine that dispenses Krusty-brand after-dinner mints. The machines are to be installed at all local Krusty Burger restaurants. The cost of the mints is $1.00, and the machine accepts only quarters (25-cent coins) or loonies (1-dollar coins). Design a Mealy-type clocked synchronous state machine to act as a controller for the vending machine. Suggest a state diagram only; it is not necessary to complete the design. There are three inputs available to you: Q - quarter. This signal is asserted after a quarter has been inserted into the machine and the coin is in physical contact with the coin sensor. Normally, Q=0; then, when the coin first touches the sensor, Q becomes asserted Q=1, and it remains Q=1 until the coin completely passes the sensor. L - loonie. This signal has the same properties as Q above, except that it is asserted when a loonie is in contact with the sensor. Since the same sensor is used for both coins, Q and L are never asserted simultaneously. CR - coin return. This signal is from a front-panel button on the machine to request that the transaction be terminated and to return just the quarters, if any, that have been inserted. CR=1 while the button is pressed. The outputs of the controller are M ( mint ), used to dispense a mint, and C ( coin ), used to cause the return of any quarters collected in the current transaction. The mint signal M indicates a successful transaction, and it also causes the machine to keep the inserted coins. The operation of the machine is as follows: When a loonie has passed by the sensor, the machine dispenses a mint and returns any quarters that may have been inserted first. The transaction is complete. If quarters are being inserted, the controller must count the passage of four coins; as the fourth moves past the sensor, the machine dispenses a mint, and the transaction is complete. If the coin-return button is pressed while the controller is waiting for a coin to be inserted, then all quarters inserted so far are returned and the transaction terminates. [8 marks.] Norm Bartley, December 14, 1999

Fundamentals of Digital Design

Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric