IN THE literature, significant research has been focused on

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1 552 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998 Simulating the Impact of Pattern-Dependent Poly-CD Variation on Circuit Performance Brian E. Stine, Duane S. Boning, Member, IEEE, James E. Chung, Member, IEEE, Dennis J. Ciplickas, and John K. Kibarian Abstract In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-cd) variation on circuit performance. The methodology is illustrated on a 0.25 m SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell. I. INTRODUCTION IN THE literature, significant research has been focused on understanding the impact of process variation on circuit performance [1] [12], but the majority of this research assumes process variation to be completely random and drawn from either independent or correlated normal distributions (i.e., Monte Carlo type simulations or design centering methodologies). This approach is adequate when assessing the impact of lot-tolot or wafer-to-wafer process variation on circuit performance since these types of variation can often be adequately modeled using Gaussian white noise. For pattern-dependent variation, however, this approach is not acceptable because it essentially assumes that the channel length of each transistor on a die can be described by the same underlying random distribution or perhaps with some crude degree of proximity effects included via a correlation structure. Previous studies have empirically observed a correlation between poly-cd variation and circuit performance [13] for small circuits (such as ring-oscillators), but predictive modeling of the impact of die-level variation has been difficult. In this paper, we present and illustrate a methodology for determining the impact of pattern-dependent polysilicon critical dimension (poly-cd) variation on circuit performance. After describing the methodology in Section II, the methodology is illustrated in Section III via a case study of a 64 8 SRAM Manuscript received December 28, 1997; revised February 24, This work was supported in part under ARPA Contracts DABT C-0088 and DAAH01-96-C-R904, AASERT Grant DAAHA04-95-I-0459, and an Intel Foundation Fellowship. B. E. Stine was with Microsystems Technology Laboratories, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA USA. He is now with PDF Solutions, Inc., San Jose, CA USA. D. S. Boning and J. E. Chung are with the Microsystems Technology Laboratories, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA USA ( D. J. Ciplickas and J. K. Kibarian are with PDF Solutions, Inc., San Jose, CA USA. Publisher Item Identifier S (98) Fig. 1. Flow used to simulate the impact of poly-cd variation on circuit performance in this paper. Fig. 2. Hopkins model used in aerial imaging simulators. Figure and notation derived from [16]. macrocell. Finally, some concluding remarks are offered in Section IV. Poly-CD variation is especially important because it translates directly into MOS transistor channel length variation and resulting variations in the drive current and switching characteristics. Current lithography and etch technology can typically achieve wafer-scale line width uniformity of approximately 5 10% (measurements of the same structure within each chip across the wafer). Design rules typically assume that the variation within any one chip will be smaller than this value. However, measurements of supposedly identical structures within the same die reveal variations on the order of 15 20% or more [14], [15]. Clearly, additional physical effects are coming into play at this scale and within-die poly- CD nonuniformity contributes significant variance to the total poly-cd variation budget /98$ IEEE

2 STINE et al.: PATTERN-DEPENDENT POLY-CD VARIATION 553 Fig. 5. Estimated poly-cd variation across all coordinates in the cell. Aerial imaging simulation was used to estimate the poly-cd variation. (a) Fig. 3. Ideal as-drawn features from an SRAM cell and corresponding aerial imaged features. (b) Fig. 6. (a) Drain current versus drain voltage for V gs at the supply rail. (b) Saturation or drive current versus channel langth for the NMOS and PMOS devices. Fig. 4. A SRAM macrocell. Layout is approximately m. The problem of determining the impact of variation on circuit performance is especially vexing because of the intense coupling between design and manufacturing. A portion of the variance that a design sees is driven by the process (mainly lot-to-lot, wafer-to-wafer, and within-wafer), but a large part of the variance, especially for critical parameters such as the polysilicon critical dimension, is dependent on the design itself as represented by the layout. In this way, the question what is the impact of spatial or pattern-dependent variation on circuit performance? cannot be answered in the general, but must be dealt with in the specific as the answer is necessarily different for each design. As such, this paper offers a methodology for determining the impact of patterndependent poly-cd variation on circuit performance which can be used on each layout of interest or on several layouts to gain insight rather than presents a conclusive study or evaluation of

3 554 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998 Fig. 7. Simulation of the write-access behavior for the SRAM macrocell with poly-cd variation enabled. Significant skew is seen across all data lines for this particular address. the impact of pattern-dependent poly-cd variation on circuit performance. II. SIMULATION METHODOLOGY We propose the methodology shown in Fig. 1 for exploring the impact of pattern-dependent poly-cd variation on circuit performance. We use aerial imaging to perturb or transform all of the polygons in the original or as-drawn layout into the aerial imaged or as-manufactured layout resulting in a new poly layer. In this way, the aerial image simulator is modeling the manufacturing process. After simulating the manufacturing process, a circuit net-list is extracted from the as-manufactured layout (with the imaged poly layer used as the gate mask) using a traditional layout-parasitic engine. Finally, a circuit simulator is used to evaluate the performance of the layout. By looking at the performance of the layout with and without aerial imaging over different input conditions, a determination can be made as to the impact of poly-cd variation on circuit performance. Many other effects such as lens-aberration, stepper leveling/focusing errors, and etch loading contribute to poly-cd variation. Since these effects are more macroscopic, the relative utility of the methodology presented here is limited to small to medium size layouts; however, this restriction can be removed if accurate and calibrated models exist for these effects as a function of extractable or tangible layout parameters. Optical proximity components are estimated using aerial imaging [16], [17]. Aerial imaging has been in practice for approximately ten years and most simulators use the Hopkins model approach [17]. In this approach (see Fig. 2), the intensity at the target can be expressed as a nonlinear function of the illumination lens and pupil,, the projection optics, and the mask being imaged. The numeric aperture of the lens (NA), the illumination wavelength ( ), and the coherence of the imaging system ( ) are the key input parameters which shape the Hopkins integral. Using these parameters and several assumptions of the image/projection system [16] allow the Hopkins integral to be expressed as a two-dimensional convolution integral which allows the expression to be evaluated using numerically efficient fast Fourier transforms. By taking equi-illumination contours at the target, an estimate of the optical proximity component of lithography variance is enabled. A sample result is shown in Fig. 3. The ideal features are shown as well as the results from aerially imaging for a sample SRAM cell. III. SIMULATION EXAMPLE In this section, the methodology described in Section II is applied to a m64 8 SRAM macrocell. In current technologies, SRAM finds application not only as a standalone part, but also as an embedded memory element in microprocessors and complex logic and as a process qualification and development vehicle [18]. Also, SRAM layout typically includes a mix of periodic structures (the cell array) and aperiodic logic components (e.g., the decoders and input-output buffers). For these reasons, SRAM makes a suitable case study for exploring the impact of variation on circuit performance. The SRAM macrocell layout (see Fig. 4) is approximately 180 m 140 m in size and contains approximately 4000 transistors. The layout was originally designed for 3- m design rules but was scaled down to m design rules using simple scaling. Only aerial imaging was used to simulate the within-die poly-cd variation. This is mainly due to the small size of

4 STINE et al.: PATTERN-DEPENDENT POLY-CD VARIATION 555 Fig. 8. Delay versus input address for the SRAM cell. Maximum skew across all output lines depends on the address chosen. the layout compared to the length scales of other sources of variation (e.g., stepper leveling errors, lens aberration). Fig. 5 shows a surface plot of poly-cd, the deviation of gate length from nominal, versus location. This figure was generated by extracting the channel length and position of each transistor from the netlist and interpolating on to a surface plot. The mean channel length is approximately 0.25 m and the largest excursions are almost 10%. In this way, we are assuming that the stepper has been perfectly targeted (i.e., the mean channel lengths equals the specified target). Note the presence of periodic components in addition to larger peaks and valleys. Interconnect variation modeling was not done due to the small size of the layout and was only crudely modeled using an identical load capacitor of 10 ff at each output bit to simulate external wiring. For circuit simulation, a 0.25 m SPICE device model was created based on SIA roadmap specifications [19], [20] and typical values reported in the literature. The sensitivity of, the measured drain current when both the gate and drain are held at the supply rail, is shown in Fig. 6. Although the values are slightly higher than normally expected, the sensitivity to channel length variation is similar to results published elsewhere (e.g., [21]). Fig. 7 shows the result of simulating the aerially imaged layout with the above device models. The voltage at each output line [Fig. 7(c)] is shown for the address lines (ADDR[0] ADDR[5]) set to all zeros [Fig. 7(a)] and for strobing the input data lines (In[0] In[7]) from all ones to all zeros [Fig. 7(b)]. Also, the write strobe is held high resulting in a display of the write access behavior. In this case study, we are interested in the time required to write a data word to an address location (the write access time). In particular, the maximum skew for all the data lines is of key interest since this is a measure of the susceptibility of this circuit to poly-cd variation. Since interconnect has not been included and each input bit passes through the same number of gates, the amount of skew for the as-drawn layout is near zero, but as Fig. 7 shows, there is significant skew for the write access time. The

5 556 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998 read access time does not show significant skew behavior and is significantly shorter than any write access time; thus, it is not discussed. For the case of fully bidirectional applications (i.e., in cases where the proportion of writing data to reading data is relatively similar) such as in microprocessors, the slowest of the read access times or write-access times dictates the overall performance of the part. The skew behavior shown in Fig. 7(c) is for one particular address location. As Fig. 8 shows, the maximum amount of write-access time skew is heavily dependent on the input address vector. The oscillating behavior is especially apparent on address line Out[5]. The 64 8 layout is organized into two blocks of 32 8 with each block having separate decoder circuitry and hence different layout environments. The oscillating behavior in Out[5] is most likely caused by differences in the channel lengths in each 32 8 block s decoding circuitry. In this way, the results of simulating the impact of spatial variation on circuit performance are heavily dependent on the input test vectors used during circuit simulation. If all possible input vectors cannot be simulated, then careful planning and examination of test vectors is needed. Normally, test vectors are selected to stimulate all or most of the functional blocks in the layout. Since functional blocks are often repeated as many instances in a layout, stimulating just one instance of each functional block is not sufficient since instances are likely to have different layout environments and hence difference degrees of poly-cd variation. For this reason, the choice of test vectors should always include the stimulation of all instances of a particular functional block. If the number of instances of a functional block is very large as well, then the number of instances stimulated should be subseted to include only those which are furthest apart in the layout. IV. CONCLUSION In this paper, we have demonstrated a methodology for determining the impact of pattern-dependent poly-cd variation on circuit performance. For a particular SRAM example, the results indicate that pattern-dependent poly-cd variation results in an approximately 10% skew in the write access time. The simulated skew, however, is strongly dependent on the input conditions and assumptions. Further work is needed to include interconnect variation and more extensive printing (i.e., lithography and etch) models. Further studies are also underway using this methodology to examine the sensitivity of functionally identical logic blocks to different design styles (such as dynamic versus static logic). REFERENCES [1] P. Balaban and J. Golembeski, Statistical analysis for practical circuit design, IEEE Trans. Circuits Syst. vol. CAS-22, pp , Feb [2] P. Rankin and R. Soin, Efficient Monte Carlo yield prediction using control variates, in Proc. IEEE Int. Symp. Circuits Syst., Apr. 1981, vol. 1, pp [3] S. W. Director and G. Hatchel, The simplicial approximation approach to design centering, IEEE Trans. Circuits Syst., vol. CAS-24, no. 7, pp , July [4] J. Bandler and H. Abdel-Malek, Optimal centering, tolerancing, and yield determination via updated approximations and cuts, IEEE Trans. Circuit Syst., vol. CAS-25, no. 10, pp , Oct [5] L. Vidigal and S. Director, A design centering algorithm for nonconvex regions of acceptability, IEEE Trans. Computer-Aided Design, vol. CAD-1, pp , Jan [6] K. Tahim and R. Spence, A radial exploration approach to manufacturing yield estimation and design centering, IEEE Trans. Circuits Syst., vol. CAS-26, pp , Sept [7] K. Singhal and J. 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Spanos, Ring oscillator sensitivity to spatial process variation, in Proc. 1st Int. Workshop Statistical Metrology, June [14] B. Stine, D. Boning, J. Chung, D. Bell, and E. Equi, Inter- and intra-die polysilicon critical dimension variation, in Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, SPIE 1996 Symp. Microelectronic Manufacturing, Oct. 1996, Austin, TX. [15] D. Doherty Fitzgerald, Analysis of polysilicon critical dimension variation for submicron CMOS processes, M.S. thesis, Dept. Elect. Eng. Comp. Sci., Mass. Inst. Technol., Cambridge, June [16] Y. Pati, A. Ghazanfarian, and R. Pease, Exploiting structure in fast aerial image computation for integrated circuit patterns, IEEE Trans. Semiconduct. Manufact., vol. 10, pp , Feb [17] D. Cole, E. Barouch, U. Hollerbach, and S. Orszag, Derivation and simulation of higher numerical aperture scalar aerial images, Jpn. J. Appl. Phys., vol. 31, p. 4110, [18] M. Bohr and Y. El-Mansy, Technology for advanced high-performance microprocessors, IEEE Trans. Electron Devices, vol. 45, pp , Mar [19] Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, San Jose, CA, [20] K. Rahmat, O. Nakagawa, S.-Y. Oh, J. Moll, and W. Lynch, A scaling scheme for interconnect in deep-submicron processes, in IEDM Tech. Dig., Dec [21] G. Thakar, V. McNeil, S. Madan, B. Riemenschneider, D. Rogers, J. McKee, R. Eklund, and R. Chapman, A manufacturable high performance quarter micron CMOS technology using I-line lithography and gate linewidth reduction etch process, in Proc Symp. VLSI Technology, June 1996, pp Brian E. Stine, for a photograph and biography, see p. 139 of the February 1998 issue of this TRANSACTIONS. Duane S. Boning (M 91), for a photograph and biography, see p. 139 of the February 1998 issue of this TRANSACTIONS. James E. Chung (S 87 M 90), for a photograph and biography, see p. 140 of the February 1998 issue of this TRANSACTIONS. Dennis J. Ciplickas, photograph and biography not available at the time of publication. John K. Kibarian, photograph and biography not available at the time of publication.