Prospect of Ballistic CNFET in High Performance Applications: Modeling and Analysis

Transcription

1 Prospect of Ballistic CNFET in High Performance Applications: Modeling and Analysis 12 BIPUL C. PAUL Stanford University and Toshiba America Research Inc. SHINOBU FUJITA and MASAKI OKAJIMA Toshiba America Research Inc. and THOMAS LEE Stanford University With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOS- FET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry. Categories and Subject Descriptors: I.6.5 [Simulation and Modeling]: Model Development General Terms: Design Additional Key Words and Phrases: Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance, process variability ACM Reference Format: Paul, B. C., Fujita, S., Okajima, M., and Lee, T Prospect of ballistic CNFET in high performance applications: modeling and analysis. ACM J. Emerg. Technol. Comput. Syst. 3, 3, This article is an extended and revised version of the paper presented at the 2006 IEEE/ACM Design Automation Conference (DAC) C ACM Authors addresses: B. C. Paul, S. Fujita, M. Okajima, Toshiba America Research, 2590 Orchard Parkway, San Jose, CA 95131; bpaul@tari.toshiba.com; T. Lee, Center for Integrated Systems, Stanford University, 420 Via Palou, Stanford, CA Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY USA, fax +1 (212) , or permissions@acm.org. C 2007 ACM /2007/11-ART12 $5.00. DOI / /

2 12:2 B. C. Paul et al. Article 12 (November 2007), 16 pages. DOI = / / INTRODUCTION As silicon technology is approaching its limit, several emerging devices are being studied to find a suitable alternative to silicon. Carbon nanotube FETs (CNFET) have the potential of taking this place in the post silicon era. Its interesting structural and electrostatic properties (e.g., near ballistic transport) make it attractive for the future integrated circuit applications [Avouris 2004]. Consequently, interest has grown in predicting the performance of these devices in circuits and systems [Guo et al. 2002, 2004; Castro et al. 2002; Pennington and Goldsman 2003; Dwyer et al. 2004; Raychowdhury et al. 2004]. However, circuit simulation using CNFET is a difficult task at present because most of the developed device models are numerical [Guo et al. 2002; Natori et al. 2005], which conventional circuit simulators like SPICE can not handle. For this purpose, analytical expressions for device characteristics (e.g., I-V and C-V) in terms of applied terminal voltages (e.g., V gs, V ds ; see Figure 1) are highly desirable. A good analytical device model will thus facilitate the early analysis of the performance of CNFET devices in large circuits and systems. A few attempts have been made recently to obtain an analytical model for CNFET [Raychowdhury et al. 2004; Mugnaini and Iannaccone 2005]. However, while the simple model in Raychowdhury et al. [2004] is not effective for all operating conditions due to its underlying assumptions, the nanowire model proposed in Mugnaini and Iannaccone [2005] may not be appropriate (as proposed) for CNFET because of its centroid-based approach. In this article, we present a circuit compatible quasi-analytical device model, 1 which can be used for different semiconducting CNFET structures under all operating conditions in the digital circuit application domain. This compact model will greatly facilitate the circuit simulation using any conventional simulator like SPICE. The model is developed assuming the ballistic transport of CNFET [Guo et al. 2002] and is shown to have close agreement with the physical model. We further provide in this article, a quantitative analysis on the geometrydependent parasitic capacitances of state-of-the-art CNFET structures and their impact on the circuit performance. Because of its high drive current (due to ballistic transport) the intrinsic performance of CNFET has been predicted to be very high [Guo et al. 2005; Castro and Pulfrey 2006; Lin et al. 2005; Alam and Lake 2005]. The effective circuit performance in reality is, however, governed by the effective gate capacitance of the device, which includes both (1) the intrinsic and (2) extrinsic (parasitic) capacitances. While the intrinsic capacitance of CNFET has theoretically been shown to be only a few atto-farads [Lin et al. 2005a; Alam and Lake 2005; John et al. 2004; Rosenblatt et al. 2002], the parasitic capacitance, however, is a strong function of the device geometry and should also be considered in order to estimate the realistic performance of CNFET [John and Pulfrey 2006]. We show that the performance of CNFET is 1 This work was partly presented at DAC 2006 [Paul et al. 2006].

3 Prospect of Ballistic CNFET in High Performance Applications 12:3 Fig. 1. (a) Schematic of a carbon nanotube transistor; (b) Equivalent circuit of a ballistic onedimensional CNFET for circuit simulation. R s and R d are the source and drain contact resistance, respectively. limited by the process (the current technique to fabricate CNFET) and that the device width needs to be significantly reduced in order to achieve the superior performance of intrinsic CNFET over silicon MOSFET in circuits. This analysis not only provides a realistic estimation of the performance of CNFET circuits but also draws a very effective guideline for device design and optimization as well as process development. We also present an in depth analysis on CNFET performance under process variability. While every process parameter variation drastically affects the conventional MOSFET performance, we found that CNFETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry. Though the process technology such as diameter and direction-controlled growth are yet to mature, considering the recent progress [Javey et al. 2004; Deng et al. 2007], one can expect more sophisticated process and circuit solutions in the near future that will overcome this problem to a large extent. We therefore, assume a reasonably matured process, which provides devices with reasonable accuracy. This also enables us to make a fair comparison with existing Si MOSFET devices based on the same dimension of source, drain and gate area. It is observed that a 2-input NAND gate with CNFET shows more than 5 times less performance variation than its bulk MOSFET counterpart at 45 nm technology. In other words, for a tolerable performance variation, CNFET devices can have much larger allowable process parameters variation than that of conventional devices. The rest of the article is organized as follows. In Section 2, we describe the proposed compact model of CNFET for circuit simulation. Section 3 discuses the parasitic capacitances in state-of-the-art CNFET structures and its impact on circuit performance. Section 4 presents an analysis on CNFET performance under process parameter variations and compares that with conventional MOSFET, followed by a conclusion in Section COMPACT MODEL OF CNFET For circuit simulation using a conventional simulator like SPICE, we need an analytical expression for device characteristics (e.g., I-V and C-V) in terms of applied terminal voltages (e.g., V gs, V ds : see Figure 1). However, it is impossible to obtain exact closed-form expressions directly by solving self-consistent

4 12:4 B. C. Paul et al. device equations [Guo et al. 2002; Natori et al. 2005]. For example, the applied voltage at the gate terminal partly drops across the insulator (V INS ) and partly across the channel (Figure 1(a)). On top of this, the lateral electric field due to applied drain voltage further complicates the entire electrostatics. Finding an analytical solution to such a complicated system of highly nonlinear simultaneous equations is extremely difficult. As a result, most previously developed physical device models use numerical techniques to obtain device characteristics where the reference point is the surface potential, ψ s (not the terminal potential: V g, V d or V s (Figure 1(a))) [Guo et al. 2002; Natori et al. 2005]. On the other hand, we employ appropriate approximations to analytically solve the device equations. We assume ballistic transport in MOSFET- like single-walled CNFET with one-dimensional (1D) electrostatics [McEuen et al. 2002]. Short channel MOSFET- like CNFETs are of particular interest because they provide near ballistic current, thereby indicating maximum performance [Javey et al. 2003; Wind et al. 2003]. Conceptually, in a CNFET, the nanotube channel is connected between the source and drain contacts, which are in thermodynamic equilibrium. Hence, the electrostatics at the source and drain contacts can be described by their individual Fermi level. Since the nanotube channel is isolated from any other source of mobile carrier, the source and drain are the sole source of carriers inside the channel. In such an electrostatic system, the carrier density at any subband (pth) can be expressed as in Guo et al. [2002], n p = E c, p D p (E) [ f (E μ s ) + f (E μ d )] de, (1) 2 where μ s(d) is the source (drain) Fermi level, E c, p is the conduction band minimum for the pth subband, which is inversely proportional to the nanotube diameter [Mintmire and White 1998]. f (E) is the probability that a state with energy E is occupied and D(E) is the nanotube density-of-states, which can be approximated as D 0 E / E 2 Ec, 2 p for low bias [Mintmire and White 1998]. D 0 = 8/(3π V b), where V and b are respectively, the carbon-carbon bonding energy and the distance. Normalizing all energies and voltages by β (k B T/q) and substituting ε 2 εc, 2 p = z2 (ε = E/β), Equation (1) can be written as follows. [ ] dz n p = N 0 (, N 0 = v i =v s,v d e z 2 +εc, 2 p (ϕ s v i )) β D 0 2, (2) / where ϕ s (ψ s β), vs and v d are the normalized surface, source and drain potentials, respectively. Though solving Equation (2) analytically is not possible, an approximate closed-form solution can be obtained by dividing the operating condition into two parts. For ψ s <ψ T (below threshold), when z 2 + εc, 2 p ϕ s >> 1 (for all z : 0 ), Equation (2) can be approximated to calculate the charge as, [ ( ] ) Q CNT = qn 0 e z 2 +εc, 2 p dz (1 + e v ds )e ϕ s p 0

5 Prospect of Ballistic CNFET in High Performance Applications 12:5 = e α 0+ϕ s. (3) We consider the source potential as the reference potential and V ds is the drain potential with respect to source. It is observed that ψ T = E c, p /q 2β is a good choice for this approximation. The integral of Equation (3) can be precomputed numerically and α 0 can be analytically obtained for any drain voltage. For ψ T <ψ s E c, p /q (above threshold), Equation (2) can be rewritten as, [ n p = N 0 e [x (ϕ s v i )] ( 1 + e [x (ϕ s v i )] ) ] 1 dz x = v i =0,v ds 0 z 2 + ε 2 c, p. (4) Further expanding Equation (4) into binomial series, which is now a converging series for all values of z, and e ϕ s into infinite series and neglecting the higherorder terms, we can obtain Q CNT as, [ = qn 0 ( 1) n 1 e n(ϕ s ϕ T ) (1 + e nv ( ds ) e n (x ϕ T ) ) ] dz Q CNT p n=1 λ 0 + η 1 λ 1 (ψ s ψ T ) + η 2 λ 2 (ψ s ψ T ) 2. (5) λ 0, λ 1, λ 2 are geometry-dependent parameters which can be obtained with simple algebraic calculation, while all integrations can be performed numerically. Note that the reason for approximating Q CNT into polynomial form is to obtain an analytical V gs ψ s relation which is derived in the following. Further, though one can obtain an accurate expression by considering higher-order terms (without using any correction factor), we, however, use the polynomial of order two with constant correction factors η 1 and η 2 to obtain a simpler V gs ψ s relation. For ψ s > E c /q, though a similar approximate solution can be achieved following the previous approach of carefully expanding in series, we observed that Equation (5) also efficiently predicts the charge. Figure 2 shows Q CNT verses ψ s obtained from a physics model [numerical solution of Equation (2)] and the approximate analytical model (Equations (3) and (5)). It can be seen that the analytical models (with Equation (5) and without correction factors polynomial of order 4) closely match the physics model in both below (Figure 2(a)) and above threshold (Figure 2(b)). Q CNT is further related to terminal voltage, V gs (neglecting the flat-band voltage, see Figure 1(a)) as, ψ s = V gs V INS = V gs Q CNT, (6) C INS where C INS is the insulator capacitance. Substituting Q CNT in Equation (6), an analytical closed-form expression for V g ψ s can be obtained as [ ] 1 ψ s = V gs β lambertw e (α 0+Vgs/β) for V gs V T β C INS 0

6 12:6 B. C. Paul et al. Fig. 2. Charge vs. channel potential of a ballistic carbon nanotube FET. The physical model represents the numerical solution of Equation (2). (a) ψ s <ψ t, (b) ψ s >ψ t, the curve Analytical (a) represents the charge obtained from Equation (5) (with correction factors), and Analytical (b) is the charge obtained from the polynomial expression of order 4 without using any empirical parameter. α o = 32.42, λ o = coulomb, λ 1 η 1 = coulomb/volt, λ 2 η 2 = coulomb/volt 2, for V ds = 0. ψ s = ψ T (η 1λ 1 + C INS ) 2η 2 λ 2 + [(η 1λ 1 + C INS ) 2 4η 2 λ 2 [λ 0 C INS (V gs ψ T )]] 1 / 2 2η 2 λ 2 for V gs > V T, where V T is the gate voltage (threshold voltage) corresponding to ψ T and can be obtained from Equations (3) and (6) with ψ s = ψ T. Knowing ψ s in terms of the terminal voltages, the drain current, I ds and gate input capacitance, C G (Figure 1) can be easily obtained as follows [Raychowdhury et al. 2004]. I ds = 4qk BT [ln(1 + e ξ s ) ln(1 + e ξ d )] h p and C G = Q CNT V gs, (8) where ξ i = qψ s E c, p qv i k B (i = s, d) and h is the Planck s constant. Further, typical T values for R s and R d (Figure 1) can be used based on the experimental results for circuit simulation. Figure 3 shows the I V (I d V g and I d V d ) characteristics of a CNFET with 2 nm diameter and 48.3 pf/m insulator capacitance. It can be seen from the figure that, while the model proposed in Raychowdhury et al. [2004] does not match the physical model for large bias conditions, our proposed model matches closely for a wide range of bias conditions. Also note that since we did not make any abrupt approximation in our model, no discontinuity arises around the threshold. We also verified our model for different nanotube diameters (1, 1.6, 1.7 and 2 nm) and obtained a close match with the physical model in all cases. Note that we used the physical model with numerical solutions to compare our model due to the unavailability of adequate experimentally measured data with different nanotube dimensions. (7)

7 Prospect of Ballistic CNFET in High Performance Applications 12:7 Fig. 3. I V characteristics of CNFET with diameter = 2 nm and C INS = 48.3 pf/m, V T = 0.3V (T = 300 K ); (a) I ds V gs for different V ds ; (b) I ds V ds for different V gs. Fig. 4. Input/Output waveform of a 2-input NAND driving three identical gates. Figure 4 shows the SPICE simulation result of a 2-input NAND gate driving three identical gates (CNT: diameter = 2 nm and L ch = 20 nm (V dd = 0.9V)). We used one nanotube for PCNFET and two parallel nanotubes for series connected NCNFETs. As shown in the figure, a considerably fast response time (2.52ps) was obtained using the intrinsic devices compared to the conventional ITRS 45 nm CMOS technology prediction. 3. IMPACT OF PARASITICS ON CIRCUIT PERFORMANCE In this section, we analyze the impact of parasitic capacitances on the CNFET circuit performance. We first describe the effective geometry-dependent parasitic components in state-of-the-art CNFET structures followed by a discussion on the overall circuit performance with parasitics. 3.1 Geometry-Dependent Parasitic Capacitance Figure 5(a) shows the schematic cross section of a state-of-the-art top-gated CNFET structure [Javey et al. 2004; Wing et al. 2002]. In this self-aligned process, the gate electrode metal (height, T g ) is separated from the source/drain (length, L sd ) metal by approximately T ox H sd in the vertical direction (T ox : oxide

8 12:8 B. C. Paul et al. Fig. 5. (a) Schematic of a self-aligned top-gated carbon nanotube transistor. (b) Top view of CNFET. Note that W here is the geometric gate width and not the effective channel width (W eff ). It therefore, does not affect I on and only contributes to the parasitic capacitances. (c) Electrostatic geometry for the fringing field of the device. thickness, H sd : source/drain metal thickness) and by the thin oxide (L un ) in the horizontal direction that is used to isolate the gate metal during source/drain metal deposition. The cross-sectional view of the electrostatic geometry of the device can be represented as shown in Figure 5(c). The parasitic capacitance in this structure consists of mainly the gate/source and gate/drain fringe capacitances. The other components such as gate-to-substrate and source/drain-tosubstrate capacitances are expected to be very small (due to large SiO 2 thickness) and are therefore neglected in this analysis. The fringe capacitance (C fr ) of this geometry can be analytically calculated using the following equation [Bansal et al. 2005]. C fr = 2εW π ln T g,s/d + ηt g + L 2 un + (ηt g) 2 + 2T g,s/d ηt g L un + T g,s/d + kεw π ln π W e L un T g,s/d Lun +T g,s/d, (9) L 2 un + T g,s/d 2 where η = exp[(l sd + L un L 2 un + T g 2 + 2T g,s/d T g )/τ L sd ] and T g,s/d = T ox H sd ε is the permittivity of medium, W is the device width, and k and τ are constants. A detail description about the above formulation can be found in Bansal et al. [2005]. In this analysis, we used SiO 2 as the medium outside the device. 3.2 Analysis of Fringe Capacitance Figure 6 shows the variation in C fr with T g (gate height) and T ox (oxide thickness). C fr has two components, outer (C of ) and inner (C if ) fringe capacitances. Unlike conventional MOSFET, in CNFET, both C of and C if will substantially contribute to the total fringe capacitance due to very narrow channel region (typically one nanotube in one micrometer width). C of and C fr are calculated following Equation (9). It can be seen from the figure that, for a typical geometry (T g 30 nm, T ox 8 nm, L un 1 nm, L sd 250 nm, H sd 7 nm), C fr is about two orders of magnitude larger than the typical device intrinsic capacitance

9 Prospect of Ballistic CNFET in High Performance Applications 12:9 Fig. 6. Variation in fringe capacitance with device geometry, (a) with gate metal thickness, (b) with source/drain length, (c) with oxide thickness, and (d) with underlap. ( 1.5aF for a 50 nm gate [Lin et al. 2005a]). The typical width (W ) of a stateof-the-art CNFET device is about 1 μm. This is necessary to ensure the nanotube channel under the gate. Hence, the circuit performance will be dominated by the parasitic fringe capacitances, and the effectiveness of very low intrinsic capacitance of CNFET can not be utilized in reality. Note that here W (Figure 5(b)) is the geometric gate width and not the effective channel width (W eff ). It, therefore, does not affect I on and only contributes to the parasitic capacitances. Further, due to the logarithmic dependency, C fr is not a very sensitive function of T g (Figure 6(a)). T g also cannot be very thin since it increases the gate resistance drastically [Bansal et al. 2005]. C fr has a similar dependency on L sd due to the geometric symmetry and, hence, varying L sd will not impact C fr significantly (Figure 6(b)). C fr, however, has a strong dependency on the gate oxide thickness (T ox ) of the transistor. It can be seen Figure 6(c) that C fr reduces steeply with the increase in T ox at around 8 nm. This is because the electric flux strongly depends on the nearest distance between the electrodes. This implies that the use of high-k gate oxide will lead to lower effective gate capacitance by employing larger T ox while still having good gate control. Separating the source and drain from the gate has also been tried by means of doping the nanotube

10 12:10 B. C. Paul et al. Fig. 7. Schematic of a dual-gate (bottom) CNFET. (b) Schematic of a multiple FIN CNFET equivalent to five parallel CNT channel. outside of the gate region [Chen et al. 2005]. We studied the impact of this structure (analogous to underlap device) on C fr by varying L un. Though C fr can be reduced significantly by increasing L un, it still remains significantly higher than intrinsic device capacitance (Figure 6(d)). It is evident from Figure 6 that C fr cannot be reduced to the order of intrinsic device capacitance by optimizing T g, T ox, L sd, and L un. One way to effectively reduce C fr is to reduce the width of the device (W ). However, this not only calls for the improvement in the control of nanotube fabrication but also requires improvement in the lithography process. With present lithography equipment, achieving such small W (order of 10 nm) is extremely difficult. A dual-gate (bottom) CNFET structure has also been recently proposed for improved performance [Lin et al. 2005a, 2005b] in which the active gate is deposited on top of the back SiO 2 gate (below the nanotube channel) and separated from the source and drain by a large distance (Figure 7(a)). In this structure, though the gate to source/drain parasitic capacitances are expected to reduce considerably, the parasitic capacitance between the active and the back gates is expected to be large if the back gate is controlled independently. It will consist of both overlap and fringe capacitances as shown in Figure 7(a). For a typical structure with gate length 50 nm and height 20 nm, the parasitic capacitance was found to be F with 1 μm width, which is much larger than the intrinsic capacitance. On the other hand, if the back gate switches with the active gate, though the capacitance between them will be negligible, the overlap and fringe capacitances between the back gate and the source/drain will be significantly higher. Efforts have also been put into increasing the transistor drive current by introducing multiple nanotubes between the source and drain (parallel nanotube channels). One such geometry has been proposed in Javey et al. [2004] (see Figure 7(b)). In this self-aligned process, one nanotube acts as multiple channels between the source and drain. We analyzed one such structure to understand its effectiveness in improving the circuit performance. In a typical process, the gate FINs are separated by approximately 250 nm and, hence, besides each individual gate FIN, the gate metal connecting the FINs also contributes to the total fringe capacitance. Therefore, the improvement in drive current will be masked by the increase in capacitance degrading the overall performance.

11 Prospect of Ballistic CNFET in High Performance Applications 12:11 Fig. 8. Input/Output waveform of a 2-input NAND gate with fanout 3 using CNFET (20 nm gate length) and CMOS BPTM 45 nm technology. To further analyze the impact of parasitic capacitance, we simulated a 2-input CNFET (20 nm gate length) NAND gate driving 3 identical gates and compared the same with bulk silicon 45 nm predictive CMOS technology ( ptm/). The circuit simulation with CNFET was performed with the developed compact model discussed in Section 2. It can be seen in Figure 8 that, while the intrinsic delay of the CNFET NAND gate is very small (2.52ps), the delay with parasitics (344ps) is much larger than silicon CMOS delay (165ps). This is because, in 45 nm technology, the minimum transistor size (nmos transistor width = 240 nm in a 2-input NAND) was much smaller than CNFET width ( 1 μm). Further, the junction capacitance was not considered in Si CMOS transistors. The result confirms that the performance will be indeed dominated by the fringe capacitance, which is also expected to dominate the effective gate capacitance in silicon [Bansal et al. 2005]. In the previous analysis, we have not taken interconnect into account. Interconnect may further limit the performance of CNFET circuits. However, we feel that a quantitative analysis of performance with interconnect is too abstract at this point since there is too little information available about CNFET circuit layout configuration. 4. IMPACT OF PROCESS VARIATION While inherent characteristics such as gate controllability drive current etc, of carbon nanotube devices are shown to be superior to that of bulk MOSFETs, it is also widely believed that variation in the fabrication process may significantly undermine those advantages. In this section, we evaluate the performance of these devices under process variability. The same top-gated device structure [Javey et al. 2004] is used in this analysis assuming ohmic source/drain contacts. We, however, consider a 100 nm gate width (W ) for these devices for a fair comparison with 45 nm bulk CMOS technology. The process parameters of such devices are divided into two categories, namely, lithography/geometry-related parameters and nanotube growth-related parameters such as the diameter (D), nanotube chirality, and intertube spacing. For a low-voltage operation (as in most digital applications),

12 12:12 B. C. Paul et al. Fig. 9. Sensitivity of I on of an NFET to T ox (a), and diameter (b) variation. The following typical parameter values were considered. CNFET: T ox = 8nm, T g = 30 nm, W = 100 nm, L sd = 100 nm, L eff = 20 nm, H sd = 7nm, L un = 2 nm, D = 2 nm; MOSFET: 45 nm predictive technology model [Wing et al. 2002]. since chirality variation in CNT does not significantly affect the device electrostatics [McEuen et al. 2002], we therefore, omit chirality variation in our analysis. The screening effect due to intertube spacing variation is also omitted assuming sufficiently large spacing to avoid intertube coupling. While lithography/growth-related parameters will have variations similar to conventional silicon technology, we need to consider a reasonable variation that may occur in the diameter of nanotubes. Note that the variation in diameter depends on the process technology to grow the nanotubes. However, it has been demonstrated that the diameter of a nanotube can be controlled within a reasonable limit (<30%) [Han et al. 2005]. High-precision semiconducting nanotubes are also commercially available [Helix Material Solutions] for developing CNFET circuits. Hence, in a future sophisticated process, we may assume diameter variation within a reasonable limit. Further, considering the nanotube growth characteristics (in state-of-the-art technologies), we may have to keep large enough gate margins outside the channel area to ensure nanotubes under the gate. This will significantly reduce the probability that any nanotube channel is left out of the gate region and, hence, variation in W may not significantly affect the drive current. Note that, as we mentioned earlier, W in CNFET devices is not the effective channel width, W eff (see Figure 5(b)). Since at present, adequate information is not available in this regard, we assumed a continuous variation in W eff in our analysis which affects I on. 4.1 Impact on Drive Current The interesting point to note in nanotube devices is that, unlike conventional MOSFET devices, most lithography-related parameter variation does not significantly affect the drive current of these devices. For example, while the variation in T ox drastically affects I on of bulk MOSFET, I on of CNFET is a weak function of T ox variation due to cylindrical gate geometry (Figure 9(a)). Further, I on of CNFET will also be independent of L eff (effective channel length) variation considering ballistic transport. Note that L eff variation is attributed to both wire orientation variation and lithography variation. Variation in diameter (D),

13 Prospect of Ballistic CNFET in High Performance Applications 12:13 Fig. 10. Overall I on sensitivity to all parameter variations. Random dopant effect is also included in bulk MOSFET analysis. Fig. 11. Overall gate capacitance (C g ) sensitivity to all parameter variation. The approximate linear response demonstrates the dominance of W variation. however, will considerably affect I on of CNFETs (Figure 9(b)) by varying its band-gap. Figure 10 shows the overall I on sensitivity of both CNFET and bulk MOSFET devices under all parameter variations. It can be observed that I on of CNFET is significantly less sensitive to process variation than conventional bulk MOSFET. Note that the random dopant effect in bulk MOSFET devices is also included in the analysis. Overall, due to cylindrical gate geometry, the drive current of CNFET devices are significantly less sensitive to variations than bulk MOSFETs. 4.2 Impact on Capacitance Parameter variations also affect device capacitance, which needs to be analyzed to understand the overall impact of variation on the performance of any device. We mentioned earlier that the effective device capacitance in CNFET is dominated by C fr and, hence, it will be less sensitive to most geometry-dependent parameter variations, such as L sd, L un, T ox, T g, for logarithmic dependency (Equation (9)). It, however, strongly depends on W variation. Figure 11 shows the impact of variation on overall gate capacitance, C g, where the linear change demonstrates the dominance of W. In contrast, C g of bulk MOSFET is more

14 12:14 B. C. Paul et al. Fig. 12. Delay variation of a 2 input NAND gate with an inverter load. sensitive to variations due to the presence of significant intrinsic and overlap capacitances, which are strong functions of geometry-related parameters. 4.3 Impact on Circuit Performance Now that we have discussed the effect of process parameter variation on the drive current and capacitance of carbon nanotube transistors, it is imperative to evaluate the circuit performance of this device under variation. We compare the performance of a 2-input NAND gate with an inverter load under variation at an equivalent 45 nm technology node using HSPICE Monte-Carlo simulation. Figure 12 compares the delay variation of a circuit for different 3σ values. It can be observed that CNFET shows significantly lower sensitivity (5X less) to variation than bulk MOSFET. This further confirms the insensitivity of CNFET device performance to many geometry/lithography-related process parameter variations as discussed before. 5. CONCLUSIONS In this article, we provided a quasi-analytical circuit-compatible model for intrinsic ballistic CNFET. This model is very effective for various CNFET structures with a wide range of bias conditions, which can be used in conventional circuit simulators. We also provided a quantitative analysis on the parasitic capacitance of state-of-the-art CNFET structures. We showed that the parasitic capacitance cannot be significantly reduced by optimizing gate metal thickness, gate oxide thickness, or source/drain length and that it can be effectively reduced only by decreasing the width. We further demonstrated that, due to its cylindrical gate structure, CNFET devices are significantly less sensitive to many process parameter variations. In other words, CNFET will have a larger margin to process parameter (especially diameter and number of tubes) variation than bulk MOSFET for an allowable performance variation limit. Hence, while the parasitic capacitance analysis will provide a useful guideline to device design and process development of CNFET, its lesser sensitivity to process variation is expected to encourage further research towards high-performance applications.

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