SCHOTTKY BARRIER MOSFET DEVICE PHYSICS FOR CRYOGENIC APPLICATIONS
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1 CHOTTKY BARRIER FET DEVICE PHYIC FOR CRYOGENIC APPLICATION Mike chwarz, Laurie E. Calvet, John P. nyder, Tillmann Krauss, Udo chwalke, Alexander Kloes
2 cope OI and Multi-Gate FETs Dresden ept.3, 2018 New device concepts and structures, e.g. IV or III-V chottky Barrier FETs Benefits at cryogenic temperatures, e.g. superior carrier mobility due to less doping, lower temps and reduced surface roughness scattering TCAD requires accurate models for transport through B incl. lowering High-res. TEM of a 22-nm B-P [1] [1] J. M. Larson, J. P. nyder, Overview and status of metal /D chottky-barrier FET technology, IEEE Transaction Electron Devices 53 (5), , /15
3 Outline Device Physics Analysis i versus GaAs devices Effect of chottky Barrier Lowering Temperature Effects Comparison B-DG-FET vs. DG-FET Conclusion Acknowledgements Dresden ept.3, /15
4 Device Physics chottky Barrier Five basic transport processes under forward bias [2] [2]. M. ze, KWOG K. NG, Physics of emiconductor Devices, John Wiley & ons, Dresden ept.3, 2018 Metal-emiconductor junction Majority carriers are responsible for current flow Basic transport processes Thermionic emission Tunneling Recombination Diffusion of electrons Diffusion of holes 4/15
![Device Physics - Operation Principles increasing V ds [3] M. chwarz, T. Holtij, A. Kloes, B.](/docs-images/90/103278213/images/5-4.jpg "Iniguez, Analytical Compact Modeling Framework for the 2D Electrostatics in Lightly Doped Double-Gate FETs, olid-tate Electronics 69")
5 Device Physics - Operation Principles increasing V ds [3] M. chwarz, T. Holtij, A. Kloes, B. Iniguez, Analytical Compact Modeling Framework for the 2D Electrostatics in Lightly Doped Double-Gate FETs, olid-tate Electronics 69 (1), 72 84, Dresden ept.3, /15
6 Analysis - Device Definition implified geometry of a B-DG-FET Within the TCAD simulation the following models were activated: Fermi distribution incomplete ionization, doping dependency, high field saturation effect on mobility mobility degradation at interface bandgap narrowing effect on effective intrinsic density (old lotboom model) lattice temperature nonlocal tunneling at metal-semiconductor interfaces including chottky barrier lowering thermionic emission Dresden ept.3, /15
7 Analysis - Temperature Impact on Carrier Densities Impact of the temperature on the carrier densities n(e) and p(e) Dresden ept.3, /15
8 Analysis - Temperature Impact on Carrier Densities The density-of-states, Fermi level and Fermi distribution function can affect the effective mass of B- and improve transport by enhancing the tunneling transport (transport bottleneck versus tunneling enhancement) Dresden ept.3, /15
9 Analysis - Banddiagrams w/wo chottky Barrier Lowering i B-DG-FET with Bn = 0.3eV w/wo BL at the silicon/oxide interface l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
10 Analysis - Banddiagrams w/wo chottky Barrier Lowering i B-DG-FET with Bn = 0.3eV w/wo BL at the silicon/oxide interface l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
11 Analysis - imulation vs. Measurement Pti B-DG-PFET 320nm measurements [4] vs. simulation model [4] L. Hutin et al., Dual Metallic ource and Drain Integration on Planar ingle and Double Gate OI C down to 20nm: Performance and calability Assessment, IEDM, 1 4, December, Dresden ept.3, /15
12 Analysis - imulation vs. Measurement Pti B-DG-PFET 70nm measurements [4] vs. simulation model [4] L. Hutin et al., Dual Metallic ource and Drain Integration on Planar ingle and Double Gate OI C down to 20nm: Performance and calability Assessment, IEDM, 1 4, December, Dresden ept.3, /15
13 Analysis - Temperature Impact on i and GaAs i B-DG-FET: I FETE - V g and gm - V g with Bn = 0.3eV l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
14 Analysis - Temperature Impact on i and GaAs III-V B-DG-FET GaAs: I FETE - V g and gm - V g with Bn = 0.3eV l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
15 Analysis - Temperature Impact on i and GaAs i and III-V B-DG-FET GaAs: I FETE - V g and gm - V g with Bn = 0.3eV l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
16 Analysis - Temperature Impact on i and GaAs Density-of-states strongly affects the field emission current making the GaAs device having a smaller drive current! Dresden ept.3, /15
17 Analysis - Impact V ds with/without BL Influence of V ds on I TE - V g w/wo BL with Bn = 0.3eV l ch = 100nm, t ch = 20nm, t ox,io2 = 2nm Dresden ept.3, /15
18 Analysis - Impact V ds with/without BL Influence of V ds on I TE - V g, I FE - V g w/wo BL with Bn = 0.3eV l ch = 100nm, t ch = 20nm, t ox,io2 = 2nm Dresden ept.3, /15
19 Analysis - Temperature Impact on BL BL effect vs. temperature for Bn = 0.3eV hown is the effective B at the center and at the silicon/oxide interface l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm Dresden ept.3, /15
20 Analysis - B-DG-FET vs. conventional DG-FET B-DG-FET w BL vs. conv. DG-FET: Id - Vg of I FETE with Bn = 0.3eV vs. I DD with /D doping N D = 1e20cm-3, l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm. l source = 5nm and l = 5nm Dresden ept.3, /15
21 Analysis - B-DG-FET vs. conventional DG-FET Improvement at RT by BL and due to voltage drop at the B maller field in the channel and a reduced velocity saturation At LT current improve due to enhancement of the mobility from reduced phonon scattering Dresden ept.3, /15
22 Analysis - B-DG-FET vs. conventional DG-FET B-DG-FET w BL vs. conv. DG-FET: Id - Vg of I FETE with Bn = 0.3eV vs. I DD with /D doping N D = 1e20cm-3, l ch = 22nm, t ch = 10nm, t ox,io2 = 2nm. l source = 5nm and l = 5nm Dresden ept.3, /15
23 Analysis - B-DG-FET vs. conventional DG-FET Improvement at RT by BL and due to voltage drop at the B maller field in the channel and a reduced velocity saturation At LT current improve due to enhancement of the mobility from reduced phonon scattering Dresden ept.3, /15
24 Conclusion maller m* reduced drive current due to density-of-states effects BL effect influences the dominating conduction mechanism total amount of current especially in the low temperature regime BL can significantly improve B-FET performance particular at low temperatures Currents for the B and conventional FETs were found to be comparable At RT higher currents for the ideal B-FET large voltage drop at the B increased mobility Analysis and comparison of IV and III-V chottky barrier offer interesting material combinations to boost the device performance Dresden ept.3, /15
25 Acknowledgements The authors would especially like to thank Paul Pfaeffli and Guenther Zandler from ynopsys Inc. for their fruitful dicussions and support during the simulation setup THANK YOU FOR YOU ATTENTION Dresden ept.3, /15
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