A New Model of Gate Capacitance as a Simple Tool to Extract MOS Parameters

Transcription

1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY A New Model of Gate Capacitance as a Simple Tool to Extract MOS Parameters Luca Larcher, Student Member, IEEE, Paolo Pavan, Member, IEEE, Fabio Pellizzer, Gabriella Ghidini Abstract This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-si depletion charge quantization includes temperature effects. A new fast iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, poly-si doping) oxide field, surface potentials at the Si/SiO 2 at the poly-si/sio 2 interfaces. Its effectiveness will be demonstrated by comparing oxide field oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed we suggest improvements to reduce their errors. The agreement between simulation experimental data is good without the need of any free parameter to improve the fitting quality for several gate substrate materials combinations. Finally, a simple law to estimate substrate poly-si doping in n+/n+ MOS capacitor from curves is proposed. Index Terms Capacitance measurements, dielectric films, electric fields, simulations. NOMENCLATURE Oxide thickness. Electric field within the oxide. Substrate surface doping. Poly-gate surface doping. Substrate surface potential. Poly gate surface potential. Gate-body capacitance. Voltage applied between gate body. Flatb voltage. Threshold voltage. Electron charge. Silicon permittivity. SiO permittivity. Electric field in the silicon at the interface with oxide. Mean effective electric fields for quantized carriers. Maximum electric due to depletion charge. Fermi level. Energy bgap. Fermi potential (substrate). Fermi potential (poly-si gate). Manuscript received September 29, 2000; revised November 13, This work was supported in part by CNR-Italy, Progetto Microelettronica 5% P.F. Madess II. The review of this paper was arranged by Editor G. Baccarani. L. Larcher P. Pavan are with Dipartimento di Scienze dell Ingegneria, Università di Modena e Reggio Emilia INFM, Modena, Italy ( larcher@dsi.unimo.it). F. Pellizzer G. Ghidini are with Central R&D/ST Microelectronics, Agrate Brianza, Italy. Publisher Item Identifier S (01) Boltzmann s constant. Temperature. Thermal voltage. Poly-Si charge. Substrate capacitance. Poly-Si gate capacitance. Oxide capacitance. Effective mass of electrons/holes. Density-of-states effective mass of electrons/holes. Free electrons mass. Hole density. Electron density. Degeneracy factor. Subb energy levels. Subb carrier density. Subb charge centroid. Total carrier density. Global charge centroid. Enhancement of surface potential due to quantum effects. Work function. Surface potential in the depletion region. Substrate charge. Parasitic charge. Depletion charge. Depletion capacitance. th zero of the Airy s function. Normalized Planck s constants. I. INTRODUCTION THE EXACT knowledge of the oxide thickness electric field within the oxide is essential when dealing with nonvolatile memory cells as E PROM Flash. In fact, Fowler Nordheim (FN) current depends strongly on oxide thickness electric field, so do write/erase speed retention properties of nonvolatile memories. In addition, an accurate oxide thickness evaluation is also needed for highperformance MOS field-effect transistors (MOSFETs) for advanced integrated circuits: the transconductance the gain of MOS inverter amplifier stages are inversely proportional to. However, the estimate of is still solved either by approximate methods affected by large errors, or by numerical methods particularly expensive for their computational effort not easily applicable to the stard methodologies for parameter extraction adopted in semiconductor industry. The use of numerical techniques is mainly due to difficulties in modeling charge quantization, that is no more negligible in ultrathin oxides needed in current future device generations [1], [2] /01$ IEEE

2 936 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 Many methods have been already proposed in the literature to evaluate oxide thickness. Some of these treat charge quantization using a rigorous approach, but they suffer excessive complexity, thus requiring numerical solutions [3] [5]; others provide bias dependent [6], [7], as reported also in [2] that, however, proposes an analytical law that depends on a parameter which is difficult to evaluate; others do not take into account poly-si depletion [8]; [9] gives as a result of complex iterative calculations. Although an exact knowledge of is necessary for a correct simulation of FN current, the oxide field is generally calculated by approximate methods neglecting charge quantization effects (enhancement of the surface potential with respect to the classical treatment). In [10] an extension of the Berglund s integration method [11] has been proposed to determine the potential drop across the oxide,, leading to dependent value. A more rigorous theoretical treatment has been followed by Suñè et al. in [7], although the analytical expression proposed for does not hold true for every gate-body voltage. Moreover, the calculation of surface potential by an iterative approach including charge quantization phenomena has been discussed in [12], while no effective methods to determine the dopings of poly, of substrate for every gate body materials have been proposed till now in the literature. Since the estimate of one of the aforementioned MOS parameters implies usually the correct knowledge of the others, the parameter extraction has to be processed using a global approach, as suggested also in [6]. For this reason, we have developed a new simple iterative procedure from which also, the surface potential at the Si/SiO,, the potential at the poly-si/sio interfaces,, are easily simultaneously calculated. This iterative procedure is based on a simple model of the MOS capacitor gate capacitance including poly depletion charge quantization effects. In fact, as the simulation of curves of MOS capacitors requires the correct evaluation of the main MOS system parameters ( the parasitic charge ), the good fitting is an explicit confirmation of the correct estimate of the aforementioned parameters. Thus, are the input variables of this procedure that gives the simulated as output. The fitting of the measured by the simulated one can be improved at each step by properly modifying the input parameters, as their effect on curves is unique. This iterative procedure is stopped when a good agreement between measured simulated curves is achieved, as it corresponds to a correct estimate of the aforementioned MOS parameters. In Section II, the theoretical model on which is based this new MOS parameter extraction procedure will be illustrated. Section III contains a brief description of the experiments the samples used, while Section IV discusses in detail results obtained with our model reviews methods previously proposed in the literature to estimate MOS system parameters. II. MODEL To simplify the theoretical analysis of the simulation model we propose, we will separate the discussion into two parts. First, at a given gate potential, we will calculate by using a iterative approach. Second, we will introduce the new model of the gate capacitance. The theoretical analysis in the following refers to the case of a MOS capacitor with n poly-si gate p-si substrate. However, it is trivial to extend the treatment to capacitors with different gate substrate materials. A., Calculation Procedure In this section, we will describe the iterative procedure to calculate as a function of in a MOS capacitor. This procedure is based on a model including charge quantization phenomena at the Si/SiO interface poly-si depletion effects. The key point of this method consists in the calculation of as a function of. In this way, can be also derived solving (1), which became an equation in one unknown term [10] In (1), the flatb voltage is given by, where is the work function difference between gate substrate materials; takes into account all the parasitic charges per unit area at the Si/SiO interface, is the oxide capacitance per unit area, where is the insulator permittivity. 1) Calculation of as a Function of : To simplify the calculation of as a function of, we split the curve into three main regions, that will be considered separately: Region 1) accumulation, when ; Region 2) depletion, when, where is the threshold voltage; Region 3) inversion, when. Since our model includes quantum phenomena at the oxide/silicon interface, hole electron quantization have to be considered in Regions 1 3, respectively. Instead, classic treatment gives a physical real picture in Region 2, because electron hole concentrations are negligible compared to ionized donors [7]. Thus, the total charge in Region 2 is given by the depletion charge the surface potential in the depletion region can be derived from the Gauss s law applied to the Si/SiO interface,, where are the electric field in the silicon the silicon permittivity, respectively [13] [15] On the contrary, in Regions 1 3, the classic treatment does not give an accurate physical picture, as charge quantization phenomena at the oxide/silicon interface need to be included to obtain correct results [1], [3], [16] [22]. In fact, electrons in inversion (or holes in accumulation, [1] [3]) are distributed in energetic subbs within the conduction b where every subb corresponds to a quantized level for the motion of the carriers in the direction normal to the surface [1], [3], [17] [22]. Still, a proper quantum mechanical description predicts that carriers will move some distance away from the silicon/oxide interface, leading to a gate capacitance reduction to a surface potential enhancement with respect to what predicted by the classic model [1], [3], [18] [22]. Since the theoretical treatment (1) (2)

3 LARCHER et al.: NEW MODEL OF GATE CAPACITANCE 937 of quantum phenomena is a rather complex problem involving a self-consistent solution of Schrödinger s Poisson s equations that can be solved only by numerical methods, we will approximate the exact electrostatic potential by a linear potential, to obtain an analytical solution [1], [20] [22]. Thus, the analytical expressions of the quantized energy levels the charge centroid in the direction normal to the surface are given by (3) (4) for electrons holes is the normalized Planck s constant, is the th zero of the Airy s function ( ), where the index indicates the sub-b considered, is the electron/hole effective mass in the direction normal to the surface [1], [12], [20] [22]. The mean value of the effective electric field for the carriers in the silicon,, is given by for inversion (electrons) accumulation (holes), respectively [1], [20] [22]. is the peak field due to the depletion charge which occurs approximately when, where is the Fermi potential is the thermal voltage [15]. The surface densities of electrons holes of each subb are given by (5) (6), where the difference between the Fermi level the electron subb is between the hole subb the Fermi level is, respectively [1], [13], [21], [22]. where energy bgap; Boltzmann s constant; temperature; density-of-states effective mass; degeneracy factor [1], [12], [20] [22]. For a crystal silicon with orientation, the electron effective masses are the usual longitudinal transverse masses ( ) the density-of-states effective masses are given by, as the degeneracy factor are [1], [20]. For simplicity, light heavy hole bs have been considered parabolic despite of their warped shape. Thus, the hole effective masses assumed in the model are, respectively [3]. The effective masses increase strongly with temperature [23], [24]. Therefore, the values we use are (3) (4) (5) (6) larger than what is usually proposed in the literature, which refers to 0 K. Moreover, the values assumed provide the correct three-dimensional state density, as suggested in [3]. The total electron (hole) charge density the distance from the interface of its centroid are given by [1], [21], [22]. The nonzero value of the quantized charge centroid implies that a greater surface potential than predicted by the classic model has to be expected [1], [12], [20] [22]. Thus, by assuming that the inversion (electron) accumulation (holes) charges are sheets of infinitesimal width (a delta function) placed at distance from the Si/SiO interface, the enhancement of the surface potential determined by quantum effects is given by (7) [12], [20] [22] However, themselves are function of the surface potential, given by in depletion-inversion accumulation regions, respectively, hence (7) represents also an implicit equation in. To determine we have to solve (7), whose complexity depends strictly on the number of subbs considered. As in [1], we have verified that by considering the three lowest energy levels a negligible error occurs. However, since the occupation probability of the highest subbs is larger at low fields, the error of considering only the lowest three subbs is larger when the field is lower (in terms of gate voltage, when ). 2) Calculation of as a Function of : The calculation of the surface potential at the poly-si/sio interface has two main differences from calculation. First, it is very difficult to deplete completely the poly-si gate for the range of voltage usually applied, as the poly-si doping level is very high in advanced devices. Moreover, it is impossible to invert completely the poly-si, as the minority carriers (holes) cannot be generated or provided by external sources, differently from the case of the Si-substrate, where source drain wells provide electrons to form the inversion layer at the p-si/sio interface. Thus, instead of going in inversion, at high the poly-si gate goes in deep depletion conditions. Second, no charge quantization occurs at the poly-si/sio interface, since the high doping of the poly-si in advanced devices implies that in accumulation the b-bending at the interface with the oxide cannot be so strong to contain quantized subbs [25]. In fact, at very high doping levels ( cm, as we have directly verified) the accumulation potential well is narrow enough that all the subbs are squeezed out of the potential well. Therefore, no carrier quantization phenomena have to be considered to estimate the surface potential at the poly-si/sio, the alone classic treatment is sufficient to determine. Following the classic theory, the charge at the poly-si/sio interface is given by (8), which has been derived from [15] by canceling the term taking into account the inversion charge contribution. is positive when (7) (8)

4 938 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 The poly-si Fermi potential is given by for the poly-si doping level characterizing current future technologies. Finally, can also be determined by solving the charge neutrality equation, where the substrate charge is given by B. The Gate to Body Capacitance This section describes the expression of the gate to body capacitance which consists of the oxide capacitance in series with the substrate capacitance the poly-si capacitance such that [1], [3], [10], [15], [17], [18], [20]. (9) (10) It is worth pointing out that depend on the silicon poly surface potentials, which have to be evaluated by solving numerically (7). approaches the ideal oxide capacitance only when are much larger than. Thus, it is more important to take into account a correct model of as decreases. In fact, with thinner oxide thickness increases with respect to, their contribution to cannot be neglected anymore. As previously anticipated, for usual substrate poly-si doping values charge quantization at the Si/SiO interface takes place determining the penetration of the charge centroid in the Si-substrate more than that predicted by the classical theory [2], [15], [18]. Thus, the expressions of have been calculated by differentiating (9) (8), respectively (12), shown at the bottom of the page. is the capacitance due to the depletion charge. Finally, be determined by inserting (12) (11) in (10). (11) can III. SAMPLES AND EXPERIMENTS Samples used in this work are MOS capacitors manufactured at ST-Microelectronics. Devices are capacitors with n polysilicon gate on p-si substrate, surrounded by a n ring, to allow electron injection under positive gate voltages. Oxides have been grown either in wet ambient at 800 C nitrogen annealed. Three oxide thickness have been grown, nm, nm, nm, as determined from optical measurements. Sample areas are cm, cm, cm for nm, nm, nm, respectively. A different sample of area cm without the NO nitridation treatment has also been included. STI isolation, dual-gate technology, salicidation, five metallization levels final passivation have been performed. The capacitance voltage measurements were performed at different frequencies (1 10 khz), with n ring shorted to grounded p-substrate. Moreover, n /n capacitors with 6, 6.32, 6.95, 7.22 nm have also been used (area cm ). This oxide is grown on As implanted substrate in steam ambient followed by a 10 min annealing in N at 1000 C. measurements were performed at 1 khz. IV. RESULTS AND EXPERIMENTAL FITTING PROCEDURE The model we propose allows a correct simulation of curves measured on MOS capacitors with different gate materials (Al, n poly-si, p poly-si) substrate types (p-si, n-si, n poly-si). As previously anticipated, the MOS system parameters, are the input variables of our model giving the simulated as output. Since the fitting of the experimental curves is also an explicit confirmation of the correct estimate of the aforementioned MOS parameters, we have developed an iterative procedure which permits to evaluate them simultaneously by comparing the measured curve to the simulated one. This procedure which is stopped when a good agreement between measurements simulations is achieved, permits to improve the fitting of the measured curve by properly tuning at each iteration step. In this way, such parameters act as a fitting parameters used to reduce the differences between simulations measurements. As every single MOS parameter has an unique effect on curves, the task of achieving the best fitting is (12)

5 LARCHER et al.: NEW MODEL OF GATE CAPACITANCE 939 Fig. 1. Effects of MOS parameters on simulated C 0 V on n+-poly-si/p-si capacitors. (a) Effect of oxide thickness: T = 5:5; 6:0; 6:5 nm. (b) Effect of substrate doping: N =52 10 ; ; 2: (cm ). (c) Effect of poly-si doping: N =52 10 ; ; (cm ). very fast simple. For example: 1) the increase of results in a shift toward lower capacitance values of the simulated curve in accumulation inversion regions, as shown in Fig. 1(a); 2) the reduction of produces the narrowing of the depletion dip the lowering of the minimum capacitance value [see Fig. 1(b)]; 3) the decrease of enhances the slope of the curve in the inversion region ( )as shown in Fig. 1(c). An example of results achieved by our model is shown in Fig. 2, where measured (solid lines) simulated (symbols) curves on n /p capacitors are depicted for different oxide thickness ( 5.82 nm). The fitting is excellent despite of the approximation assumed in the model. No free parameters have been included to improve the fitting quality. As expected from the process data, no parasitic charge,, interfacial states have been considered at the Si/SiO interface to obtain results shown in Fig. 2. The slight differences between measurements simulations appearing in the transition regions (from accumulation to depletion from depletion to inversion) are mainly due to the fact that at low, many subbs are populated our model includes only the three with the lowest energies [1]. Further examples of the fitting capabilities of the model are shown in Fig. 3(a) (b), where curves on n poly Si/n -Si capacitors are considered. The quality of the fitting is still excellent, only for V a little difference appears between measurements simulations it is due to the presence of holes at the poly-si/sio interface. In fact, minority carriers generated in this condition by the strong surface potential drop, do not recombine completely, so that the poly-si gate is in a transition status going from deep depletion to weak inversion [15]. Thus, the inversion carrier density depends strictly on the measurement frequency. For this reason, to avoid excessive complications, poly-si gate inversion carriers have not been taken into account, as explained in Section II-A2. However, despite the approximation taken,

6 940 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 Fig. 2. C V curves simulated measured on n+/p MOS capacitors of different oxide thickness (T = 2:75; 3:42; 5:82 nm). Solid line: measured; circles : simulated by our model. results shown in Fig. 3(a) (b) confirm the effectiveness on this model as a tool to reproduce curves also on n poly Si/n -Si capacitors, which have not received extensive consideration in the literature. From these curves we can deduce precious information about. In fact, since the minimum of at negative indicates the complete depletion of the n substrate [see Fig. 3(a)], in these conditions the total charge in the silicon is given by the alone depletion contribution, (in fact the inversion charge is negligible [15]). Thus, is derived from the Gauss s law applied to the Si/SiO interface, that is, as in complete depletion holds true [15]. By inserting expression in (1) neglecting, the following approximate expression of has been derived assuming (13) By applying (13) on curves shown in Fig. 3(a) ( ), the estimate ( cm nm cm nm) agrees pretty well with that obtained by our model. The error occurring is 7% in the worst case despite the approximation assumed. Unfortunately, (13) produces a no negligible error if interfacial states are present at the Si/SiO interface. In fact, they modify the curve shape (for example, by increasing ), thus changing the estimate. Thus, the error induced in the evaluation of can reach 50 60% for high interfacial state density ( ev cm ). Finally, since (13) needs the exact knowledge of the real oxide thickness, particular care must be taken in determining, as its wrong estimate doubles the error in. However, the deduction of an analytical law like (13) to estimate is excessively complex. This is due mainly to two reasons: 1) the poly-si layer does not go in inversion conditions (as the Si-substrate),, therefore, the value at which the poly-si is completely (but not deeply) depleted cannot be accurately estimated; 2) the surface potential at Si/SiO interface cannot be neglected any more, thus avoiding any simple expression like (13) for. In any case, some qualitative considerations about can be done by inspecting only the shape of curves. In fact, as shown in Fig. 3(b), the slope (absolute value) of curves for is inversely proportional to, respectively. Thus, from the shape of the curves shown in Fig. 3(b) we can quickly deduce that. Moreover, the ratios between the different values can be approximately evaluated. Moreover, the model we propose is able to reproduce successfully the behavior of curves also at low temperatures. The shape changes occurring at low temperatures in curves can be briefly described as an enlargement of the depletion dip a lowering of the minimum capacitance value (see Fig. 4). These results agree qualitatively with what observed experimentally. These changes are mainly due to the decrease of the effective carrier density occurring at low temperatures (the so called freeze-out of carriers [26]), which shifts toward higher values (by considering absolute values) the points of transition from depletion to both inversion accumulation. On the other h, curve changes cannot be due to variations of,, as we have directly verified they are insensitive to temperature, as confirmed by Riccò Fischetti in [27]. V. AND CALCULATION METHODS As described in Section II-A, with this model we are able to calculate, as a function of (see Fig. 5). As reported also in [7], depend also on. However, any analytical expression of dependence on these parameters is practically impossible to achieve in the general case. As an example, in Fig. 5 the oxide thickness effect on is shown. Both (absolute value) increase with decreasing, whereas decreases, as reported also in [10]. Similar results illustrating effects on (which can be derived quickly by applying our model) are not reported here for brevity. Of course, with our model it is also immediate to calculate the electric field within the oxide, since it is given by. An interesting method to estimate, based on a much general theoretical approach that is an extension of the Berglund s integration [11], has been proposed by Depas et al. [10]. is simply given by (14), where is the experimental gate to body capacitance per unit area measured at high frequencies (1 10 KHz) (14)

7 LARCHER et al.: NEW MODEL OF GATE CAPACITANCE 941 Fig. 3. Measured (solid lines) simulated (symbols) CV curves on n+/n+ MOS capacitors (area = 1210 cm ). (a) T = 6:32; 7:22 nm. (b) Nsub = 1:4; 2:2; 4:0; 9: cm Fig. 4. CV curves simulated on n+/p MOS capacitors (area =4: cm, T =5:75 nm, N =52 10 cm N =32 10 cm ) at different temperatures (T = 100K, 200K, 300K). Unfortunately, the correct estimation of requires the knowledge of (to calculate ), which is an input parameter has to be evaluated with other methods. Thus, to eliminate the dependence on (which is a parameter difficult to evaluate), we have changed (14) in (15), where can be directly determined from the measurements alone (15) Oxide fields evaluated by our model (solid lines) by (15) (dashed line) are shown in Fig. 6(a) (b) for two different oxide thickness. As shown in Fig. 6(a) (b), the modified Fig. 5. Potential drop across the oxide surface potentials at Si/SiO poly-si/sio interfaces estimated by our model on two different MOS n+/p capacitors. Solid lines: T = 5:82 nm, N = cm, N = 1: cm, area = 4: cm ; dashed lines: T = 3:42 nm, N =52 10 cm, N =1:3210 cm, area =4: cm. Depas Berglund s method underestimates the oxide field calculated by our model, the difference between these two methods increases with decreasing. This is due to the fact that (15) is derived following the classical treatment, thus neglecting quantum phenomena [10]. Therefore, the error occurring by using the Depas Berglund s methods becomes larger as is thinner, since the effects of quantum phenomena on are more evident. Moreover, as shown in Fig. 6(a) (b), the difference between estimated by our model (15) increases also with increasing. Even in this case, this is due to the neglected quantum phenomena. In fact, by referring to (14),

8 942 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 Fig. 6. Oxide field evaluated on n+/p MOS capacitors [(a) T = 5:82 nm (b) T = 3:42 nm] by our model (solid line) modified Berglund s method [10] (dashed line). since is classically calculated (by using the physical, see [2]), it overestimates the effective oxide capacitance, so that the oxide field is underestimated. Of course, as is constant in the expression [see (14)], the error is proportional to. Finally, it is worth noting that the Depas Berglund s method can produce further errors if the curves are measured on samples affected by a large amount of interfacial states, whose effects have to be properly taken into account. Another method to estimate that can be compared to that evaluated by our model, has been derived from [15] [2]. As suggested by Tsividis [15], simulations obtained following the classic theory can be corrected to include charge quantization phenomena by considering the effective oxide capacitance in place of the physical oxide capacitance (see [2]), where the quantized charge centroid is given by (16) [2], [15] (16) is a fitting parameter, are the depletion inversion charges, respectively [15]. As (16) holds only in the inversion region, we have extended it to accumulation region by assuming that, where is the accumulation charge [15]. The enhancement of the surface potential due to quantum effects in inversion accumulation regions is also given by, respectively [see (7)]. Thus, taking into account quantum effects can be achieved by subtracting to the potential drop across the oxide classically calculated [15]. As shown in Fig. 7(a), (symbols) evaluated in this way (which we have called the modified Rios s method) is strongly influenced by the value assumed by. The value of this parameter is not known a priori, since it has to be calibrated by rigorous numerical simulations [2], in literature different values are reported ( (C cm) in [15] (C cm) in [2]). Thus, becomes practically a fitting parameter that can be estimated by comparing simulations to measurements [see Fig. 7(b)] [2]. However, to do so we have to know the correct oxide thickness, that cannot also be estimated by this method (contrarily to what asserted by Rios et al. in [2]), as it depends on itself. By adjusting a good fitting of the experimental data can be obtained [see Fig. 7(b)], although this approach is physically meaningless, since cannot be a fitting parameter but it must be determined by numerical simulations [2]. Anyway, assuming the value of for the best fit, the agreement between measurements simulations can be significantly reduced, in this case the estimated approaches the one determined by our model, as shown in Fig. 7(a). VI. REVIEW OF THE METHODS PROPOSED IN THE LITERATURE TO ESTIMATE As discussed in Section IV, a good fit of experimental curves indicates the correct estimate of,. Therefore, to test the effectiveness of this model as a tool to extract the MOS parameters, we have compared these last ones to the values expected from manufacturing process data TEM measurements. Generally, values estimated by this model agree very well with those expected from manufacturing process data. Particularly, regarding the oxide thickness, our model provides practically the same results given by TEM measurements (see Table I). This confirms the effectiveness of our model as a tool to evaluate MOS parameters to reproduce curves on MOS capacitors with ultrathin oxide. We have reviewed some methods proposed in the literature to estimate (see [6] [8], [28]) by comparing their results with ours. Generally, since many of these methods have to be applied on curves in strong accumulation [8], [28], they are not suitable to extract oxide thickness when nm. In fact, in this case leakage current series resistance cannot be neglected anymore, as they are responsible for the decreasing capacitance in strong accumulation [5]. Therefore, curve

9 LARCHER et al.: NEW MODEL OF GATE CAPACITANCE 943 Fig. 7. (a) Oxide field (b) CV curves evaluated on n+/p MOS capacitors (T =5:82 nm, area =4: cm ) by our model the modified Rios s method [2]. (a) Solid line: our model; box, 2 : simulated by the modified Rios s model with, B =12 10 B =3:5210, respectively. (b) Solid line: measured; circles : simulated by our model; box, 2 : simulated by Tsividis Rios s model with B =12 10 B =3:5 2 10, respectively [2], [15]. TABLE I COMPARISON BETWEEN OUR MODEL AND OTHER METHODS TO ESTIMATE T FROM CV CURVES. VALUES ARE EXPRESEED IN nm shape is modified compared to that of thicker, they cannot be applied anymore [8], [28], as they do not take into account tunneling conductance series resistance. Although also our model does not take into account tunneling conductance series resistance, it provides a correct oxide thickness estimate due to the fact that parameter extraction procedure is based on the fitting of the entire curves, range can be narrowed so that leakage current series resistance effects can be neglected. The method proposed by Riccò et al. [6] applied to our samples overestimates systematically the correct (see Table I). This is due to two reasons: 1) the poly-si depletion is not correctly taken into account; 2) the charge quantization phenomena are neglected whereas they have to be considered also in flatb conditions, as reported by Pacelli et al. [19]. On the other h, by assuming in strong accumulation, we obtain a pretty good estimate of the oxide thickness by simply considering. A bias dependent is achieved, whose minimum (reported in Table I) is closer to the correct value than that estimated by [6]. As shown in Table I, this simple calculation overestimates because charge quantization phenomena are neglected. Thus, the effective oxide thickness (see [2]) is evaluated in place of the physical one. The algorithm developed by Maserjian et al. [8] underestimates strongly the correct (see Table I). A large error (15% in the best case) occurs using [8], contrarily to what asserted in [9]. This is mainly due to four reasons: 1) this method suffers the three-significant-digit-limit of experimental curves [9]; 2) this algorithm is very sensitive to calculation, thus requiring particular care in performing the derivative measurements [9]; 3) it has to be applied at very low temperature; 4) charge quantization phenomena ( ) are not successfully taken into account, as demonstrated by the fact that the error is larger with thinner (error % with nm error % with nm). In fact, the ratio increases steeply with decreasing oxide thickness. With the method developed by McNutt et al. [28], extracted shows excessive variability in the range considered. As for the Maserjian s method, this is due to the three-significant-digit-limit of experimental data the high sensitivity of calculation. In the best case, the error in estimate is almost 5 10%. It is our opinion that the excessive sensitivity to the experimental data ( also to the range considered) of Maserjian s McNutt s methods represents a strong limit for their applicability, as their results became unreliable. Moreover, Maserjian s McNutt s algorithms are also affected by large errors. VII. CONCLUSIONS A new model able to reproduce curves on MOS capacitors with different gate materials substrate types has been

10 944 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 proposed. Our model takes into account both poly-si depletion charge quantization effects through a simplified self-consistent approach. In every case, the agreement between simulation results is excellent. No free parameters are included to improve the fitting quality. Temperature effects are also successfully simulated. Based on this model, a new fast iterative procedure to estimate simultaneously the main MOS system parameters ( ) has been developed. Through this procedure the oxide field, the potential drop across the oxide, the surface potentials at the Si/SiO at the poly-si/sio interfaces can be calculated. extracted by our procedure has been compared to that obtained by two new methods. One of these, which we have derived starting from Berglund s integral [10], provides a estimate differing slightly from ours because the quantum phenomena are neglected. The second one, which is based on simulations obtained following [15] [2], gives an estimate overlapping perfectly with our one, provided that is considered as fitting parameter. To test our models as a tool to extract the MOS parameters, we have compared the extracted by our procedure to that achieved by the most known methods proposed in literature. Generally, all the algorithms reviewed give values that disagree with both our results data from the manufacturing process. Therefore, the model proposed in this paper results the best tradeoff between computational complexity, facility of use correctness of results in order to evaluate the main MOS system parameters. In conclusion, it is worth noting that this model is able to successfully simulate curves also on poly-n gate/n -Si substrate MOS capacitors. These capacitors are frequently used to characterize nonvolatile memories, but there are not many models in the literature. In this case, we have also derived a new analytical expression for extracting the substrate doping directly from measurements. ACKNOWLEDGMENT The authors would like to thank Prof. A. Paccagnella (University of Padova), Prof. L. Reggiani (University of Lecce), Dr. A. Ghetti (STMicroelectronics) for their comments suggestions. Careful comments of the anonymous reviewers have been greatly appreciated. REFERENCES [1] C. Moglestue, Self-consistent calculation of electron hole inversion charges at silicon-silicon dioxide interfaces, J. Appl. Phys., vol. 59, no. 9, pp , [2] R. Rios N. D. Arora, Determination of ultra-thin gate oxide thickness for CMOS structures using quantum effects, in IEDM Tech. Dig., 1994, pp [3] K. S. Krisch, J. D. Bude, L. Mancha, Gate capacitance attenuation in MOS devices with thin gate dielectrics, IEEE Electron Device Lett., vol. 17, pp , Nov [4] C.-H. Choi, J.-S. Goo, T.-Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. Voorde, D. Vook, C.H. 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11 LARCHER et al.: NEW MODEL OF GATE CAPACITANCE 945 Luca Larcher (S 99) was born in Trento, Italy, in He received the Laurea degree in electronic engineering from the University of Padova, Padova, Italy, in Since 1998, he has been pursuing the Ph.D. degree at the Department of Engineering Science, University of Modena Reggio Emilia, Italy. His research activities are in the field of nonvolatile memory cells. Particularly, his interest are on the oxide reliability, the simulation of oxide leakage current, the modeling of E PROM Flash. Fabio Pellizzer was born in He received the B.S. degree in electronic engineering in 1996 from the University of Padova, Italy, with a thesis on characterization reliability of thin gate oxides in MOS transistors. He joined STMicroelectronics, Agrate, Italy, in His work focuses on thin dielectric characterization modeling. Paolo Pavan (M 95) was born in Venice, Italy, in He received the Laurea degree in electrical engineering from the University of Padova, Italy, in 1990, working on latch-up hot-electron degradation phenomena in MOS devices, the Ph.D. degree in impact ionization phenomena in advanced bipolar transistor in 1994 from the University of Padova. He is currently Associate Professor of Electronics at the University of Modena Reggio Emilia, Italy. From 1992 to 1994, he was at the University of California, Berkeley, where he studied radiation effects on MOS devices circuits. Recently, his interest has been in the characterization modeling of Flash memory cells on the development of new nonvolatile cells. He authored coauthored technical papers, invited papers, two chapters in books. Gabriella Ghidini received the Laurea degree in physics from the University of Parma, Italy, in 1979 the Ph.D. degree in physics in 1983 from the City College of New York. In 1983, she joined the STMicroelectronics, Agrate, Italy, working in the physics group of the Central R&D Department. In 1987, she moved to the Non-Volatile Memory Process Development group within the Central R&D becoming the Leader of the Dielectric Reliability group. Her research activities include failure wear-out mechanisms of all active dielectric of EPROM, Flash EEPROM, E2PROM devices the evaluation of new technologies for the future generations. She has published more than 60 technical papers in international journals conferences.