Graphene based FETs. Raghav Gupta ( )

Transcription

1 1 Graphene based FETs Raghav Gupta ( ) Abstract The extraordinary electronic properties along with excellent optical, mechanical, thermodynamic properties have led to a lot of interest in its possible applications. Due to zero band gap in large area Graphene, its usability as channel material in MOSFETs has been limited. This paper presents the basic physics of Graphene and describes a few methods used by researchers to create band gaps in Graphene. A few implementations of Graphene in FETs and their results are also presented along with a model for the current and charge densities in top gated Large Area Graphene FETs. Index Terms Graphene FET, ends to form the source and drain contacts. The dual gate configuration consists of a dielectric deposited on top of the flake to form another gate and thereby allowing both gates to control free carrier concentration in the channel. The top gate Graphene FET can be fabricated by growing epitaxial Graphene on top of a SiC layer. On top of the Graphene layer a dielectric layer is deposited (usually Al 2O 3) to form the top gate. Graphene grown on the C face of SiC has been shown to display higher values of mobility [4] and can be used to make better devices although creating monolayer and bilayer on Silicon face is easier which makes it more suitable for commercial applications. I. INTRODUCTION Graphene is a planar two dimensional single layer thick crystalline allotrope of carbon. It forms the building block of one of the most important allotropes of carbon-graphite (also of fullerenes, Carbon nanotubes, charcoal etc.). Graphene consists of sp 2 hybridized carbon atoms connected together in the form of extended benzene ring structures. Due to this structure, Graphene is known to exhibit outstanding electronic properties with recorded electron mobility as high as 250,000 cm 2 V 1 1 [1] s (suspended form). Graphene has also been observed to exhibit exceptional mechanical properties and has been shown to display the highest values of breaking strengths ever recorded (42 N-m -1 [2] ). Apart from this Graphene also exhibits excellent optical properties [3], due to which it finds applications in optical devices such as photo detectors. Another factor that has led to rapid growth of Graphene is the fact that Graphene only requires planar processing technologies similar to the ones already present in the existing CMOS technology. Three typical configurations used in Graphene based Field Effect Transistors are- (i) back gate, (ii) dual gate, (iii) top gate (Fig. 1). The back gate configuration consists of highly doped silicon substrate on top of which a dielectric is deposited followed by subsequent deposition of a Graphene flake which acts as a channel. The flake is contacted at its two Fig. 1. a) Back gate graphene FET b) Dual gate c) Top gate structure with epitaxial graphene on SiC substrate [5]

2 2 II. THEORY Pure Graphene, having a planar honeycomb structure, has zero bad gap. The band structure for Graphene consists of the conduction and valence bands forming conic shapes and intersecting each other at points known as the Dirac points (Fig. 2). The electronic dispersion near these Dirac points at lower energies is linear suggesting that the electrons in Graphene behave as Dirac fermions near theses points and obey the laws of quantum electrodynamics (QED) physics for massless fermions. The equation for the electronic dispersion is: E = ±hv F k x 2 + k y 2 where v f is the Fermi velocity (10 8 cm/sec). This results in the electrons behaving as zero mass particles and thus also exhibiting an interesting phenomena known as the Klein paradox. According to the Klein paradox, fermions obeying the Dirac equation can tunnel through potential barriers with probability one. As a result, the electrons in Graphene do not display localization effects and are hence able to propagate long distances without being scattered (experimentally recorded values range upto micrometers [6] ). Fig. 2 Electronic dispersion in the honeycomb lattice. Left: Energy spectrum. Right: zoom in of bands near Dirac points [7] This zero band gap in pristine Graphene is mainly due to the equivalence of two sub-lattices in the honeycomb structure with adjacent carbon atoms belonging to different sub-lattices. As a result of this, the electrons are prevented from gaining mass and behave as massless fermions obeying the Dirac Equation. This behavior of Graphene does not allow it to be used in Logic circuits. A lot of research has therefore been focused on trying to produce a band gap in Graphene. One of the ways to induce a band gap in Graphene has been by introducing asymmetry in the crystal. Hunt. Et al [8] show that by bringing single layer Graphene in contact with hexagonal Boron Nitride (hbn), an alteration in potential is produced between adjacent carbon atoms due to inter layer van der Waals interaction of the carbon atoms with B and N atoms. This variation in potential between adjacent carbon atoms causes the electrons to gain mass thereby creating a band gap between the conduction and valence bands. This property of Graphene allows control of mass of electrons and of band gap which finds use in many applications. Another method used to create band gap in single layer Graphene is by lateral confinement wherein Graphene ribbons of small width are created which result in band gaps of the order of 1.38/W (wwidth) [10]. This method of creating Graphene nanoribbons has been the focus of lot of research and nanoribbons with smooth edges have been created and used to make FETs with large values of cutoff frequencies for possible RF applications. Now, in the primitive Graphene structure, the Fermi energy lies between the conduction and valence bands, hence at the Dirac points. On application of positive voltage the Fermi energy level shifts into the conduction band and as a result the electrons start to populate the conduction band. On the other hand on application of a negative voltage, Fermi level drops below Dirac point and holes start to occupy then valence band. Thus Graphene shows dual behavior in presence of electric field. Novoselov et al [9] have shown that on application of electric field on a few layer Graphene we can observe maximum resistivity at the Dirac point. Typically, in pristine Graphene the resistivity is highest at zero applied gate voltage (however in their experiment the Dirac point attains a positive value due to absorbed water in the Graphene during deposition of SiO 2). They have further showed that the Hall coefficient changes its sign at the Dirac point indicating ambipolar effect of Graphene in electric field similar to that observed in semiconductors. However the conductivity in Graphene approaches zero at the Dirac point due to very small amount of free carriers at that voltage. Another interesting effect observed only in bilayer Graphene (BLG) is the ability to tailor a tunable band gap in it by applying a transverse Electric Field across its two layers (it is the only material to show this effect [10] ). This effect can be used in BLG to create band gaps upto 300 mev [10]. This can be done by stacking a gate electrode on top of BLG along with a layer high k dielectric (usually Al 2O 3). Application of voltage at the gate electrode causes different charge densities in the two layers of Graphene which interact to create a band gap in the material. Experimentally the maximum band gap created via this method is around 250 ev. Similar to single layer Graphene another method to induce a band gap in BLG is

3 3 to break the vertical symmetry by bringing it in contact with foreign atoms, in this case, by introducing dopant atoms in the top layer of BLG. This amount to deposition of charge on the doped layer resulting in asymmetry between the layers, and as a result opening of a band gap. Using these methods FETs based on graphene can be created for use in logic and RF circuits. A. Fabrication of Graphene Graphene for these applications can be produced by several methods [12] - a. Mechanical Exfoliation- Since graphite is made up of sheets of Graphene bonded to each other via van der Waals forces, single to multiple layers of Graphene can be extracted from graphite by repeatedly peeling off with the help of scotch tape. b. Epitaxy Ultrahigh vacuum annealing of SiC crystals leads to sublimation of Si atoms from the substrate leaving behind carbon atoms that rearrange to form Graphene c. Chemical Vapor Deposition- Heavy metals exposed to hydrocarbon gas are heated and lead to diffusion of carbon atoms to metal surface where they precipitate on cooling to form layers of Graphene. d. Chemical Derivation Graphene Oxide which is readily exfoliated in water to form single layer sheets which can be reduced by hydrazine or sodium borohydrate to precipitate Graphene sheets which are insoluble in water. their work propose use of a thin nucleation layer of oxidized Al on top of Graphene to allow growth of dielectric on top of it [14]. This method does not degrade electron mobility in Graphene and as a result they were able to obtain mobility of the order of 8000 cm 2 /V s. In their work, they have fabricated dual gate Graphene FETs with monolayer Graphene films used for the channel. This is one of the most common topologies used for Graphene FETs. The back gate consists of a Silicon substrate on top of which lies SiO 2 as the back gate dielectric, followed by layers of Graphene, Al, Al 2O 3 and finally nickel contacts for the gate and source & drain. On application of the gate voltages to this device, we can expect to observe accumulation of carriers in Graphene and hence a decrease in the resistance of the channel. The maximum resistance of the channel should be observed at the Dirac point where the number of carriers is minimum and the Fermi energy level lies in between the conduction and valence bands exactly at the Dirac points. This is confirmed by results obtained in their work (Fig. 3). B. Graphene FETs The three main topologies used for fabricating Graphene based FETs are as mentioned before-bottom, dual and top gate topologies. For the deposition of dielectric on Graphene layers, normal Atomic Layer Deposition (ALD) is not possible with Graphene because of the hydrophobic nature of Graphene. As a result the Graphene surface is usually functionalized with NO 2 or O 3 etc. to allow deposition of dielectric on top of it. But this method usually results in considerable mobility reduction of the Graphene layer thereby defeating the very purpose of using Graphene. It has also been shown that using SiO 2 as gate dielectric reduces the mobility of electrons and holes by upto 85% [13]. This has been attributed to the participation of π- orbitals in forming van der Waals bonds with the SiO 2 molecules. Hence commonly used dielectrics for top gated Graphene FETs are Al2O3 and HfO 2. Kim et al. in Fig. 3: Rtot vs V TG data measured at different V BG values. Inset: position of V Dirac, TG at different VBG. (TG-top gate, BGback gate) [14] The current voltage relationship of Graphene based FETs (Large area Graphene FETs with zero band gap) typically contains two linear regions (Fig 4.a) (drain current vs the gate voltage). The two linear regions meet at the Dirac point which defines the point of minimum conductivity for the device. Due to this trend of Graphene FETs the drain current vs drain source voltage characteristic (Fig 4.b) shows some peculiar behavior as compared to the conventional MOSFETs. The I DS-V DS characteristic show an initial linear region on application

4 4 which corresponds to accumulation electrons in the layer due to positive gate bias and the channel behaves as n- type. As the drain source voltage is increased further the current eventually saturates and on further increase a critical point is reached, wherein further increase of drain bias causes accumulation of holes in the channel and as a result the channel changes from n-type to p-type at the drain end. This gives way to a second linear region in the characteristic unlike conventional MOSFETs where the current eventually saturates. The characteristics at different gate biases can thus intersect giving rise to zero or negative transconductances. This behavior is highly undesirable for applications in circuits. Graphene based FET with on off ratios of currents of around at 20K and about 100 at room temperature. They have used bilayer Graphene as channel material and applied transverse electrical field across it to obtain band gap of the order 130eV (at electric displacement of 2.2 V/cm). To achieve this they have used a high k dielectric namely HfO 2 deposited using atomic layer deposition for the top gate and SiO 2 as dielectric for the bottom gate. This method can be used to further improve Graphene FETs for applications in logic circuits. III. MODEL Lin et al have presented a model for large area zero band gap Graphene FETs [17] which is described below. In general the current in a MOSFET can be written as ID= qρsh(x)v(x)w= qρsh[v(x)]v[v(x)]w Now, we know that electronic dispersion in zero band gap Graphene is linear around the Dirac point: E(K) E CV=E(k)= shv F k Where v F is Fermi velocity, s is 1 in conduction band and -1 in valence band and E CV is the energy of the valence and conduction band (both are equal). We also know that since Fermi energy at no applied bias is E CV itself, therefore E F E CV = -q*v ch. Expression for available states [17] : And density of states: Fig 4 a. Transfer characteristics of two large area Graphene FET b. Output characteristics for large area Graphene FET [20] As we can see, the on off current ratio is poor for large area Graphene FETs. However these FETs can be useful for use in RF circuits where speed matters more than small off current. For application in logic circuits, usually non zero band gap materials such as Graphene nanoribbons or biased bilayer Graphene are used to obtain good on-off currents. For example, Xia et al. in their work have shown a D(E) = 1 dn A de = 2 E Ecv π (hv F ) 2 Therefore the hole density is: Solving, we get: Ecv n = D(E) f(e)de inf

5 5 2 n = π(hv F ) 2 0 inf Thus total charge density is: Q sh = = 2 E exp ( E E de F k B T ) + 1 π(hv F ) inf E 2 0 exp( E+E F k B T )+1 E de exp( E E F k B T )+1 Thus the quantum capacitance of the channel can be written as : C q = dq sh dv ch Hence the current is: v = I D = qρ sh μe 1 + μ E v sat μ ( dv dx ) dv μ ( 1 + dx ) v sat W = qμw Vds 0 ρ shdv Vds 1 L μ v dv 0 sat Modeled characteristics thus obtained are: Using the approximation (q*v ch >> k BT), we get C q = 2q2 π q V ch (hv F ) 2 The previous equation therefore gives us Q sh = 1 2 C qv ch Therefore the carries charge density can be written as: qρ sh = Q sh = 1 2 C qv ch To account for the difference in workfunctions of gate and Graphene, which along with unintentional doping of Graphene and interface trapped charges at Graphene oxide interface causes shift in the Dirac point, we can write effective gate potential as V GS = V GS V GS0 Where V GS0 is the gate voltage at Dirac point. Now to calculate Drain current we need to find the carrier velocity as a function of the field. It has been observed by Meric et al that the maximum carrier velocity in Graphene is limited by interfacial phonon scattering which can be modelled as a phonon of energy hω. The expression for saturation velocity according to them is: ω v sat = (πρ sh ) 0.5+AV2 (x) The carrier velocity is therefore modelled as: Fig 5. Output characteristics of modeled Graphene FET [17] IV. APPLICATIONS OF GRAPHENE The extraordinary properties of Graphene allow its use in a variety of applications. Some possible applications of Graphene are: RF circuits (due to excellent mobility values observed in it) and large cutoff frequencies in Graphene FETs (for example Lin el al have demonstrated in their work, Graphene nanoribbon based FETs with 100GHz cutoff frequencies [18].). Logic circuits (by tailoring a band gap by any of the aforementioned methods) For fabricating transparent electrodes in Photovoltaic technology (due to optical transparency of Graphene coupled with its flexibility as compared to the less transparent and more brittle Indium tin oxide currently used in the industry) As active material in photo detectors, as hole collecting layer of solar cells (due to the non-

6 6 corrosive nature of Graphene oxide as compared to PEDOT:PSS currently being used which corrodes the ITO electrodes [11] ) Interconnect Applications: due to its semi-metallic behavior with high mobility and good flexibility. Graphene can also be used in the future to form supercapacitors due to its large surface area to volume ratio. V. CONCLUSIONS As of now, the use of Graphene in logic circuits is not possible due to low values of on/off currents. It can be used in RC circuits because of its high mobility and high cutoff frequency but the problem of high off currents still prevails which leads to much higher power dissipation than the current CMOS technology which is extremely low powered. With more research it might be possible to create bandgaps in Graphene without sacrificing mobility much and hence create Graphene FETs with high mobility as well as good on/off current ratio. With that, Graphene could be the future material for electronic devices in the coming years. REFERENCES [9] Novoselov, Kostya S., et al. "Electric field effect in atomically thin carbon films."science (2004): [10] Klekachev, Alexander V., et al. "Graphene Transistors and Photodetectors."Electrochemical Society Interface (2013): 63. [11] Singh, Virendra, et al. "Graphene based materials: past, present and future."progress in materials science 56.8 (2011): [12] Vaziri, Sam. Fabrication and Characterization of Graphene Field Effect Transistors. Diss. KTH, [13] Lemme, Max C., et al. "A graphene field-effect device." Electron Device Letters, IEEE 28.4 (2007): [14] Kim, Seyoung, et al. "Realization of a high mobility dualgated graphene field-effect transistor with Al 2 O 3 dielectric." Applied Physics Letters 94.6 (2009): [15] Liao, Lei, et al. "High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors." Proceedings of the national academy of sciences (2010): [16] Xia, Fengnian, et al. "Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature." Nano letters 10.2 (2010): [17] Thiele, S. A., J. A. Schaefer, and F. Schwierz. "Modeling of graphene metal-oxide-semiconductor field-effect transistors with gapless large-area graphene channels." Journal of Applied Physics (2010): [18] Lin, Y-M., et al. "100-GHz transistors from wafer-scale epitaxial graphene."science (2010): [19] Meric, Inanc, et al. "Current saturation in zero-bandgap, top-gated graphene field-effect transistors." Nature nanotechnology 3.11 (2008): [20] Schwierz, Frank. "Graphene transistors." Nature nanotechnology 5.7 (2010): [1] Bolotin, Kirill I., et al. "Ultrahigh electron mobility in suspended graphene." Solid State Communications (2008): [2] Lee, Changgu, et al. "Measurement of the elastic properties and intrinsic strength of monolayer graphene." Science (2008): [3] Misewich, J. A., et al. "Electrically induced optical emission from a carbon nanotube FET." Science (2003): [4] de Heer, Walt A., et al. "Epitaxial graphene electronic structure and transport."journal of Physics D: Applied Physics (2010): [5] Klekachev, Alexander V., et al. "Graphene Transistors and Photodetectors."Electrochemical Society Interface (2013): 63. [6] Novoselov, K. S., A. K. Geim, S. V. Morozov, D. Jiang, Y.Zhang, S. V. Dubonos, I. V. Gregorieva, and A. A. Firsov, 2004, Science306, 666. [7] Neto, AH Castro, et al. "The electronic properties of graphene." Reviews of modern physics 81.1 (2009): 109. [8] B. Hunt et al., Science 340, 1427 (2013); /science